TAS2764 fixes/extensions
Merge series from Martin Povišer <povik+lin@cutebit.org>: First three patches are fixes analogical to those recently done to the TAS2770 driver. Link: https://lore.kernel.org/asahi/20220808141246.5749-1-povik+lin@cutebit.org/T/#t The latter two add IRQ handler to log faults and expose a new control.
This commit is contained in:
Mark Brown
Коммит
d08a0d41ec
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@ -31,11 +31,66 @@ struct tas2764_priv {
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struct gpio_desc *sdz_gpio;
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struct regmap *regmap;
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struct device *dev;
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int irq;
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int v_sense_slot;
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int i_sense_slot;
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bool dac_powered;
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bool unmuted;
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};
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static const char *tas2764_int_ltch0_msgs[8] = {
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"fault: over temperature", /* INT_LTCH0 & BIT(0) */
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"fault: over current",
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"fault: bad TDM clock",
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"limiter active",
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"fault: PVDD below limiter inflection point",
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"fault: limiter max attenuation",
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"fault: BOP infinite hold",
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"fault: BOP mute", /* INT_LTCH0 & BIT(7) */
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};
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static const unsigned int tas2764_int_readout_regs[6] = {
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TAS2764_INT_LTCH0,
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TAS2764_INT_LTCH1,
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TAS2764_INT_LTCH1_0,
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TAS2764_INT_LTCH2,
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TAS2764_INT_LTCH3,
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TAS2764_INT_LTCH4,
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};
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static irqreturn_t tas2764_irq(int irq, void *data)
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{
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struct tas2764_priv *tas2764 = data;
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u8 latched[6] = {0, 0, 0, 0, 0, 0};
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int ret = IRQ_NONE;
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int i;
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for (i = 0; i < ARRAY_SIZE(latched); i++)
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latched[i] = snd_soc_component_read(tas2764->component,
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tas2764_int_readout_regs[i]);
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for (i = 0; i < 8; i++) {
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if (latched[0] & BIT(i)) {
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dev_crit_ratelimited(tas2764->dev, "%s\n",
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tas2764_int_ltch0_msgs[i]);
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ret = IRQ_HANDLED;
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}
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}
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if (latched[0]) {
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dev_err_ratelimited(tas2764->dev, "other context to the fault: %02x,%02x,%02x,%02x,%02x",
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latched[1], latched[2], latched[3], latched[4], latched[5]);
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snd_soc_component_update_bits(tas2764->component,
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TAS2764_INT_CLK_CFG,
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TAS2764_INT_CLK_CFG_IRQZ_CLR,
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TAS2764_INT_CLK_CFG_IRQZ_CLR);
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}
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return ret;
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}
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static void tas2764_reset(struct tas2764_priv *tas2764)
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{
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if (tas2764->reset_gpio) {
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@ -50,34 +105,22 @@ static void tas2764_reset(struct tas2764_priv *tas2764)
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usleep_range(1000, 2000);
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}
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static int tas2764_set_bias_level(struct snd_soc_component *component,
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enum snd_soc_bias_level level)
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static int tas2764_update_pwr_ctrl(struct tas2764_priv *tas2764)
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{
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struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
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struct snd_soc_component *component = tas2764->component;
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unsigned int val;
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int ret;
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switch (level) {
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case SND_SOC_BIAS_ON:
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snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
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TAS2764_PWR_CTRL_MASK,
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TAS2764_PWR_CTRL_ACTIVE);
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break;
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case SND_SOC_BIAS_STANDBY:
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case SND_SOC_BIAS_PREPARE:
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snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
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TAS2764_PWR_CTRL_MASK,
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TAS2764_PWR_CTRL_MUTE);
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break;
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case SND_SOC_BIAS_OFF:
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snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
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TAS2764_PWR_CTRL_MASK,
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TAS2764_PWR_CTRL_SHUTDOWN);
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break;
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if (tas2764->dac_powered)
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val = tas2764->unmuted ?
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TAS2764_PWR_CTRL_ACTIVE : TAS2764_PWR_CTRL_MUTE;
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else
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val = TAS2764_PWR_CTRL_SHUTDOWN;
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default:
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dev_err(tas2764->dev,
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"wrong power level setting %d\n", level);
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return -EINVAL;
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}
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ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
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TAS2764_PWR_CTRL_MASK, val);
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if (ret < 0)
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return ret;
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return 0;
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}
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@ -114,9 +157,7 @@ static int tas2764_codec_resume(struct snd_soc_component *component)
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usleep_range(1000, 2000);
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}
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ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
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TAS2764_PWR_CTRL_MASK,
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TAS2764_PWR_CTRL_ACTIVE);
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ret = tas2764_update_pwr_ctrl(tas2764);
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if (ret < 0)
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return ret;
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@ -150,14 +191,12 @@ static int tas2764_dac_event(struct snd_soc_dapm_widget *w,
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switch (event) {
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case SND_SOC_DAPM_POST_PMU:
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ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
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TAS2764_PWR_CTRL_MASK,
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TAS2764_PWR_CTRL_MUTE);
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tas2764->dac_powered = true;
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ret = tas2764_update_pwr_ctrl(tas2764);
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break;
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case SND_SOC_DAPM_PRE_PMD:
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ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
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TAS2764_PWR_CTRL_MASK,
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TAS2764_PWR_CTRL_SHUTDOWN);
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tas2764->dac_powered = false;
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ret = tas2764_update_pwr_ctrl(tas2764);
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break;
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default:
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dev_err(tas2764->dev, "Unsupported event\n");
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@ -202,17 +241,11 @@ static const struct snd_soc_dapm_route tas2764_audio_map[] = {
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static int tas2764_mute(struct snd_soc_dai *dai, int mute, int direction)
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{
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struct snd_soc_component *component = dai->component;
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int ret;
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struct tas2764_priv *tas2764 =
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snd_soc_component_get_drvdata(dai->component);
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ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
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TAS2764_PWR_CTRL_MASK,
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mute ? TAS2764_PWR_CTRL_MUTE : 0);
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if (ret < 0)
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return ret;
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return 0;
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tas2764->unmuted = !mute;
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return tas2764_update_pwr_ctrl(tas2764);
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}
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static int tas2764_set_bitwidth(struct tas2764_priv *tas2764, int bitwidth)
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@ -485,7 +518,7 @@ static struct snd_soc_dai_driver tas2764_dai_driver[] = {
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.id = 0,
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.playback = {
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.stream_name = "ASI1 Playback",
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.channels_min = 2,
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.channels_min = 1,
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.channels_max = 2,
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.rates = TAS2764_RATES,
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.formats = TAS2764_FORMATS,
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@ -516,6 +549,34 @@ static int tas2764_codec_probe(struct snd_soc_component *component)
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tas2764_reset(tas2764);
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if (tas2764->irq) {
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ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK0, 0xff);
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if (ret < 0)
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return ret;
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ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK1, 0xff);
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if (ret < 0)
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return ret;
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ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK2, 0xff);
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if (ret < 0)
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return ret;
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ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK3, 0xff);
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if (ret < 0)
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return ret;
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ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK4, 0xff);
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if (ret < 0)
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return ret;
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ret = devm_request_threaded_irq(tas2764->dev, tas2764->irq, NULL, tas2764_irq,
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IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
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"tas2764", tas2764);
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if (ret)
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dev_warn(tas2764->dev, "failed to request IRQ: %d\n", ret);
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}
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ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG5,
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TAS2764_TDM_CFG5_VSNS_ENABLE, 0);
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if (ret < 0)
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@ -526,30 +587,33 @@ static int tas2764_codec_probe(struct snd_soc_component *component)
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if (ret < 0)
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return ret;
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ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
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TAS2764_PWR_CTRL_MASK,
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TAS2764_PWR_CTRL_MUTE);
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if (ret < 0)
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return ret;
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return 0;
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}
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static DECLARE_TLV_DB_SCALE(tas2764_digital_tlv, 1100, 50, 0);
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static DECLARE_TLV_DB_SCALE(tas2764_playback_volume, -10050, 50, 1);
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static const char * const tas2764_hpf_texts[] = {
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"Disabled", "2 Hz", "50 Hz", "100 Hz", "200 Hz",
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"400 Hz", "800 Hz"
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};
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static SOC_ENUM_SINGLE_DECL(
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tas2764_hpf_enum, TAS2764_DC_BLK0,
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TAS2764_DC_BLK0_HPF_FREQ_PB_SHIFT, tas2764_hpf_texts);
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static const struct snd_kcontrol_new tas2764_snd_controls[] = {
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SOC_SINGLE_TLV("Speaker Volume", TAS2764_DVC, 0,
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TAS2764_DVC_MAX, 1, tas2764_playback_volume),
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SOC_SINGLE_TLV("Amp Gain Volume", TAS2764_CHNL_0, 1, 0x14, 0,
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tas2764_digital_tlv),
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SOC_ENUM("HPF Corner Frequency", tas2764_hpf_enum),
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};
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static const struct snd_soc_component_driver soc_component_driver_tas2764 = {
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.probe = tas2764_codec_probe,
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.suspend = tas2764_codec_suspend,
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.resume = tas2764_codec_resume,
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.set_bias_level = tas2764_set_bias_level,
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.controls = tas2764_snd_controls,
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.num_controls = ARRAY_SIZE(tas2764_snd_controls),
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.dapm_widgets = tas2764_dapm_widgets,
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@ -585,9 +649,21 @@ static const struct regmap_range_cfg tas2764_regmap_ranges[] = {
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},
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};
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static bool tas2764_volatile_register(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case TAS2764_INT_LTCH0 ... TAS2764_INT_LTCH4:
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case TAS2764_INT_CLK_CFG:
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return true;
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default:
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return false;
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}
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}
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static const struct regmap_config tas2764_i2c_regmap = {
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.reg_bits = 8,
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.val_bits = 8,
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.volatile_reg = tas2764_volatile_register,
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.reg_defaults = tas2764_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(tas2764_reg_defaults),
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.cache_type = REGCACHE_RBTREE,
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@ -641,6 +717,7 @@ static int tas2764_i2c_probe(struct i2c_client *client)
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return -ENOMEM;
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tas2764->dev = &client->dev;
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tas2764->irq = client->irq;
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i2c_set_clientdata(client, tas2764);
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dev_set_drvdata(&client->dev, tas2764);
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@ -33,6 +33,10 @@
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#define TAS2764_VSENSE_POWER_EN 3
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#define TAS2764_ISENSE_POWER_EN 4
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/* DC Blocker Control */
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#define TAS2764_DC_BLK0 TAS2764_REG(0x0, 0x04)
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#define TAS2764_DC_BLK0_HPF_FREQ_PB_SHIFT 0
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/* Digital Volume Control */
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#define TAS2764_DVC TAS2764_REG(0X0, 0x1a)
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#define TAS2764_DVC_MAX 0xc9
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@ -87,4 +91,23 @@
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#define TAS2764_TDM_CFG6_ISNS_ENABLE BIT(6)
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#define TAS2764_TDM_CFG6_50_MASK GENMASK(5, 0)
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/* Interrupt Masks */
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#define TAS2764_INT_MASK0 TAS2764_REG(0x0, 0x3b)
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#define TAS2764_INT_MASK1 TAS2764_REG(0x0, 0x3c)
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#define TAS2764_INT_MASK2 TAS2764_REG(0x0, 0x40)
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#define TAS2764_INT_MASK3 TAS2764_REG(0x0, 0x41)
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#define TAS2764_INT_MASK4 TAS2764_REG(0x0, 0x3d)
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/* Latched Fault Registers */
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#define TAS2764_INT_LTCH0 TAS2764_REG(0x0, 0x49)
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#define TAS2764_INT_LTCH1 TAS2764_REG(0x0, 0x4a)
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#define TAS2764_INT_LTCH1_0 TAS2764_REG(0x0, 0x4b)
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#define TAS2764_INT_LTCH2 TAS2764_REG(0x0, 0x4f)
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#define TAS2764_INT_LTCH3 TAS2764_REG(0x0, 0x50)
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#define TAS2764_INT_LTCH4 TAS2764_REG(0x0, 0x51)
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/* Clock/IRQ Settings */
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#define TAS2764_INT_CLK_CFG TAS2764_REG(0x0, 0x5c)
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#define TAS2764_INT_CLK_CFG_IRQZ_CLR BIT(2)
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#endif /* __TAS2764__ */
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