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Merge branch 'hisi/soc' into next/soc 

* hisi/soc:
  ARM: dts: rename hi4511 dts file
  ARM: hisi: remove init_time
  ARM: hisi: rename hi3xxx to hisi
  ARM: dts: enable clock binding on Hi3620
  ARM: hi3xxx: add hotplug support
  ARM: hi3xxx: add smp support
  ARM: config: add defconfig for Hi3xxx
  ARM: config: enable hi3xxx in multi_v7_defconfig
  ARM: dts: enable hi4511 with device tree
  ARM: hi3xxx: add board support with device tree

Signed-off-by: Kevin Hilman <khilman@linaro.org>
This commit is contained in:
Kevin Hilman 2014-01-08 13:55:26 -08:00
Родитель e05f9ac42c 0cfb1c8bec
Коммит d0f2a5ba07
14 изменённых файлов: 1725 добавлений и 0 удалений
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32
Documentation/devicetree/bindings/arm/hisilicon/hisilicon.txt Normal file
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@ -0,0 +1,32 @@
Hisilicon Platforms Device Tree Bindings
----------------------------------------------------
Hi4511 Board
Required root node properties:
- compatible = "hisilicon,hi3620-hi4511";
Hisilicon system controller
Required properties:
- compatible : "hisilicon,sysctrl"
- reg : Register address and size
Optional properties:
- smp-offset : offset in sysctrl for notifying slave cpu booting
cpu 1, reg;
cpu 2, reg + 0x4;
cpu 3, reg + 0x8;
If reg value is not zero, cpun exit wfi and go
- resume-offset : offset in sysctrl for notifying cpu0 when resume
- reboot-offset : offset in sysctrl for system reboot
Example:
/* for Hi3620 */
sysctrl: system-controller@fc802000 {
compatible = "hisilicon,sysctrl";
reg = <0xfc802000 0x1000>;
smp-offset = <0x31c>;
resume-offset = <0x308>;
reboot-offset = <0x4>;
};

2
arch/arm/Kconfig
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@ -951,6 +951,8 @@ source "arch/arm/mach-gemini/Kconfig"
source "arch/arm/mach-highbank/Kconfig"
source "arch/arm/mach-hisi/Kconfig"
source "arch/arm/mach-integrator/Kconfig"
source "arch/arm/mach-iop32x/Kconfig"

1
arch/arm/Makefile
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@ -159,6 +159,7 @@ machine-$(CONFIG_ARCH_EP93XX) += ep93xx
machine-$(CONFIG_ARCH_EXYNOS) += exynos
machine-$(CONFIG_ARCH_GEMINI) += gemini
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_HI3xxx) += hisi
machine-$(CONFIG_ARCH_INTEGRATOR) += integrator
machine-$(CONFIG_ARCH_IOP13XX) += iop13xx
machine-$(CONFIG_ARCH_IOP32X) += iop32x

1
arch/arm/boot/dts/Makefile
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@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos5420-smdk5420.dtb \
exynos5440-sd5v1.dtb \
exynos5440-ssdk5440.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
ecx-2000.dtb
dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \

649
arch/arm/boot/dts/hi3620-hi4511.dts Normal file
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@ -0,0 +1,649 @@
/*
* Copyright (C) 2012-2013 Linaro Ltd.
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
/dts-v1/;
#include "hi3620.dtsi"
/ {
model = "Hisilicon Hi4511 Development Board";
compatible = "hisilicon,hi3620-hi4511";
chosen {
bootargs = "console=ttyAMA0,115200 root=/dev/ram0 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x40000000 0x20000000>;
};
amba {
dual_timer0: dual_timer@800000 {
status = "ok";
};
uart0: uart@b00000 { /* console */
pinctrl-names = "default", "idle";
pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
pinctrl-1 = <&uart0_pmx_idle &uart0_cfg_idle>;
status = "ok";
};
uart1: uart@b01000 { /* modem */
pinctrl-names = "default", "idle";
pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
pinctrl-1 = <&uart1_pmx_idle &uart1_cfg_idle>;
status = "ok";
};
uart2: uart@b02000 { /* audience */
pinctrl-names = "default", "idle";
pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
pinctrl-1 = <&uart2_pmx_idle &uart2_cfg_idle>;
status = "ok";
};
uart3: uart@b03000 {
pinctrl-names = "default", "idle";
pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
pinctrl-1 = <&uart3_pmx_idle &uart3_cfg_idle>;
status = "ok";
};
uart4: uart@b04000 {
pinctrl-names = "default", "idle";
pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
pinctrl-1 = <&uart4_pmx_idle &uart4_cfg_func>;
status = "ok";
};
pmx0: pinmux@803000 {
pinctrl-names = "default";
pinctrl-0 = <&board_pmx_pins>;
board_pmx_pins: board_pmx_pins {
pinctrl-single,pins = <
0x008 0x0 /* GPIO -- eFUSE_DOUT */
0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */
>;
};
uart0_pmx_func: uart0_pmx_func {
pinctrl-single,pins = <
0x0f0 0x0
0x0f4 0x0 /* UART0_RX & UART0_TX */
>;
};
uart0_pmx_idle: uart0_pmx_idle {
pinctrl-single,pins = <
/*0x0f0 0x1*/ /* UART0_CTS & UART0_RTS */
0x0f4 0x1 /* UART0_RX & UART0_TX */
>;
};
uart1_pmx_func: uart1_pmx_func {
pinctrl-single,pins = <
0x0f8 0x0 /* UART1_CTS & UART1_RTS (IOMG61) */
0x0fc 0x0 /* UART1_RX & UART1_TX (IOMG62) */
>;
};
uart1_pmx_idle: uart1_pmx_idle {
pinctrl-single,pins = <
0x0f8 0x1 /* GPIO (IOMG61) */
0x0fc 0x1 /* GPIO (IOMG62) */
>;
};
uart2_pmx_func: uart2_pmx_func {
pinctrl-single,pins = <
0x104 0x2 /* UART2_RXD (IOMG96) */
0x108 0x2 /* UART2_TXD (IOMG64) */
>;
};
uart2_pmx_idle: uart2_pmx_idle {
pinctrl-single,pins = <
0x104 0x1 /* GPIO (IOMG96) */
0x108 0x1 /* GPIO (IOMG64) */
>;
};
uart3_pmx_func: uart3_pmx_func {
pinctrl-single,pins = <
0x160 0x2 /* UART3_CTS & UART3_RTS (IOMG85) */
0x164 0x2 /* UART3_RXD & UART3_TXD (IOMG86) */
>;
};
uart3_pmx_idle: uart3_pmx_idle {
pinctrl-single,pins = <
0x160 0x1 /* GPIO (IOMG85) */
0x164 0x1 /* GPIO (IOMG86) */
>;
};
uart4_pmx_func: uart4_pmx_func {
pinctrl-single,pins = <
0x168 0x0 /* UART4_CTS & UART4_RTS (IOMG87) */
0x16c 0x0 /* UART4_RXD (IOMG88) */
0x170 0x0 /* UART4_TXD (IOMG93) */
>;
};
uart4_pmx_idle: uart4_pmx_idle {
pinctrl-single,pins = <
0x168 0x1 /* GPIO (IOMG87) */
0x16c 0x1 /* GPIO (IOMG88) */
0x170 0x1 /* GPIO (IOMG93) */
>;
};
i2c0_pmx_func: i2c0_pmx_func {
pinctrl-single,pins = <
0x0b4 0x0 /* I2C0_SCL & I2C0_SDA (IOMG45) */
>;
};
i2c0_pmx_idle: i2c0_pmx_idle {
pinctrl-single,pins = <
0x0b4 0x1 /* GPIO (IOMG45) */
>;
};
i2c1_pmx_func: i2c1_pmx_func {
pinctrl-single,pins = <
0x0b8 0x0 /* I2C1_SCL & I2C1_SDA (IOMG46) */
>;
};
i2c1_pmx_idle: i2c1_pmx_idle {
pinctrl-single,pins = <
0x0b8 0x1 /* GPIO (IOMG46) */
>;
};
i2c2_pmx_func: i2c2_pmx_func {
pinctrl-single,pins = <
0x068 0x0 /* I2C2_SCL (IOMG26) */
0x06c 0x0 /* I2C2_SDA (IOMG27) */
>;
};
i2c2_pmx_idle: i2c2_pmx_idle {
pinctrl-single,pins = <
0x068 0x1 /* GPIO (IOMG26) */
0x06c 0x1 /* GPIO (IOMG27) */
>;
};
i2c3_pmx_func: i2c3_pmx_func {
pinctrl-single,pins = <
0x050 0x2 /* I2C3_SCL (IOMG20) */
0x054 0x2 /* I2C3_SDA (IOMG21) */
>;
};
i2c3_pmx_idle: i2c3_pmx_idle {
pinctrl-single,pins = <
0x050 0x1 /* GPIO (IOMG20) */
0x054 0x1 /* GPIO (IOMG21) */
>;
};
spi0_pmx_func: spi0_pmx_func {
pinctrl-single,pins = <
0x0d4 0x0 /* SPI0_CLK/SPI0_DI/SPI0_DO (IOMG53) */
0x0d8 0x0 /* SPI0_CS0 (IOMG54) */
0x0dc 0x0 /* SPI0_CS1 (IOMG55) */
0x0e0 0x0 /* SPI0_CS2 (IOMG56) */
0x0e4 0x0 /* SPI0_CS3 (IOMG57) */
>;
};
spi0_pmx_idle: spi0_pmx_idle {
pinctrl-single,pins = <
0x0d4 0x1 /* GPIO (IOMG53) */
0x0d8 0x1 /* GPIO (IOMG54) */
0x0dc 0x1 /* GPIO (IOMG55) */
0x0e0 0x1 /* GPIO (IOMG56) */
0x0e4 0x1 /* GPIO (IOMG57) */
>;
};
spi1_pmx_func: spi1_pmx_func {
pinctrl-single,pins = <
0x184 0x0 /* SPI1_CLK/SPI1_DI (IOMG98) */
0x0e8 0x0 /* SPI1_DO (IOMG58) */
0x0ec 0x0 /* SPI1_CS (IOMG95) */
>;
};
spi1_pmx_idle: spi1_pmx_idle {
pinctrl-single,pins = <
0x184 0x1 /* GPIO (IOMG98) */
0x0e8 0x1 /* GPIO (IOMG58) */
0x0ec 0x1 /* GPIO (IOMG95) */
>;
};
kpc_pmx_func: kpc_pmx_func {
pinctrl-single,pins = <
0x12c 0x0 /* KEY_IN0 (IOMG73) */
0x130 0x0 /* KEY_IN1 (IOMG74) */
0x134 0x0 /* KEY_IN2 (IOMG75) */
0x10c 0x0 /* KEY_OUT0 (IOMG65) */
0x110 0x0 /* KEY_OUT1 (IOMG66) */
0x114 0x0 /* KEY_OUT2 (IOMG67) */
>;
};
kpc_pmx_idle: kpc_pmx_idle {
pinctrl-single,pins = <
0x12c 0x1 /* GPIO (IOMG73) */
0x130 0x1 /* GPIO (IOMG74) */
0x134 0x1 /* GPIO (IOMG75) */
0x10c 0x1 /* GPIO (IOMG65) */
0x110 0x1 /* GPIO (IOMG66) */
0x114 0x1 /* GPIO (IOMG67) */
>;
};
gpio_key_func: gpio_key_func {
pinctrl-single,pins = <
0x10c 0x1 /* KEY_OUT0/GPIO (IOMG65) */
0x130 0x1 /* KEY_IN1/GPIO (IOMG74) */
>;
};
emmc_pmx_func: emmc_pmx_func {
pinctrl-single,pins = <
0x030 0x2 /* eMMC_CMD/eMMC_CLK (IOMG12) */
0x018 0x0 /* NAND_CS3_N (IOMG6) */
0x024 0x0 /* NAND_BUSY2_N (IOMG8) */
0x028 0x0 /* NAND_BUSY3_N (IOMG9) */
0x02c 0x2 /* eMMC_DATA[0:7] (IOMG10) */
>;
};
emmc_pmx_idle: emmc_pmx_idle {
pinctrl-single,pins = <
0x030 0x0 /* GPIO (IOMG12) */
0x018 0x1 /* GPIO (IOMG6) */
0x024 0x1 /* GPIO (IOMG8) */
0x028 0x1 /* GPIO (IOMG9) */
0x02c 0x1 /* GPIO (IOMG10) */
>;
};
sd_pmx_func: sd_pmx_func {
pinctrl-single,pins = <
0x0bc 0x0 /* SD_CLK/SD_CMD/SD_DATA0/SD_DATA1/SD_DATA2 (IOMG47) */
0x0c0 0x0 /* SD_DATA3 (IOMG48) */
>;
};
sd_pmx_idle: sd_pmx_idle {
pinctrl-single,pins = <
0x0bc 0x1 /* GPIO (IOMG47) */
0x0c0 0x1 /* GPIO (IOMG48) */
>;
};
nand_pmx_func: nand_pmx_func {
pinctrl-single,pins = <
0x00c 0x0 /* NAND_ALE/NAND_CLE/.../NAND_DATA[0:7] (IOMG3) */
0x010 0x0 /* NAND_CS1_N (IOMG4) */
0x014 0x0 /* NAND_CS2_N (IOMG5) */
0x018 0x0 /* NAND_CS3_N (IOMG6) */
0x01c 0x0 /* NAND_BUSY0_N (IOMG94) */
0x020 0x0 /* NAND_BUSY1_N (IOMG7) */
0x024 0x0 /* NAND_BUSY2_N (IOMG8) */
0x028 0x0 /* NAND_BUSY3_N (IOMG9) */
0x02c 0x0 /* NAND_DATA[8:15] (IOMG10) */
>;
};
nand_pmx_idle: nand_pmx_idle {
pinctrl-single,pins = <
0x00c 0x1 /* GPIO (IOMG3) */
0x010 0x1 /* GPIO (IOMG4) */
0x014 0x1 /* GPIO (IOMG5) */
0x018 0x1 /* GPIO (IOMG6) */
0x01c 0x1 /* GPIO (IOMG94) */
0x020 0x1 /* GPIO (IOMG7) */
0x024 0x1 /* GPIO (IOMG8) */
0x028 0x1 /* GPIO (IOMG9) */
0x02c 0x1 /* GPIO (IOMG10) */
>;
};
sdio_pmx_func: sdio_pmx_func {
pinctrl-single,pins = <
0x0c4 0x0 /* SDIO_CLK/SDIO_CMD/SDIO_DATA[0:3] (IOMG49) */
>;
};
sdio_pmx_idle: sdio_pmx_idle {
pinctrl-single,pins = <
0x0c4 0x1 /* GPIO (IOMG49) */
>;
};
audio_out_pmx_func: audio_out_pmx_func {
pinctrl-single,pins = <
0x0f0 0x1 /* GPIO (IOMG59), audio spk & earphone */
>;
};
};
pmx1: pinmux@803800 {
pinctrl-names = "default";
pinctrl-0 = < &board_pu_pins &board_pd_pins &board_pd_ps_pins
&board_np_pins &board_ps_pins &kpc_cfg_func
&audio_out_cfg_func>;
board_pu_pins: board_pu_pins {
pinctrl-single,pins = <
0x014 0 /* GPIO_158 (IOCFG2) */
0x018 0 /* GPIO_159 (IOCFG3) */
0x01c 0 /* BOOT_MODE0 (IOCFG4) */
0x020 0 /* BOOT_MODE1 (IOCFG5) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
};
board_pd_pins: board_pd_pins {
pinctrl-single,pins = <
0x038 0 /* eFUSE_DOUT (IOCFG11) */
0x150 0 /* ISP_GPIO8 (IOCFG93) */
0x154 0 /* ISP_GPIO9 (IOCFG94) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
board_pd_ps_pins: board_pd_ps_pins {
pinctrl-single,pins = <
0x2d8 0 /* CLK_OUT0 (IOCFG190) */
0x004 0 /* PMU_SPI_DATA (IOCFG192) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
board_np_pins: board_np_pins {
pinctrl-single,pins = <
0x24c 0 /* KEYPAD_OUT7 (IOCFG155) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
board_ps_pins: board_ps_pins {
pinctrl-single,pins = <
0x000 0 /* PMU_SPI_CLK (IOCFG191) */
0x008 0 /* PMU_SPI_CS_N (IOCFG193) */
>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
uart0_cfg_func: uart0_cfg_func {
pinctrl-single,pins = <
0x208 0 /* UART0_RXD (IOCFG138) */
0x20c 0 /* UART0_TXD (IOCFG139) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart0_cfg_idle: uart0_cfg_idle {
pinctrl-single,pins = <
0x208 0 /* UART0_RXD (IOCFG138) */
0x20c 0 /* UART0_TXD (IOCFG139) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart1_cfg_func: uart1_cfg_func {
pinctrl-single,pins = <
0x210 0 /* UART1_CTS (IOCFG140) */
0x214 0 /* UART1_RTS (IOCFG141) */
0x218 0 /* UART1_RXD (IOCFG142) */
0x21c 0 /* UART1_TXD (IOCFG143) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart1_cfg_idle: uart1_cfg_idle {
pinctrl-single,pins = <
0x210 0 /* UART1_CTS (IOCFG140) */
0x214 0 /* UART1_RTS (IOCFG141) */
0x218 0 /* UART1_RXD (IOCFG142) */
0x21c 0 /* UART1_TXD (IOCFG143) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart2_cfg_func: uart2_cfg_func {
pinctrl-single,pins = <
0x220 0 /* UART2_CTS (IOCFG144) */
0x224 0 /* UART2_RTS (IOCFG145) */
0x228 0 /* UART2_RXD (IOCFG146) */
0x22c 0 /* UART2_TXD (IOCFG147) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart2_cfg_idle: uart2_cfg_idle {
pinctrl-single,pins = <
0x220 0 /* GPIO (IOCFG144) */
0x224 0 /* GPIO (IOCFG145) */
0x228 0 /* GPIO (IOCFG146) */
0x22c 0 /* GPIO (IOCFG147) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart3_cfg_func: uart3_cfg_func {
pinctrl-single,pins = <
0x294 0 /* UART3_CTS (IOCFG173) */
0x298 0 /* UART3_RTS (IOCFG174) */
0x29c 0 /* UART3_RXD (IOCFG175) */
0x2a0 0 /* UART3_TXD (IOCFG176) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart3_cfg_idle: uart3_cfg_idle {
pinctrl-single,pins = <
0x294 0 /* UART3_CTS (IOCFG173) */
0x298 0 /* UART3_RTS (IOCFG174) */
0x29c 0 /* UART3_RXD (IOCFG175) */
0x2a0 0 /* UART3_TXD (IOCFG176) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
uart4_cfg_func: uart4_cfg_func {
pinctrl-single,pins = <
0x2a4 0 /* UART4_CTS (IOCFG177) */
0x2a8 0 /* UART4_RTS (IOCFG178) */
0x2ac 0 /* UART4_RXD (IOCFG179) */
0x2b0 0 /* UART4_TXD (IOCFG180) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
i2c0_cfg_func: i2c0_cfg_func {
pinctrl-single,pins = <
0x17c 0 /* I2C0_SCL (IOCFG103) */
0x180 0 /* I2C0_SDA (IOCFG104) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
i2c1_cfg_func: i2c1_cfg_func {
pinctrl-single,pins = <
0x184 0 /* I2C1_SCL (IOCFG105) */
0x188 0 /* I2C1_SDA (IOCFG106) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
i2c2_cfg_func: i2c2_cfg_func {
pinctrl-single,pins = <
0x118 0 /* I2C2_SCL (IOCFG79) */
0x11c 0 /* I2C2_SDA (IOCFG80) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
i2c3_cfg_func: i2c3_cfg_func {
pinctrl-single,pins = <
0x100 0 /* I2C3_SCL (IOCFG73) */
0x104 0 /* I2C3_SDA (IOCFG74) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
spi0_cfg_func1: spi0_cfg_func1 {
pinctrl-single,pins = <
0x1d4 0 /* SPI0_CLK (IOCFG125) */
0x1d8 0 /* SPI0_DI (IOCFG126) */
0x1dc 0 /* SPI0_DO (IOCFG127) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
spi0_cfg_func2: spi0_cfg_func2 {
pinctrl-single,pins = <
0x1e0 0 /* SPI0_CS0 (IOCFG128) */
0x1e4 0 /* SPI0_CS1 (IOCFG129) */
0x1e8 0 /* SPI0_CS2 (IOCFG130 */
0x1ec 0 /* SPI0_CS3 (IOCFG131) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
spi1_cfg_func1: spi1_cfg_func1 {
pinctrl-single,pins = <
0x1f0 0 /* SPI1_CLK (IOCFG132) */
0x1f4 0 /* SPI1_DI (IOCFG133) */
0x1f8 0 /* SPI1_DO (IOCFG134) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
spi1_cfg_func2: spi1_cfg_func2 {
pinctrl-single,pins = <
0x1fc 0 /* SPI1_CS (IOCFG135) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
kpc_cfg_func: kpc_cfg_func {
pinctrl-single,pins = <
0x250 0 /* KEY_IN0 (IOCFG156) */
0x254 0 /* KEY_IN1 (IOCFG157) */
0x258 0 /* KEY_IN2 (IOCFG158) */
0x230 0 /* KEY_OUT0 (IOCFG148) */
0x234 0 /* KEY_OUT1 (IOCFG149) */
0x238 0 /* KEY_OUT2 (IOCFG150) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
emmc_cfg_func: emmc_cfg_func {
pinctrl-single,pins = <
0x0ac 0 /* eMMC_CMD (IOCFG40) */
0x0b0 0 /* eMMC_CLK (IOCFG41) */
0x058 0 /* NAND_CS3_N (IOCFG19) */
0x064 0 /* NAND_BUSY2_N (IOCFG22) */
0x068 0 /* NAND_BUSY3_N (IOCFG23) */
0x08c 0 /* NAND_DATA8 (IOCFG32) */
0x090 0 /* NAND_DATA9 (IOCFG33) */
0x094 0 /* NAND_DATA10 (IOCFG34) */
0x098 0 /* NAND_DATA11 (IOCFG35) */
0x09c 0 /* NAND_DATA12 (IOCFG36) */
0x0a0 0 /* NAND_DATA13 (IOCFG37) */
0x0a4 0 /* NAND_DATA14 (IOCFG38) */
0x0a8 0 /* NAND_DATA15 (IOCFG39) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
sd_cfg_func1: sd_cfg_func1 {
pinctrl-single,pins = <
0x18c 0 /* SD_CLK (IOCFG107) */
0x190 0 /* SD_CMD (IOCFG108) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
sd_cfg_func2: sd_cfg_func2 {
pinctrl-single,pins = <
0x194 0 /* SD_DATA0 (IOCFG109) */
0x198 0 /* SD_DATA1 (IOCFG110) */
0x19c 0 /* SD_DATA2 (IOCFG111) */
0x1a0 0 /* SD_DATA3 (IOCFG112) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x70 0xf0>;
};
nand_cfg_func1: nand_cfg_func1 {
pinctrl-single,pins = <
0x03c 0 /* NAND_ALE (IOCFG12) */
0x040 0 /* NAND_CLE (IOCFG13) */
0x06c 0 /* NAND_DATA0 (IOCFG24) */
0x070 0 /* NAND_DATA1 (IOCFG25) */
0x074 0 /* NAND_DATA2 (IOCFG26) */
0x078 0 /* NAND_DATA3 (IOCFG27) */
0x07c 0 /* NAND_DATA4 (IOCFG28) */
0x080 0 /* NAND_DATA5 (IOCFG29) */
0x084 0 /* NAND_DATA6 (IOCFG30) */
0x088 0 /* NAND_DATA7 (IOCFG31) */
0x08c 0 /* NAND_DATA8 (IOCFG32) */
0x090 0 /* NAND_DATA9 (IOCFG33) */
0x094 0 /* NAND_DATA10 (IOCFG34) */
0x098 0 /* NAND_DATA11 (IOCFG35) */
0x09c 0 /* NAND_DATA12 (IOCFG36) */
0x0a0 0 /* NAND_DATA13 (IOCFG37) */
0x0a4 0 /* NAND_DATA14 (IOCFG38) */
0x0a8 0 /* NAND_DATA15 (IOCFG39) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
nand_cfg_func2: nand_cfg_func2 {
pinctrl-single,pins = <
0x044 0 /* NAND_RE_N (IOCFG14) */
0x048 0 /* NAND_WE_N (IOCFG15) */
0x04c 0 /* NAND_CS0_N (IOCFG16) */
0x050 0 /* NAND_CS1_N (IOCFG17) */
0x054 0 /* NAND_CS2_N (IOCFG18) */
0x058 0 /* NAND_CS3_N (IOCFG19) */
0x05c 0 /* NAND_BUSY0_N (IOCFG20) */
0x060 0 /* NAND_BUSY1_N (IOCFG21) */
0x064 0 /* NAND_BUSY2_N (IOCFG22) */
0x068 0 /* NAND_BUSY3_N (IOCFG23) */
>;
pinctrl-single,bias-pulldown = <0 2 0 2>;
pinctrl-single,bias-pullup = <1 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
sdio_cfg_func: sdio_cfg_func {
pinctrl-single,pins = <
0x1a4 0 /* SDIO0_CLK (IOCG113) */
0x1a8 0 /* SDIO0_CMD (IOCG114) */
0x1ac 0 /* SDIO0_DATA0 (IOCG115) */
0x1b0 0 /* SDIO0_DATA1 (IOCG116) */
0x1b4 0 /* SDIO0_DATA2 (IOCG117) */
0x1b8 0 /* SDIO0_DATA3 (IOCG118) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
pinctrl-single,drive-strength = <0x30 0xf0>;
};
audio_out_cfg_func: audio_out_cfg_func {
pinctrl-single,pins = <
0x200 0 /* GPIO (IOCFG136) */
0x204 0 /* GPIO (IOCFG137) */
>;
pinctrl-single,bias-pulldown = <2 2 0 2>;
pinctrl-single,bias-pullup = <0 1 0 1>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
call {
label = "call";
gpios = <&gpio17 2 0>;
linux,code = <169>; /* KEY_PHONE */
};
};
};

565
arch/arm/boot/dts/hi3620.dtsi Normal file
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@ -0,0 +1,565 @@
/*
* Hisilicon Ltd. Hi3620 SoC
*
* Copyright (C) 2012-2013 Hisilicon Ltd.
* Copyright (C) 2012-2013 Linaro Ltd.
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include "skeleton.dtsi"
#include <dt-bindings/clock/hi3620-clock.h>
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
pclk: clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "apb_pclk";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x0>;
next-level-cache = <&L2>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
cpu@2 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
};
cpu@3 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
};
};
amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,amba-bus";
interrupt-parent = <&gic>;
ranges = <0 0xfc000000 0x2000000>;
L2: l2-cache {
compatible = "arm,pl310-cache";
reg = <0xfc10000 0x100000>;
interrupts = <0 15 4>;
cache-unified;
cache-level = <2>;
};
gic: interrupt-controller@1000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
/* gic dist base, gic cpu base */
reg = <0x1000 0x1000>, <0x100 0x100>;
};
sysctrl: system-controller@802000 {
compatible = "hisilicon,sysctrl";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x802000 0x1000>;
reg = <0x802000 0x1000>;
smp-offset = <0x31c>;
resume-offset = <0x308>;
reboot-offset = <0x4>;
clock: clock@0 {
compatible = "hisilicon,hi3620-clock";
reg = <0 0x10000>;
#clock-cells = <1>;
};
};
dual_timer0: dual_timer@800000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x800000 0x1000>;
/* timer00 & timer01 */
interrupts = <0 0 4>, <0 1 4>;
clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
dual_timer1: dual_timer@801000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x801000 0x1000>;
/* timer10 & timer11 */
interrupts = <0 2 4>, <0 3 4>;
clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
dual_timer2: dual_timer@a01000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0xa01000 0x1000>;
/* timer20 & timer21 */
interrupts = <0 4 4>, <0 5 4>;
clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
dual_timer3: dual_timer@a02000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0xa02000 0x1000>;
/* timer30 & timer31 */
interrupts = <0 6 4>, <0 7 4>;
clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
dual_timer4: dual_timer@a03000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0xa03000 0x1000>;
/* timer40 & timer41 */
interrupts = <0 96 4>, <0 97 4>;
clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
clock-names = "apb_pclk";
status = "disabled";
};
timer5: timer@600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x600 0x20>;
interrupts = <1 13 0xf01>;
};
uart0: uart@b00000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb00000 0x1000>;
interrupts = <0 20 4>;
clocks = <&clock HI3620_UARTCLK0>;
clock-names = "apb_pclk";
status = "disabled";
};
uart1: uart@b01000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb01000 0x1000>;
interrupts = <0 21 4>;
clocks = <&clock HI3620_UARTCLK1>;
clock-names = "apb_pclk";
status = "disabled";
};
uart2: uart@b02000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb02000 0x1000>;
interrupts = <0 22 4>;
clocks = <&clock HI3620_UARTCLK2>;
clock-names = "apb_pclk";
status = "disabled";
};
uart3: uart@b03000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb03000 0x1000>;
interrupts = <0 23 4>;
clocks = <&clock HI3620_UARTCLK3>;
clock-names = "apb_pclk";
status = "disabled";
};
uart4: uart@b04000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0xb04000 0x1000>;
interrupts = <0 24 4>;
clocks = <&clock HI3620_UARTCLK4>;
clock-names = "apb_pclk";
status = "disabled";
};
gpio0: gpio@806000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x806000 0x1000>;
interrupts = <0 64 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
&pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK0>;
clock-names = "apb_pclk";
};
gpio1: gpio@807000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x807000 0x1000>;
interrupts = <0 65 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
&pmx0 3 3 1 &pmx0 4 3 1 &pmx0 5 4 1
&pmx0 6 5 1 &pmx0 7 6 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK1>;
clock-names = "apb_pclk";
};
gpio2: gpio@808000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x808000 0x1000>;
interrupts = <0 66 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
&pmx0 3 10 1 &pmx0 4 3 1 &pmx0 5 3 1
&pmx0 6 3 1 &pmx0 7 3 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK2>;
clock-names = "apb_pclk";
};
gpio3: gpio@809000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x809000 0x1000>;
interrupts = <0 67 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
&pmx0 3 3 1 &pmx0 4 11 1 &pmx0 5 11 1
&pmx0 6 11 1 &pmx0 7 11 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK3>;
clock-names = "apb_pclk";
};
gpio4: gpio@80a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80a000 0x1000>;
interrupts = <0 68 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
&pmx0 3 11 1 &pmx0 4 12 1 &pmx0 5 12 1
&pmx0 6 13 1 &pmx0 7 13 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK4>;
clock-names = "apb_pclk";
};
gpio5: gpio@80b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80b000 0x1000>;
interrupts = <0 69 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
&pmx0 3 16 1 &pmx0 4 16 1 &pmx0 5 16 1
&pmx0 6 16 1 &pmx0 7 16 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK5>;
clock-names = "apb_pclk";
};
gpio6: gpio@80c000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80c000 0x1000>;
interrupts = <0 70 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
&pmx0 3 17 1 &pmx0 4 18 1 &pmx0 5 18 1
&pmx0 6 18 1 &pmx0 7 19 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK6>;
clock-names = "apb_pclk";
};
gpio7: gpio@80d000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80d000 0x1000>;
interrupts = <0 71 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
&pmx0 3 22 1 &pmx0 4 23 1 &pmx0 5 24 1
&pmx0 6 25 1 &pmx0 7 26 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK7>;
clock-names = "apb_pclk";
};
gpio8: gpio@80e000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80e000 0x1000>;
interrupts = <0 72 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
&pmx0 3 30 1 &pmx0 4 31 1 &pmx0 5 32 1
&pmx0 6 33 1 &pmx0 7 34 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK8>;
clock-names = "apb_pclk";
};
gpio9: gpio@80f000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x80f000 0x1000>;
interrupts = <0 73 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
&pmx0 3 38 1 &pmx0 4 39 1 &pmx0 5 40 1
&pmx0 6 41 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK9>;
clock-names = "apb_pclk";
};
gpio10: gpio@810000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x810000 0x1000>;
interrupts = <0 74 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
&pmx0 5 45 1 &pmx0 6 46 1 &pmx0 7 46 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK10>;
clock-names = "apb_pclk";
};
gpio11: gpio@811000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x811000 0x1000>;
interrupts = <0 75 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
&pmx0 3 47 1 &pmx0 4 47 1 &pmx0 5 48 1
&pmx0 6 49 1 &pmx0 7 49 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK11>;
clock-names = "apb_pclk";
};
gpio12: gpio@812000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x812000 0x1000>;
interrupts = <0 76 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
&pmx0 3 49 1 &pmx0 4 51 1 &pmx0 5 51 1
&pmx0 6 51 1 &pmx0 7 52 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK12>;
clock-names = "apb_pclk";
};
gpio13: gpio@813000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x813000 0x1000>;
interrupts = <0 77 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
&pmx0 3 53 1 &pmx0 4 53 1 &pmx0 5 54 1
&pmx0 6 55 1 &pmx0 7 56 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK13>;
clock-names = "apb_pclk";
};
gpio14: gpio@814000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x814000 0x1000>;
interrupts = <0 78 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
&pmx0 3 58 1 &pmx0 4 59 1 &pmx0 5 60 1
&pmx0 6 60 1 &pmx0 7 61 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK14>;
clock-names = "apb_pclk";
};
gpio15: gpio@815000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x815000 0x1000>;
interrupts = <0 79 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
&pmx0 3 63 1 &pmx0 4 63 1 &pmx0 5 64 1
&pmx0 6 64 1 &pmx0 7 65 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK15>;
clock-names = "apb_pclk";
};
gpio16: gpio@816000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x816000 0x1000>;
interrupts = <0 80 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
&pmx0 3 69 1 &pmx0 4 70 1 &pmx0 5 71 1
&pmx0 6 72 1 &pmx0 7 73 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK16>;
clock-names = "apb_pclk";
};
gpio17: gpio@817000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x817000 0x1000>;
interrupts = <0 81 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
&pmx0 3 77 1 &pmx0 4 78 1 &pmx0 5 79 1
&pmx0 6 80 1 &pmx0 7 81 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK17>;
clock-names = "apb_pclk";
};
gpio18: gpio@818000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x818000 0x1000>;
interrupts = <0 82 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
&pmx0 3 84 1 &pmx0 4 84 1 &pmx0 5 85 1
&pmx0 6 86 1 &pmx0 7 87 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK18>;
clock-names = "apb_pclk";
};
gpio19: gpio@819000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x819000 0x1000>;
interrupts = <0 83 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
&pmx0 3 88 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK19>;
clock-names = "apb_pclk";
};
gpio20: gpio@81a000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x81a000 0x1000>;
interrupts = <0 84 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
&pmx0 3 90 1 &pmx0 4 91 1 &pmx0 5 92 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK20>;
clock-names = "apb_pclk";
};
gpio21: gpio@81b000 {
compatible = "arm,pl061", "arm,primecell";
reg = <0x81b000 0x1000>;
interrupts = <0 85 0x4>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
interrupt-controller;
#interrupt-cells = <2>;
clocks = <&clock HI3620_GPIOCLK21>;
clock-names = "apb_pclk";
};
pmx0: pinmux@803000 {
compatible = "pinctrl-single";
reg = <0x803000 0x188>;
#address-cells = <1>;
#size-cells = <1>;
#gpio-range-cells = <3>;
ranges;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
&range 12 1 0 &range 13 29 1
&range 43 1 0 &range 44 49 1
&range 94 1 1 &range 96 2 1>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
pmx1: pinmux@803800 {
compatible = "pinconf-single";
reg = <0x803800 0x2dc>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-single,register-width = <32>;
};
};
};

56
arch/arm/configs/hi3xxx_defconfig Normal file
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@ -0,0 +1,56 @@
CONFIG_IRQ_DOMAIN_DEBUG=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_RD_LZMA=y
CONFIG_ARCH_HI3xxx=y
CONFIG_SMP=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_NET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_SATA_AHCI_PLATFORM=y
CONFIG_NETDEVICES=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_SPI=y
CONFIG_SPI_PL022=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_GPIO_GENERIC_PLATFORM=y
CONFIG_REGULATOR_GPIO=y
CONFIG_DRM=y
CONFIG_FB_SIMPLE=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_MMC=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_PL031=y
CONFIG_DMADEVICES=y
CONFIG_DW_DMAC=y
CONFIG_PL330_DMA=y
CONFIG_PWM=y
CONFIG_EXT4_FS=y
CONFIG_TMPFS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
CONFIG_PRINTK_TIME=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
CONFIG_LOCKUP_DETECTOR=y

1
arch/arm/configs/multi_v7_defconfig
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@ -12,6 +12,7 @@ CONFIG_MACH_BERLIN_BG2=y
CONFIG_MACH_BERLIN_BG2CD=y
CONFIG_GPIO_PCA953X=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_ARCH_HI3xxx=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ARCH_MXC=y
CONFIG_MACH_IMX51_DT=y

17
arch/arm/mach-hisi/Kconfig Normal file
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@ -0,0 +1,17 @@
config ARCH_HI3xxx
bool "Hisilicon Hi36xx/Hi37xx family" if ARCH_MULTI_V7
select ARM_AMBA
select ARM_GIC
select ARM_TIMER_SP804
select ARCH_WANT_OPTIONAL_GPIOLIB
select CACHE_L2X0
select CLKSRC_OF
select GENERIC_CLOCKEVENTS
select HAVE_ARM_SCU
select HAVE_ARM_TWD
select HAVE_SMP
select PINCTRL
select PINCTRL_SINGLE
select SMP
help
Support for Hisilicon Hi36xx/Hi37xx processor family

7
arch/arm/mach-hisi/Makefile Normal file
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@ -0,0 +1,7 @@
#
# Makefile for Hisilicon processors family
#
obj-y += hisilicon.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o

15
arch/arm/mach-hisi/core.h Normal file
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@ -0,0 +1,15 @@
#ifndef __HISILICON_CORE_H
#define __HISILICON_CORE_H
#include <linux/reboot.h>
extern void hi3xxx_set_cpu_jump(int cpu, void *jump_addr);
extern int hi3xxx_get_cpu_jump(int cpu);
extern void secondary_startup(void);
extern struct smp_operations hi3xxx_smp_ops;
extern void hi3xxx_cpu_die(unsigned int cpu);
extern int hi3xxx_cpu_kill(unsigned int cpu);
extern void hi3xxx_set_cpu(int cpu, bool enable);
#endif

90
arch/arm/mach-hisi/hisilicon.c Normal file
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@ -0,0 +1,90 @@
/*
* (Hisilicon's SoC based) flattened device tree enabled machine
*
* Copyright (c) 2012-2013 Hisilicon Ltd.
* Copyright (c) 2012-2013 Linaro Ltd.
*
* Author: Haojian Zhuang <haojian.zhuang@linaro.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clk-provider.h>
#include <linux/clocksource.h>
#include <linux/irqchip.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <asm/proc-fns.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include "core.h"
#define HI3620_SYSCTRL_PHYS_BASE 0xfc802000
#define HI3620_SYSCTRL_VIRT_BASE 0xfe802000
/*
* This table is only for optimization. Since ioremap() could always share
* the same mapping if it's defined as static IO mapping.
*
* Without this table, system could also work. The cost is some virtual address
* spaces wasted since ioremap() may be called multi times for the same
* IO space.
*/
static struct map_desc hi3620_io_desc[] __initdata = {
{
/* sysctrl */
.pfn = __phys_to_pfn(HI3620_SYSCTRL_PHYS_BASE),
.virtual = HI3620_SYSCTRL_VIRT_BASE,
.length = 0x1000,
.type = MT_DEVICE,
},
};
static void __init hi3620_map_io(void)
{
debug_ll_io_init();
iotable_init(hi3620_io_desc, ARRAY_SIZE(hi3620_io_desc));
}
static void hi3xxx_restart(enum reboot_mode mode, const char *cmd)
{
struct device_node *np;
void __iomem *base;
int offset;
np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
if (!np) {
pr_err("failed to find hisilicon,sysctrl node\n");
return;
}
base = of_iomap(np, 0);
if (!base) {
pr_err("failed to map address in hisilicon,sysctrl node\n");
return;
}
if (of_property_read_u32(np, "reboot-offset", &offset) < 0) {
pr_err("failed to find reboot-offset property\n");
return;
}
writel_relaxed(0xdeadbeef, base + offset);
while (1)
cpu_do_idle();
}
static const char *hi3xxx_compat[] __initconst = {
"hisilicon,hi3620-hi4511",
NULL,
};
DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)")
.map_io = hi3620_map_io,
.dt_compat = hi3xxx_compat,
.smp = smp_ops(hi3xxx_smp_ops),
.restart = hi3xxx_restart,
MACHINE_END

200
arch/arm/mach-hisi/hotplug.c Normal file
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@ -0,0 +1,200 @@
/*
* Copyright (c) 2013 Linaro Ltd.
* Copyright (c) 2013 Hisilicon Limited.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
#include <linux/cpu.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include "core.h"
/* Sysctrl registers in Hi3620 SoC */
#define SCISOEN 0xc0
#define SCISODIS 0xc4
#define SCPERPWREN 0xd0
#define SCPERPWRDIS 0xd4
#define SCCPUCOREEN 0xf4
#define SCCPUCOREDIS 0xf8
#define SCPERCTRL0 0x200
#define SCCPURSTEN 0x410
#define SCCPURSTDIS 0x414
/*
* bit definition in SCISOEN/SCPERPWREN/...
*
* CPU2_ISO_CTRL (1 << 5)
* CPU3_ISO_CTRL (1 << 6)
* ...
*/
#define CPU2_ISO_CTRL (1 << 5)
/*
* bit definition in SCPERCTRL0
*
* CPU0_WFI_MASK_CFG (1 << 28)
* CPU1_WFI_MASK_CFG (1 << 29)
* ...
*/
#define CPU0_WFI_MASK_CFG (1 << 28)
/*
* bit definition in SCCPURSTEN/...
*
* CPU0_SRST_REQ_EN (1 << 0)
* CPU1_SRST_REQ_EN (1 << 1)
* ...
*/
#define CPU0_HPM_SRST_REQ_EN (1 << 22)
#define CPU0_DBG_SRST_REQ_EN (1 << 12)
#define CPU0_NEON_SRST_REQ_EN (1 << 4)
#define CPU0_SRST_REQ_EN (1 << 0)
enum {
HI3620_CTRL,
ERROR_CTRL,
};
static void __iomem *ctrl_base;
static int id;
static void set_cpu_hi3620(int cpu, bool enable)
{
u32 val = 0;
if (enable) {
/* MTCMOS set */
if ((cpu == 2) || (cpu == 3))
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
ctrl_base + SCPERPWREN);
udelay(100);
/* Enable core */
writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);
/* unreset */
val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
| CPU0_SRST_REQ_EN;
writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
/* reset */
val |= CPU0_HPM_SRST_REQ_EN;
writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
/* ISO disable */
if ((cpu == 2) || (cpu == 3))
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
ctrl_base + SCISODIS);
udelay(1);
/* WFI Mask */
val = readl_relaxed(ctrl_base + SCPERCTRL0);
val &= ~(CPU0_WFI_MASK_CFG << cpu);
writel_relaxed(val, ctrl_base + SCPERCTRL0);
/* Unreset */
val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
| CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
} else {
/* wfi mask */
val = readl_relaxed(ctrl_base + SCPERCTRL0);
val |= (CPU0_WFI_MASK_CFG << cpu);
writel_relaxed(val, ctrl_base + SCPERCTRL0);
/* disable core*/
writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);
if ((cpu == 2) || (cpu == 3)) {
/* iso enable */
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
ctrl_base + SCISOEN);
udelay(1);
}
/* reset */
val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
| CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
if ((cpu == 2) || (cpu == 3)) {
/* MTCMOS unset */
writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
ctrl_base + SCPERPWRDIS);
udelay(100);
}
}
}
static int hi3xxx_hotplug_init(void)
{
struct device_node *node;
node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
if (node) {
ctrl_base = of_iomap(node, 0);
id = HI3620_CTRL;
return 0;
}
id = ERROR_CTRL;
return -ENOENT;
}
void hi3xxx_set_cpu(int cpu, bool enable)
{
if (!ctrl_base) {
if (hi3xxx_hotplug_init() < 0)
return;
}
if (id == HI3620_CTRL)
set_cpu_hi3620(cpu, enable);
}
static inline void cpu_enter_lowpower(void)
{
unsigned int v;
flush_cache_all();
/*
* Turn off coherency and L1 D-cache
*/
asm volatile(
" mrc p15, 0, %0, c1, c0, 1\n"
" bic %0, %0, #0x40\n"
" mcr p15, 0, %0, c1, c0, 1\n"
" mrc p15, 0, %0, c1, c0, 0\n"
" bic %0, %0, #0x04\n"
" mcr p15, 0, %0, c1, c0, 0\n"
: "=&r" (v)
: "r" (0)
: "cc");
}
void hi3xxx_cpu_die(unsigned int cpu)
{
cpu_enter_lowpower();
hi3xxx_set_cpu_jump(cpu, phys_to_virt(0));
cpu_do_idle();
/* We should have never returned from idle */
panic("cpu %d unexpectedly exit from shutdown\n", cpu);
}
int hi3xxx_cpu_kill(unsigned int cpu)
{
unsigned long timeout = jiffies + msecs_to_jiffies(50);
while (hi3xxx_get_cpu_jump(cpu))
if (time_after(jiffies, timeout))
return 0;
hi3xxx_set_cpu(cpu, false);
return 1;
}

89
arch/arm/mach-hisi/platsmp.c Normal file
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@ -0,0 +1,89 @@
/*
* Copyright (c) 2013 Linaro Ltd.
* Copyright (c) 2013 Hisilicon Limited.
* Based on arch/arm/mach-vexpress/platsmp.c, Copyright (C) 2002 ARM Ltd.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*/
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include "core.h"
static void __iomem *ctrl_base;
void hi3xxx_set_cpu_jump(int cpu, void *jump_addr)
{
cpu = cpu_logical_map(cpu);
if (!cpu || !ctrl_base)
return;
writel_relaxed(virt_to_phys(jump_addr), ctrl_base + ((cpu - 1) << 2));
}
int hi3xxx_get_cpu_jump(int cpu)
{
cpu = cpu_logical_map(cpu);
if (!cpu || !ctrl_base)
return 0;
return readl_relaxed(ctrl_base + ((cpu - 1) << 2));
}
static void __init hi3xxx_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np = NULL;
unsigned long base = 0;
u32 offset = 0;
void __iomem *scu_base = NULL;
if (scu_a9_has_base()) {
base = scu_a9_get_base();
scu_base = ioremap(base, SZ_4K);
if (!scu_base) {
pr_err("ioremap(scu_base) failed\n");
return;
}
scu_enable(scu_base);
iounmap(scu_base);
}
if (!ctrl_base) {
np = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
if (!np) {
pr_err("failed to find hisilicon,sysctrl node\n");
return;
}
ctrl_base = of_iomap(np, 0);
if (!ctrl_base) {
pr_err("failed to map address\n");
return;
}
if (of_property_read_u32(np, "smp-offset", &offset) < 0) {
pr_err("failed to find smp-offset property\n");
return;
}
ctrl_base += offset;
}
}
static int hi3xxx_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
hi3xxx_set_cpu(cpu, true);
hi3xxx_set_cpu_jump(cpu, secondary_startup);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
return 0;
}
struct smp_operations hi3xxx_smp_ops __initdata = {
.smp_prepare_cpus = hi3xxx_smp_prepare_cpus,
.smp_boot_secondary = hi3xxx_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_die = hi3xxx_cpu_die,
.cpu_kill = hi3xxx_cpu_kill,
#endif
};