ARM: Merge for-2635/s5p6440-clock
Merge branch 'for-2635/s5p6440-clock' into for-linus/samsung2
This commit is contained in:
Ben Dooks
Коммит
d16067b25e
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@ -134,24 +134,6 @@ static struct clksrc_clk clk_mout_mpll = {
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
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};
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static struct clk clk_h_low = {
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.name = "hclk_low",
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.id = -1,
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.rate = 0,
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.parent = NULL,
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.ctrlbit = 0,
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.ops = &clk_ops_def_setrate,
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};
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static struct clk clk_p_low = {
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.name = "pclk_low",
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.id = -1,
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.rate = 0,
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.parent = NULL,
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.ctrlbit = 0,
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.ops = &clk_ops_def_setrate,
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};
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enum perf_level {
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L0 = 532*1000,
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L1 = 266*1000,
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@ -247,23 +229,70 @@ static struct clk_ops s5p6440_clkarm_ops = {
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.round_rate = s5p6440_armclk_round_rate,
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};
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static unsigned long s5p6440_clk_doutmpll_get_rate(struct clk *clk)
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{
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unsigned long rate = clk_get_rate(clk->parent);
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static struct clksrc_clk clk_armclk = {
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.clk = {
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.name = "armclk",
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.id = 1,
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.parent = &clk_mout_apll.clk,
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.ops = &s5p6440_clkarm_ops,
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},
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
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};
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if (__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_MPLL_MASK)
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rate /= 2;
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return rate;
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}
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static struct clk clk_dout_mpll = {
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static struct clksrc_clk clk_dout_mpll = {
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.clk = {
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.name = "dout_mpll",
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.id = -1,
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.parent = &clk_mout_mpll.clk,
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.ops = &(struct clk_ops) {
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.get_rate = s5p6440_clk_doutmpll_get_rate,
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},
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
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};
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static struct clksrc_clk clk_hclk = {
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.clk = {
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.name = "clk_hclk",
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.id = -1,
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.parent = &clk_armclk.clk,
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},
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
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};
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static struct clksrc_clk clk_pclk = {
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.clk = {
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.name = "clk_pclk",
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.id = -1,
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.parent = &clk_hclk.clk,
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},
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.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
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};
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static struct clk *clkset_hclklow_list[] = {
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&clk_mout_apll.clk,
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&clk_mout_mpll.clk,
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};
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static struct clksrc_sources clkset_hclklow = {
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.sources = clkset_hclklow_list,
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.nr_sources = ARRAY_SIZE(clkset_hclklow_list),
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};
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static struct clksrc_clk clk_hclk_low = {
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.clk = {
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.name = "hclk_low",
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.id = -1,
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},
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.sources = &clkset_hclklow,
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.reg_src = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
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.reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
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};
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static struct clksrc_clk clk_pclk_low = {
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.clk = {
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.name = "pclk_low",
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.id = -1,
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.parent = &clk_hclk_low.clk,
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},
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.reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
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};
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int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
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@ -307,6 +336,11 @@ static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
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return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
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}
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static int s5p6440_sclk1_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable);
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}
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static int s5p6440_mem_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
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@ -321,37 +355,37 @@ static struct clk init_clocks_disable[] = {
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{
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.name = "nand",
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.id = -1,
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.parent = &clk_h,
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.parent = &clk_hclk.clk,
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.enable = s5p6440_mem_ctrl,
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.ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON,
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}, {
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.name = "adc",
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.id = -1,
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.parent = &clk_p_low,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = S5P_CLKCON_PCLK_TSADC,
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}, {
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.name = "i2c",
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.id = -1,
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.parent = &clk_p_low,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = S5P_CLKCON_PCLK_IIC0,
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}, {
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.name = "i2s_v40",
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.id = 0,
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.parent = &clk_p_low,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = S5P_CLKCON_PCLK_IIS2,
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}, {
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.name = "spi",
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.id = 0,
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.parent = &clk_p_low,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = S5P_CLKCON_PCLK_SPI0,
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}, {
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.name = "spi",
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.id = 1,
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.parent = &clk_p_low,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = S5P_CLKCON_PCLK_SPI1,
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}, {
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@ -387,58 +421,124 @@ static struct clk init_clocks_disable[] = {
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}, {
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.name = "otg",
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.id = -1,
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.parent = &clk_h_low,
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.parent = &clk_hclk_low.clk,
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.enable = s5p6440_hclk0_ctrl,
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.ctrlbit = S5P_CLKCON_HCLK0_USB
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}, {
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.name = "post",
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.id = -1,
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.parent = &clk_h_low,
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.parent = &clk_hclk_low.clk,
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.enable = s5p6440_hclk0_ctrl,
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.ctrlbit = S5P_CLKCON_HCLK0_POST0
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}, {
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.name = "lcd",
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.id = -1,
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.parent = &clk_h_low,
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.parent = &clk_hclk_low.clk,
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.enable = s5p6440_hclk1_ctrl,
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.ctrlbit = S5P_CLKCON_HCLK1_DISPCON,
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}, {
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.name = "hsmmc",
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.id = 0,
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.parent = &clk_h_low,
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.parent = &clk_hclk_low.clk,
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.enable = s5p6440_hclk0_ctrl,
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.ctrlbit = S5P_CLKCON_HCLK0_HSMMC0,
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}, {
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.name = "hsmmc",
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.id = 1,
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.parent = &clk_h_low,
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.parent = &clk_hclk_low.clk,
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.enable = s5p6440_hclk0_ctrl,
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.ctrlbit = S5P_CLKCON_HCLK0_HSMMC1,
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}, {
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.name = "hsmmc",
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.id = 2,
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.parent = &clk_h_low,
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.parent = &clk_hclk_low.clk,
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.enable = s5p6440_hclk0_ctrl,
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.ctrlbit = S5P_CLKCON_HCLK0_HSMMC2,
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}, {
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.name = "rtc",
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.id = -1,
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.parent = &clk_p_low,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = S5P_CLKCON_PCLK_RTC,
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}, {
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.name = "watchdog",
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.id = -1,
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.parent = &clk_p_low,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = S5P_CLKCON_PCLK_WDT,
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}, {
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.name = "timers",
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.id = -1,
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.parent = &clk_p_low,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = S5P_CLKCON_PCLK_PWM,
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}
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}, {
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.name = "hclk_fimgvg",
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.id = -1,
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.parent = &clk_hclk.clk,
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.enable = s5p6440_hclk1_ctrl,
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.ctrlbit = (1 << 2),
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}, {
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.name = "tsi",
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.id = -1,
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.parent = &clk_hclk_low.clk,
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.enable = s5p6440_hclk1_ctrl,
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.ctrlbit = (1 << 0),
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}, {
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.name = "pclk_fimgvg",
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.id = -1,
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.parent = &clk_pclk.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = (1 << 31),
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}, {
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.name = "dmc0",
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.id = -1,
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.parent = &clk_pclk.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = (1 << 30),
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}, {
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.name = "etm",
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.id = -1,
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.parent = &clk_pclk.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = (1 << 29),
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}, {
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.name = "dsim",
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.id = -1,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = (1 << 28),
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}, {
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.name = "gps",
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.id = -1,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = (1 << 25),
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}, {
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.name = "pcm",
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.id = -1,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = (1 << 8),
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}, {
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.name = "irom",
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.id = -1,
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.parent = &clk_hclk.clk,
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.enable = s5p6440_hclk0_ctrl,
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.ctrlbit = (1 << 25),
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}, {
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.name = "dma",
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.id = -1,
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.parent = &clk_hclk_low.clk,
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.enable = s5p6440_hclk0_ctrl,
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.ctrlbit = (1 << 12),
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}, {
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.name = "2d",
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.id = -1,
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.parent = &clk_hclk.clk,
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.enable = s5p6440_hclk0_ctrl,
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.ctrlbit = (1 << 8),
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},
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};
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/*
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@ -448,34 +548,46 @@ static struct clk init_clocks[] = {
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{
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.name = "gpio",
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.id = -1,
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.parent = &clk_p_low,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = S5P_CLKCON_PCLK_GPIO,
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}, {
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.name = "uart",
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.id = 0,
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.parent = &clk_p_low,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = S5P_CLKCON_PCLK_UART0,
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}, {
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.name = "uart",
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.id = 1,
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.parent = &clk_p_low,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = S5P_CLKCON_PCLK_UART1,
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}, {
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.name = "uart",
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.id = 2,
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.parent = &clk_p_low,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = S5P_CLKCON_PCLK_UART2,
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}, {
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.name = "uart",
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.id = 3,
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.parent = &clk_p_low,
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.parent = &clk_pclk_low.clk,
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.enable = s5p6440_pclk_ctrl,
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.ctrlbit = S5P_CLKCON_PCLK_UART3,
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}
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}, {
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.name = "mem",
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.id = -1,
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.parent = &clk_hclk.clk,
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.enable = s5p6440_hclk0_ctrl,
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.ctrlbit = (1 << 21),
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}, {
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.name = "intc",
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.id = -1,
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.parent = &clk_hclk.clk,
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.enable = s5p6440_hclk0_ctrl,
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.ctrlbit = (1 << 1),
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},
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};
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static struct clk clk_iis_cd_v40 = {
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@ -488,20 +600,20 @@ static struct clk clk_pcm_cd = {
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.id = -1,
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};
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static struct clk *clkset_spi_mmc_list[] = {
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static struct clk *clkset_group1_list[] = {
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&clk_mout_epll.clk,
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&clk_dout_mpll,
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&clk_dout_mpll.clk,
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&clk_fin_epll,
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};
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static struct clksrc_sources clkset_spi_mmc = {
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.sources = clkset_spi_mmc_list,
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.nr_sources = ARRAY_SIZE(clkset_spi_mmc_list),
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static struct clksrc_sources clkset_group1 = {
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.sources = clkset_group1_list,
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.nr_sources = ARRAY_SIZE(clkset_group1_list),
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};
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static struct clk *clkset_uart_list[] = {
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&clk_mout_epll.clk,
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&clk_dout_mpll
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&clk_dout_mpll.clk,
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};
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static struct clksrc_sources clkset_uart = {
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@ -509,6 +621,19 @@ static struct clksrc_sources clkset_uart = {
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.nr_sources = ARRAY_SIZE(clkset_uart_list),
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};
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static struct clk *clkset_audio_list[] = {
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&clk_mout_epll.clk,
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&clk_dout_mpll.clk,
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&clk_fin_epll,
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&clk_iis_cd_v40,
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&clk_pcm_cd,
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};
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static struct clksrc_sources clkset_audio = {
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.sources = clkset_audio_list,
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.nr_sources = ARRAY_SIZE(clkset_audio_list),
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};
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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@ -517,7 +642,7 @@ static struct clksrc_clk clksrcs[] = {
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.ctrlbit = S5P_CLKCON_SCLK0_MMC0,
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.enable = s5p6440_sclk_ctrl,
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},
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.sources = &clkset_spi_mmc,
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
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.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
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}, {
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@ -527,7 +652,7 @@ static struct clksrc_clk clksrcs[] = {
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.ctrlbit = S5P_CLKCON_SCLK0_MMC1,
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.enable = s5p6440_sclk_ctrl,
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},
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.sources = &clkset_spi_mmc,
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
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.reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
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}, {
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@ -537,7 +662,7 @@ static struct clksrc_clk clksrcs[] = {
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.ctrlbit = S5P_CLKCON_SCLK0_MMC2,
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.enable = s5p6440_sclk_ctrl,
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},
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.sources = &clkset_spi_mmc,
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
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.reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
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}, {
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@ -557,7 +682,7 @@ static struct clksrc_clk clksrcs[] = {
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.ctrlbit = S5P_CLKCON_SCLK0_SPI0,
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.enable = s5p6440_sclk_ctrl,
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},
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.sources = &clkset_spi_mmc,
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
|
||||
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
|
||||
}, {
|
||||
|
|
@ -567,17 +692,63 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.ctrlbit = S5P_CLKCON_SCLK0_SPI1,
|
||||
.enable = s5p6440_sclk_ctrl,
|
||||
},
|
||||
.sources = &clkset_spi_mmc,
|
||||
.sources = &clkset_group1,
|
||||
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
|
||||
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
|
||||
}
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_post",
|
||||
.id = -1,
|
||||
.ctrlbit = (1 << 10),
|
||||
.enable = s5p6440_sclk_ctrl,
|
||||
},
|
||||
.sources = &clkset_group1,
|
||||
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 },
|
||||
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_dispcon",
|
||||
.id = -1,
|
||||
.ctrlbit = (1 << 1),
|
||||
.enable = s5p6440_sclk1_ctrl,
|
||||
},
|
||||
.sources = &clkset_group1,
|
||||
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
|
||||
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_fimgvg",
|
||||
.id = -1,
|
||||
.ctrlbit = (1 << 2),
|
||||
.enable = s5p6440_sclk1_ctrl,
|
||||
},
|
||||
.sources = &clkset_group1,
|
||||
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
|
||||
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
|
||||
}, {
|
||||
.clk = {
|
||||
.name = "sclk_audio2",
|
||||
.id = -1,
|
||||
.ctrlbit = (1 << 11),
|
||||
.enable = s5p6440_sclk_ctrl,
|
||||
},
|
||||
.sources = &clkset_audio,
|
||||
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 },
|
||||
.reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 },
|
||||
},
|
||||
};
|
||||
|
||||
/* Clock initialisation code */
|
||||
static struct clksrc_clk *init_parents[] = {
|
||||
static struct clksrc_clk *sysclks[] = {
|
||||
&clk_mout_apll,
|
||||
&clk_mout_epll,
|
||||
&clk_mout_mpll,
|
||||
&clk_dout_mpll,
|
||||
&clk_armclk,
|
||||
&clk_hclk,
|
||||
&clk_pclk,
|
||||
&clk_hclk_low,
|
||||
&clk_pclk_low,
|
||||
};
|
||||
|
||||
void __init_or_cpufreq s5p6440_setup_clocks(void)
|
||||
|
|
@ -593,21 +764,13 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
|
|||
unsigned long apll;
|
||||
unsigned long mpll;
|
||||
unsigned int ptr;
|
||||
u32 clkdiv0;
|
||||
u32 clkdiv3;
|
||||
|
||||
/* Set S5P6440 functions for clk_fout_epll */
|
||||
clk_fout_epll.enable = s5p6440_epll_enable;
|
||||
clk_fout_epll.ops = &s5p6440_epll_ops;
|
||||
|
||||
/* Set S5P6440 functions for arm clock */
|
||||
clk_arm.parent = &clk_mout_apll.clk;
|
||||
clk_arm.ops = &s5p6440_clkarm_ops;
|
||||
clk_48m.enable = s5p6440_clk48m_ctrl;
|
||||
|
||||
clkdiv0 = __raw_readl(S5P_CLK_DIV0);
|
||||
clkdiv3 = __raw_readl(S5P_CLK_DIV3);
|
||||
|
||||
xtal_clk = clk_get(NULL, "ext_xtal");
|
||||
BUG_ON(IS_ERR(xtal_clk));
|
||||
|
||||
|
|
@ -619,41 +782,28 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
|
|||
mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
|
||||
apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
|
||||
|
||||
clk_fout_mpll.rate = mpll;
|
||||
clk_fout_epll.rate = epll;
|
||||
clk_fout_apll.rate = apll;
|
||||
|
||||
printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
|
||||
" E=%ld.%ldMHz\n",
|
||||
print_mhz(apll), print_mhz(mpll), print_mhz(epll));
|
||||
|
||||
fclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_ARM);
|
||||
hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK);
|
||||
pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK);
|
||||
|
||||
if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) {
|
||||
/* Asynchronous mode */
|
||||
hclk_low = mpll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW);
|
||||
} else {
|
||||
/* Synchronous mode */
|
||||
hclk_low = apll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW);
|
||||
}
|
||||
|
||||
pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW);
|
||||
fclk = clk_get_rate(&clk_armclk.clk);
|
||||
hclk = clk_get_rate(&clk_hclk.clk);
|
||||
pclk = clk_get_rate(&clk_pclk.clk);
|
||||
hclk_low = clk_get_rate(&clk_hclk_low.clk);
|
||||
pclk_low = clk_get_rate(&clk_pclk_low.clk);
|
||||
|
||||
printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
|
||||
" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
|
||||
print_mhz(hclk), print_mhz(hclk_low),
|
||||
print_mhz(pclk), print_mhz(pclk_low));
|
||||
|
||||
clk_fout_mpll.rate = mpll;
|
||||
clk_fout_epll.rate = epll;
|
||||
clk_fout_apll.rate = apll;
|
||||
|
||||
clk_f.rate = fclk;
|
||||
clk_h.rate = hclk;
|
||||
clk_p.rate = pclk;
|
||||
clk_h_low.rate = hclk_low;
|
||||
clk_p_low.rate = pclk_low;
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
|
||||
s3c_set_clksrc(init_parents[ptr], true);
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
|
||||
s3c_set_clksrc(&clksrcs[ptr], true);
|
||||
|
|
@ -661,13 +811,8 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
|
|||
|
||||
static struct clk *clks[] __initdata = {
|
||||
&clk_ext,
|
||||
&clk_mout_epll.clk,
|
||||
&clk_mout_mpll.clk,
|
||||
&clk_dout_mpll,
|
||||
&clk_iis_cd_v40,
|
||||
&clk_pcm_cd,
|
||||
&clk_p_low,
|
||||
&clk_h_low,
|
||||
};
|
||||
|
||||
void __init s5p6440_register_clocks(void)
|
||||
|
|
@ -680,6 +825,9 @@ void __init s5p6440_register_clocks(void)
|
|||
if (ret > 0)
|
||||
printk(KERN_ERR "Failed to register %u clocks\n", ret);
|
||||
|
||||
for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
|
||||
s3c_register_clksrc(sysclks[ptr], 1);
|
||||
|
||||
s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
|
||||
s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
|
||||
|
||||
|
|
|
|||
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