crypto: talitos - move talitos structures to header file
This patch moves the talitos structure definitions from c file to its header file so that the same can be shared on need basis. Signed-off-by: Sandeep Malik <Sandeep.Malik@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Horia Geanta
Herbert Xu
Родитель
de19753348
Коммит
d1a0eb98e7
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@ -53,117 +53,6 @@
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#include "talitos.h"
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#define TALITOS_TIMEOUT 100000
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#define TALITOS_MAX_DATA_LEN 65535
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#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
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#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
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#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
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/* descriptor pointer entry */
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struct talitos_ptr {
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__be16 len; /* length */
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u8 j_extent; /* jump to sg link table and/or extent */
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u8 eptr; /* extended address */
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__be32 ptr; /* address */
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};
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static const struct talitos_ptr zero_entry = {
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.len = 0,
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.j_extent = 0,
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.eptr = 0,
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.ptr = 0
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};
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/* descriptor */
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struct talitos_desc {
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__be32 hdr; /* header high bits */
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__be32 hdr_lo; /* header low bits */
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struct talitos_ptr ptr[7]; /* ptr/len pair array */
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};
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/**
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* talitos_request - descriptor submission request
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* @desc: descriptor pointer (kernel virtual)
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* @dma_desc: descriptor's physical bus address
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* @callback: whom to call when descriptor processing is done
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* @context: caller context (optional)
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*/
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struct talitos_request {
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struct talitos_desc *desc;
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dma_addr_t dma_desc;
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void (*callback) (struct device *dev, struct talitos_desc *desc,
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void *context, int error);
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void *context;
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};
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/* per-channel fifo management */
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struct talitos_channel {
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void __iomem *reg;
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/* request fifo */
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struct talitos_request *fifo;
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/* number of requests pending in channel h/w fifo */
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atomic_t submit_count ____cacheline_aligned;
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/* request submission (head) lock */
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spinlock_t head_lock ____cacheline_aligned;
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/* index to next free descriptor request */
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int head;
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/* request release (tail) lock */
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spinlock_t tail_lock ____cacheline_aligned;
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/* index to next in-progress/done descriptor request */
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int tail;
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};
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struct talitos_private {
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struct device *dev;
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struct platform_device *ofdev;
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void __iomem *reg;
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int irq[2];
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/* SEC global registers lock */
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spinlock_t reg_lock ____cacheline_aligned;
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/* SEC version geometry (from device tree node) */
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unsigned int num_channels;
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unsigned int chfifo_len;
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unsigned int exec_units;
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unsigned int desc_types;
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/* SEC Compatibility info */
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unsigned long features;
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/*
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* length of the request fifo
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* fifo_len is chfifo_len rounded up to next power of 2
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* so we can use bitwise ops to wrap
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*/
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unsigned int fifo_len;
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struct talitos_channel *chan;
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/* next channel to be assigned next incoming descriptor */
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atomic_t last_chan ____cacheline_aligned;
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/* request callback tasklet */
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struct tasklet_struct done_task[2];
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/* list of registered algorithms */
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struct list_head alg_list;
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/* hwrng device */
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struct hwrng rng;
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};
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/* .features flag */
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#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
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#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
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#define TALITOS_FTR_SHA224_HWINIT 0x00000004
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#define TALITOS_FTR_HMAC_OK 0x00000008
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static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
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{
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talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
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@ -28,6 +28,117 @@
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*
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*/
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#define TALITOS_TIMEOUT 100000
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#define TALITOS_MAX_DATA_LEN 65535
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#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
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#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
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#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
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/* descriptor pointer entry */
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struct talitos_ptr {
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__be16 len; /* length */
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u8 j_extent; /* jump to sg link table and/or extent */
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u8 eptr; /* extended address */
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__be32 ptr; /* address */
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};
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static const struct talitos_ptr zero_entry = {
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.len = 0,
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.j_extent = 0,
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.eptr = 0,
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.ptr = 0
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};
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/* descriptor */
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struct talitos_desc {
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__be32 hdr; /* header high bits */
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__be32 hdr_lo; /* header low bits */
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struct talitos_ptr ptr[7]; /* ptr/len pair array */
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};
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/**
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* talitos_request - descriptor submission request
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* @desc: descriptor pointer (kernel virtual)
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* @dma_desc: descriptor's physical bus address
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* @callback: whom to call when descriptor processing is done
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* @context: caller context (optional)
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*/
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struct talitos_request {
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struct talitos_desc *desc;
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dma_addr_t dma_desc;
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void (*callback) (struct device *dev, struct talitos_desc *desc,
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void *context, int error);
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void *context;
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};
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/* per-channel fifo management */
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struct talitos_channel {
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void __iomem *reg;
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/* request fifo */
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struct talitos_request *fifo;
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/* number of requests pending in channel h/w fifo */
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atomic_t submit_count ____cacheline_aligned;
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/* request submission (head) lock */
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spinlock_t head_lock ____cacheline_aligned;
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/* index to next free descriptor request */
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int head;
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/* request release (tail) lock */
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spinlock_t tail_lock ____cacheline_aligned;
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/* index to next in-progress/done descriptor request */
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int tail;
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};
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struct talitos_private {
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struct device *dev;
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struct platform_device *ofdev;
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void __iomem *reg;
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int irq[2];
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/* SEC global registers lock */
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spinlock_t reg_lock ____cacheline_aligned;
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/* SEC version geometry (from device tree node) */
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unsigned int num_channels;
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unsigned int chfifo_len;
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unsigned int exec_units;
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unsigned int desc_types;
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/* SEC Compatibility info */
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unsigned long features;
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/*
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* length of the request fifo
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* fifo_len is chfifo_len rounded up to next power of 2
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* so we can use bitwise ops to wrap
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*/
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unsigned int fifo_len;
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struct talitos_channel *chan;
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/* next channel to be assigned next incoming descriptor */
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atomic_t last_chan ____cacheline_aligned;
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/* request callback tasklet */
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struct tasklet_struct done_task[2];
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/* list of registered algorithms */
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struct list_head alg_list;
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/* hwrng device */
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struct hwrng rng;
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};
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/* .features flag */
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#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
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#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
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#define TALITOS_FTR_SHA224_HWINIT 0x00000004
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#define TALITOS_FTR_HMAC_OK 0x00000008
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/*
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* TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
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*/
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