ARM: vexpress: Initial common clock support
This patch makes Versatile Express use the common clock framework instead of the plat-versatile implementation. It defines clock provider for VE's OSCs (clock generators) and registers all required fixed and variable clock sources (for both motherboard and core tile). This is a simple conversion of the existing state and will be extended (and migrated to drivers/clk) in the near future. Signed-off-by: Pawel Moll <pawel.moll@arm.com>
This commit is contained in:
Pawel Moll
Родитель
56a34b03ff
Коммит
d1b8a775fd
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@ -310,14 +310,13 @@ config ARCH_VEXPRESS
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select ARM_AMBA
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select ARM_TIMER_SP804
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select CLKDEV_LOOKUP
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select HAVE_MACH_CLKDEV
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select COMMON_CLK
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select GENERIC_CLOCKEVENTS
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select HAVE_CLK
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select HAVE_PATA_PLATFORM
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select ICST
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select NO_IOPORT
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select PLAT_VERSATILE
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select PLAT_VERSATILE_CLOCK
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select PLAT_VERSATILE_CLCD
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help
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This enables support for the ARM Ltd Versatile Express boards.
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@ -112,45 +112,11 @@ static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
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};
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static long ct_round(struct clk *clk, unsigned long rate)
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{
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return rate;
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}
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static int ct_set(struct clk *clk, unsigned long rate)
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{
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u32 site = v2m_get_master_site();
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return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(site) | 1, rate);
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}
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static const struct clk_ops osc1_clk_ops = {
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.round = ct_round,
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.set = ct_set,
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};
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static struct clk osc1_clk = {
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.ops = &osc1_clk_ops,
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.rate = 24000000,
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};
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static struct clk ct_sp804_clk = {
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.rate = 1000000,
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};
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static struct clk_lookup lookups[] = {
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{ /* CLCD */
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.dev_id = "ct:clcd",
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.clk = &osc1_clk,
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}, { /* SP804 timers */
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.dev_id = "sp804",
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.con_id = "ct-timer0",
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.clk = &ct_sp804_clk,
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}, { /* SP804 timers */
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.dev_id = "sp804",
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.con_id = "ct-timer1",
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.clk = &ct_sp804_clk,
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},
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static struct v2m_osc ct_osc1 = {
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.osc = 1,
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.rate_min = 10000000,
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.rate_max = 80000000,
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.rate_default = 23750000,
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};
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static struct resource pmu_resources[] = {
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@ -183,14 +149,10 @@ static struct platform_device pmu_device = {
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.resource = pmu_resources,
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};
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static void __init ct_ca9x4_init_early(void)
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{
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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}
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static void __init ct_ca9x4_init(void)
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{
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int i;
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struct clk *clk;
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#ifdef CONFIG_CACHE_L2X0
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void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
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@ -202,6 +164,10 @@ static void __init ct_ca9x4_init(void)
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l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
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#endif
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ct_osc1.site = v2m_get_master_site();
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clk = v2m_osc_register("ct:osc1", &ct_osc1);
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clk_register_clkdev(clk, NULL, "ct:clcd");
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for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
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amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
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@ -243,7 +209,6 @@ struct ct_desc ct_ca9x4_desc __initdata = {
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.id = V2M_CT_ID_CA9,
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.name = "CA9x4",
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.map_io = ct_ca9x4_map_io,
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.init_early = ct_ca9x4_init_early,
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.init_irq = ct_ca9x4_init_irq,
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.init_tile = ct_ca9x4_init,
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#ifdef CONFIG_SMP
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@ -1,15 +0,0 @@
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#ifndef __ASM_MACH_CLKDEV_H
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#define __ASM_MACH_CLKDEV_H
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#include <plat/clock.h>
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struct clk {
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const struct clk_ops *ops;
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unsigned long rate;
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const struct icst_params *params;
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};
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#define __clk_get(clk) ({ 1; })
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#define __clk_put(clk) do { } while (0)
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#endif
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@ -1,6 +1,8 @@
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#ifndef __MACH_MOTHERBOARD_H
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#define __MACH_MOTHERBOARD_H
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#include <linux/clk-provider.h>
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/*
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* Physical addresses, offset from V2M_PA_CS0-3
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*/
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@ -147,4 +149,21 @@ struct ct_desc {
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extern struct ct_desc *ct_desc;
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/*
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* OSC clock provider
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*/
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struct v2m_osc {
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struct clk_hw hw;
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u8 site; /* 0 = motherboard, 1 = site 1, 2 = site 2 */
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u8 stack; /* board stack position */
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u16 osc;
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unsigned long rate_min;
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unsigned long rate_max;
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unsigned long rate_default;
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};
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#define to_v2m_osc(osc) container_of(osc, struct v2m_osc, hw)
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struct clk *v2m_osc_register(const char *name, struct v2m_osc *osc);
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#endif
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@ -16,6 +16,7 @@
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#include <linux/spinlock.h>
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#include <linux/usb/isp1760.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/mtd/physmap.h>
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#include <asm/arch_timer.h>
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@ -81,16 +82,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
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sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
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}
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static void __init v2m_timer_init(void)
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{
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v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
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v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
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}
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static struct sys_timer v2m_timer = {
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.init = v2m_timer_init,
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};
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static DEFINE_SPINLOCK(v2m_cfg_lock);
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@ -326,87 +317,133 @@ static struct amba_device *v2m_amba_devs[] __initdata = {
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};
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static long v2m_osc_round(struct clk *clk, unsigned long rate)
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static unsigned long v2m_osc_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct v2m_osc *osc = to_v2m_osc(hw);
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return !parent_rate ? osc->rate_default : parent_rate;
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}
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static long v2m_osc_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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struct v2m_osc *osc = to_v2m_osc(hw);
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if (WARN_ON(rate < osc->rate_min))
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rate = osc->rate_min;
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if (WARN_ON(rate > osc->rate_max))
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rate = osc->rate_max;
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return rate;
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}
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static int v2m_osc1_set(struct clk *clk, unsigned long rate)
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static int v2m_osc_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(SYS_CFG_SITE_MB) | 1,
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rate);
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struct v2m_osc *osc = to_v2m_osc(hw);
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v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(osc->site) |
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SYS_CFG_STACK(osc->stack) | osc->osc, rate);
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return 0;
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}
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static const struct clk_ops osc1_clk_ops = {
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.round = v2m_osc_round,
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.set = v2m_osc1_set,
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static struct clk_ops v2m_osc_ops = {
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.recalc_rate = v2m_osc_recalc_rate,
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.round_rate = v2m_osc_round_rate,
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.set_rate = v2m_osc_set_rate,
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};
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static struct clk osc1_clk = {
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.ops = &osc1_clk_ops,
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.rate = 24000000,
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struct clk * __init v2m_osc_register(const char *name, struct v2m_osc *osc)
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{
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struct clk_init_data init;
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WARN_ON(osc->site > 2);
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WARN_ON(osc->stack > 15);
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WARN_ON(osc->osc > 4095);
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init.name = name;
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init.ops = &v2m_osc_ops;
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init.flags = CLK_IS_ROOT;
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init.num_parents = 0;
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osc->hw.init = &init;
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return clk_register(NULL, &osc->hw);
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}
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static struct v2m_osc v2m_mb_osc1 = {
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.site = SYS_CFG_SITE_MB,
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.osc = 1,
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.rate_min = 23750000,
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.rate_max = 63500000,
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.rate_default = 23750000,
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};
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static struct clk osc2_clk = {
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.rate = 24000000,
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static const char *v2m_ref_clk_periphs[] __initconst = {
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"mb:wdt", "1000f000.wdt", "1c0f0000.wdt", /* SP805 WDT */
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};
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static struct clk v2m_sp804_clk = {
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.rate = 1000000,
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static const char *v2m_osc1_periphs[] __initconst = {
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"mb:clcd", "1001f000.clcd", "1c1f0000.clcd", /* PL111 CLCD */
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};
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static struct clk v2m_ref_clk = {
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.rate = 32768,
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static const char *v2m_osc2_periphs[] __initconst = {
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"mb:mmci", "10005000.mmci", "1c050000.mmci", /* PL180 MMCI */
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"mb:kmi0", "10006000.kmi", "1c060000.kmi", /* PL050 KMI0 */
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"mb:kmi1", "10007000.kmi", "1c070000.kmi", /* PL050 KMI1 */
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"mb:uart0", "10009000.uart", "1c090000.uart", /* PL011 UART0 */
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"mb:uart1", "1000a000.uart", "1c0a0000.uart", /* PL011 UART1 */
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"mb:uart2", "1000b000.uart", "1c0b0000.uart", /* PL011 UART2 */
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"mb:uart3", "1000c000.uart", "1c0c0000.uart", /* PL011 UART3 */
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};
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static struct clk dummy_apb_pclk;
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static void __init v2m_clk_init(void)
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{
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struct clk *clk;
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int i;
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static struct clk_lookup v2m_lookups[] = {
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{ /* AMBA bus clock */
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.con_id = "apb_pclk",
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.clk = &dummy_apb_pclk,
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}, { /* UART0 */
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.dev_id = "mb:uart0",
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.clk = &osc2_clk,
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}, { /* UART1 */
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.dev_id = "mb:uart1",
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.clk = &osc2_clk,
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}, { /* UART2 */
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.dev_id = "mb:uart2",
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.clk = &osc2_clk,
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}, { /* UART3 */
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.dev_id = "mb:uart3",
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.clk = &osc2_clk,
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}, { /* KMI0 */
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.dev_id = "mb:kmi0",
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.clk = &osc2_clk,
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}, { /* KMI1 */
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.dev_id = "mb:kmi1",
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.clk = &osc2_clk,
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}, { /* MMC0 */
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.dev_id = "mb:mmci",
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.clk = &osc2_clk,
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}, { /* CLCD */
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.dev_id = "mb:clcd",
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.clk = &osc1_clk,
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}, { /* SP805 WDT */
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.dev_id = "mb:wdt",
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.clk = &v2m_ref_clk,
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}, { /* SP804 timers */
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.dev_id = "sp804",
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.con_id = "v2m-timer0",
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.clk = &v2m_sp804_clk,
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}, { /* SP804 timers */
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.dev_id = "sp804",
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.con_id = "v2m-timer1",
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.clk = &v2m_sp804_clk,
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},
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clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
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CLK_IS_ROOT, 0);
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WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));
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clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL,
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CLK_IS_ROOT, 32768);
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for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++)
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WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i]));
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clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL,
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CLK_IS_ROOT, 1000000);
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WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804"));
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WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804"));
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clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1);
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for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++)
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WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i]));
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clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL,
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CLK_IS_ROOT, 24000000);
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for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
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WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]));
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}
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static void __init v2m_timer_init(void)
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{
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v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
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v2m_clk_init();
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v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
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}
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static struct sys_timer v2m_timer = {
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.init = v2m_timer_init,
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};
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static void __init v2m_init_early(void)
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{
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ct_desc->init_early();
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clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
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if (ct_desc->init_early)
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ct_desc->init_early();
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versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
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}
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@ -530,77 +567,6 @@ void __init v2m_dt_map_io(void)
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#endif
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}
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static struct clk_lookup v2m_dt_lookups[] = {
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{ /* AMBA bus clock */
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.con_id = "apb_pclk",
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.clk = &dummy_apb_pclk,
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}, { /* SP804 timers */
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.dev_id = "sp804",
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.con_id = "v2m-timer0",
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.clk = &v2m_sp804_clk,
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}, { /* SP804 timers */
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.dev_id = "sp804",
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.con_id = "v2m-timer1",
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.clk = &v2m_sp804_clk,
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}, { /* PL180 MMCI */
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.dev_id = "mb:mmci", /* 10005000.mmci */
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.clk = &osc2_clk,
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}, { /* PL050 KMI0 */
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.dev_id = "10006000.kmi",
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.clk = &osc2_clk,
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}, { /* PL050 KMI1 */
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.dev_id = "10007000.kmi",
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.clk = &osc2_clk,
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}, { /* PL011 UART0 */
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.dev_id = "10009000.uart",
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.clk = &osc2_clk,
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}, { /* PL011 UART1 */
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.dev_id = "1000a000.uart",
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.clk = &osc2_clk,
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}, { /* PL011 UART2 */
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.dev_id = "1000b000.uart",
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.clk = &osc2_clk,
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}, { /* PL011 UART3 */
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.dev_id = "1000c000.uart",
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.clk = &osc2_clk,
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}, { /* SP805 WDT */
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.dev_id = "1000f000.wdt",
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.clk = &v2m_ref_clk,
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}, { /* PL111 CLCD */
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.dev_id = "1001f000.clcd",
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.clk = &osc1_clk,
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},
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/* RS1 memory map */
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{ /* PL180 MMCI */
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.dev_id = "mb:mmci", /* 1c050000.mmci */
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.clk = &osc2_clk,
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}, { /* PL050 KMI0 */
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.dev_id = "1c060000.kmi",
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.clk = &osc2_clk,
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}, { /* PL050 KMI1 */
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.dev_id = "1c070000.kmi",
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.clk = &osc2_clk,
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}, { /* PL011 UART0 */
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.dev_id = "1c090000.uart",
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.clk = &osc2_clk,
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}, { /* PL011 UART1 */
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.dev_id = "1c0a0000.uart",
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.clk = &osc2_clk,
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}, { /* PL011 UART2 */
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.dev_id = "1c0b0000.uart",
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||||
.clk = &osc2_clk,
|
||||
}, { /* PL011 UART3 */
|
||||
.dev_id = "1c0c0000.uart",
|
||||
.clk = &osc2_clk,
|
||||
}, { /* SP805 WDT */
|
||||
.dev_id = "1c0f0000.wdt",
|
||||
.clk = &v2m_ref_clk,
|
||||
}, { /* PL111 CLCD */
|
||||
.dev_id = "1c1f0000.clcd",
|
||||
.clk = &osc1_clk,
|
||||
},
|
||||
};
|
||||
|
||||
void __init v2m_dt_init_early(void)
|
||||
{
|
||||
struct device_node *node;
|
||||
|
|
@ -622,8 +588,6 @@ void __init v2m_dt_init_early(void)
|
|||
pr_warning("vexpress: DT HBI (%x) is not matching "
|
||||
"hardware (%x)!\n", dt_hbi, hbi);
|
||||
}
|
||||
|
||||
clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
|
||||
}
|
||||
|
||||
static struct of_device_id vexpress_irq_match[] __initdata = {
|
||||
|
|
@ -645,6 +609,8 @@ static void __init v2m_dt_timer_init(void)
|
|||
node = of_find_compatible_node(NULL, NULL, "arm,sp810");
|
||||
v2m_sysctl_init(of_iomap(node, 0));
|
||||
|
||||
v2m_clk_init();
|
||||
|
||||
err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
|
||||
if (WARN_ON(err))
|
||||
return;
|
||||
|
|
|
|||
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