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media: vpfe_capture: remove deprecated davinci drivers 

The vpfe_capture drivers do not use the vb2 framework for streaming
video, instead they use the old vb1 framework and nobody stepped in to
convert these drivers to vb2.

The hardware is very old, so the decision was made to remove them
altogether since we want to get rid of the old vb1 framework.

Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Acked-by: Lad Prabhakar <prabhakar.csengg@gmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Hans Verkuil 2023-01-10 13:13:41 +01:00 коммит произвёл Mauro Carvalho Chehab
Родитель 3673237b62
Коммит d2a8e92f0b
17 изменённых файлов: 0 добавлений и 6713 удалений
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1
drivers/staging/media/Kconfig
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@ -54,7 +54,6 @@ if STAGING_MEDIA_DEPRECATED
source "drivers/staging/media/deprecated/atmel/Kconfig"
source "drivers/staging/media/deprecated/saa7146/Kconfig"
source "drivers/staging/media/deprecated/tm6000/Kconfig"
source "drivers/staging/media/deprecated/vpfe_capture/Kconfig"
endif
endif

1
drivers/staging/media/Makefile
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@ -10,5 +10,4 @@ obj-$(CONFIG_VIDEO_SUNXI) += sunxi/
obj-$(CONFIG_VIDEO_TEGRA) += tegra-video/
obj-$(CONFIG_VIDEO_IPU3_IMGU) += ipu3/
obj-$(CONFIG_VIDEO_TM6000) += deprecated/tm6000/
obj-y += deprecated/vpfe_capture/
obj-y += deprecated/saa7146/

58
drivers/staging/media/deprecated/vpfe_capture/Kconfig
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@ -1,58 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
config VIDEO_DM6446_CCDC
tristate "TI DM6446 CCDC video capture driver"
depends on V4L_PLATFORM_DRIVERS
depends on VIDEO_DEV
depends on ARCH_DAVINCI || COMPILE_TEST
depends on I2C
select VIDEOBUF_DMA_CONTIG
help
Enables DaVinci CCD hw module. DaVinci CCDC hw interfaces
with decoder modules such as TVP5146 over BT656 or
sensor module such as MT9T001 over a raw interface. This
module configures the interface and CCDC/ISIF to do
video frame capture from slave decoders.
This driver is deprecated and is scheduled for removal by
the beginning of 2023. See the TODO file for more information.
To compile this driver as a module, choose M here. There will
be two modules called vpfe_capture.ko and dm644x_ccdc.ko
config VIDEO_DM355_CCDC
tristate "TI DM355 CCDC video capture driver"
depends on V4L_PLATFORM_DRIVERS
depends on VIDEO_DEV
depends on ARCH_DAVINCI || COMPILE_TEST
depends on I2C
select VIDEOBUF_DMA_CONTIG
help
Enables DM355 CCD hw module. DM355 CCDC hw interfaces
with decoder modules such as TVP5146 over BT656 or
sensor module such as MT9T001 over a raw interface. This
module configures the interface and CCDC/ISIF to do
video frame capture from a slave decoders
This driver is deprecated and is scheduled for removal by
the beginning of 2023. See the TODO file for more information.
To compile this driver as a module, choose M here. There will
be two modules called vpfe_capture.ko and dm355_ccdc.ko
config VIDEO_DM365_ISIF
tristate "TI DM365 ISIF video capture driver"
depends on V4L_PLATFORM_DRIVERS
depends on VIDEO_DEV
depends on ARCH_DAVINCI || COMPILE_TEST
depends on I2C
select VIDEOBUF_DMA_CONTIG
help
Enables ISIF hw module. This is the hardware module for
configuring ISIF in VPFE to capture Raw Bayer RGB data from
a image sensor or YUV data from a YUV source.
This driver is deprecated and is scheduled for removal by
the beginning of 2023. See the TODO file for more information.
To compile this driver as a module, choose M here. There will
be two modules called vpfe_capture.ko and isif.ko

4
drivers/staging/media/deprecated/vpfe_capture/Makefile
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@ -1,4 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_VIDEO_DM6446_CCDC) += vpfe_capture.o dm644x_ccdc.o
obj-$(CONFIG_VIDEO_DM355_CCDC) += vpfe_capture.o dm355_ccdc.o
obj-$(CONFIG_VIDEO_DM365_ISIF) += vpfe_capture.o isif.o

7
drivers/staging/media/deprecated/vpfe_capture/TODO
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@ -1,7 +0,0 @@
These are one of the few drivers still not using the vb2
framework, so these drivers are now deprecated with the intent of
removing them altogether by the beginning of 2023.
In order to keep these drivers they have to be converted to vb2.
If someone is interested in doing this work, then contact the
linux-media mailinglist (https://linuxtv.org/lists.php).

80
drivers/staging/media/deprecated/vpfe_capture/ccdc_hw_device.h
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@ -1,80 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2008-2009 Texas Instruments Inc
*
* ccdc device API
*/
#ifndef _CCDC_HW_DEVICE_H
#define _CCDC_HW_DEVICE_H
#ifdef __KERNEL__
#include <linux/videodev2.h>
#include <linux/device.h>
#include <media/davinci/vpfe_types.h>
#include <media/davinci/ccdc_types.h>
/*
* ccdc hw operations
*/
struct ccdc_hw_ops {
/* Pointer to initialize function to initialize ccdc device */
int (*open) (struct device *dev);
/* Pointer to deinitialize function */
int (*close) (struct device *dev);
/* set ccdc base address */
void (*set_ccdc_base)(void *base, int size);
/* Pointer to function to enable or disable ccdc */
void (*enable) (int en);
/* reset sbl. only for 6446 */
void (*reset) (void);
/* enable output to sdram */
void (*enable_out_to_sdram) (int en);
/* Pointer to function to set hw parameters */
int (*set_hw_if_params) (struct vpfe_hw_if_param *param);
/* get interface parameters */
int (*get_hw_if_params) (struct vpfe_hw_if_param *param);
/* Pointer to function to configure ccdc */
int (*configure) (void);
/* Pointer to function to set buffer type */
int (*set_buftype) (enum ccdc_buftype buf_type);
/* Pointer to function to get buffer type */
enum ccdc_buftype (*get_buftype) (void);
/* Pointer to function to set frame format */
int (*set_frame_format) (enum ccdc_frmfmt frm_fmt);
/* Pointer to function to get frame format */
enum ccdc_frmfmt (*get_frame_format) (void);
/* enumerate hw pix formats */
int (*enum_pix)(u32 *hw_pix, int i);
/* Pointer to function to set buffer type */
u32 (*get_pixel_format) (void);
/* Pointer to function to get pixel format. */
int (*set_pixel_format) (u32 pixfmt);
/* Pointer to function to set image window */
int (*set_image_window) (struct v4l2_rect *win);
/* Pointer to function to set image window */
void (*get_image_window) (struct v4l2_rect *win);
/* Pointer to function to get line length */
unsigned int (*get_line_length) (void);
/* Pointer to function to set frame buffer address */
void (*setfbaddr) (unsigned long addr);
/* Pointer to function to get field id */
int (*getfid) (void);
};
struct ccdc_hw_device {
/* ccdc device name */
char name[32];
/* module owner */
struct module *owner;
/* hw ops */
struct ccdc_hw_ops hw_ops;
};
/* Used by CCDC module to register & unregister with vpfe capture driver */
int vpfe_register_ccdc_device(const struct ccdc_hw_device *dev);
void vpfe_unregister_ccdc_device(const struct ccdc_hw_device *dev);
#endif
#endif

934
drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc.c
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@ -1,934 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2005-2009 Texas Instruments Inc
*
* CCDC hardware module for DM355
* ------------------------------
*
* This module is for configuring DM355 CCD controller of VPFE to capture
* Raw yuv or Bayer RGB data from a decoder. CCDC has several modules
* such as Defect Pixel Correction, Color Space Conversion etc to
* pre-process the Bayer RGB data, before writing it to SDRAM.
*
* TODO: 1) Raw bayer parameter settings and bayer capture
* 2) Split module parameter structure to module specific ioctl structs
* 3) add support for lense shading correction
* 4) investigate if enum used for user space type definition
* to be replaced by #defines or integer
*/
#include <linux/platform_device.h>
#include <linux/uaccess.h>
#include <linux/videodev2.h>
#include <linux/err.h>
#include <linux/module.h>
#include "dm355_ccdc.h"
#include <media/davinci/vpss.h>
#include "dm355_ccdc_regs.h"
#include "ccdc_hw_device.h"
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("CCDC Driver for DM355");
MODULE_AUTHOR("Texas Instruments");
static struct ccdc_oper_config {
struct device *dev;
/* CCDC interface type */
enum vpfe_hw_if_type if_type;
/* Raw Bayer configuration */
struct ccdc_params_raw bayer;
/* YCbCr configuration */
struct ccdc_params_ycbcr ycbcr;
/* ccdc base address */
void __iomem *base_addr;
} ccdc_cfg = {
/* Raw configurations */
.bayer = {
.pix_fmt = CCDC_PIXFMT_RAW,
.frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
.win = CCDC_WIN_VGA,
.fid_pol = VPFE_PINPOL_POSITIVE,
.vd_pol = VPFE_PINPOL_POSITIVE,
.hd_pol = VPFE_PINPOL_POSITIVE,
.gain = {
.r_ye = 256,
.gb_g = 256,
.gr_cy = 256,
.b_mg = 256
},
.config_params = {
.datasft = 2,
.mfilt1 = CCDC_NO_MEDIAN_FILTER1,
.mfilt2 = CCDC_NO_MEDIAN_FILTER2,
.alaw = {
.gamma_wd = 2,
},
.blk_clamp = {
.sample_pixel = 1,
.dc_sub = 25
},
.col_pat_field0 = {
.olop = CCDC_GREEN_BLUE,
.olep = CCDC_BLUE,
.elop = CCDC_RED,
.elep = CCDC_GREEN_RED
},
.col_pat_field1 = {
.olop = CCDC_GREEN_BLUE,
.olep = CCDC_BLUE,
.elop = CCDC_RED,
.elep = CCDC_GREEN_RED
},
},
},
/* YCbCr configuration */
.ycbcr = {
.win = CCDC_WIN_PAL,
.pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
.frm_fmt = CCDC_FRMFMT_INTERLACED,
.fid_pol = VPFE_PINPOL_POSITIVE,
.vd_pol = VPFE_PINPOL_POSITIVE,
.hd_pol = VPFE_PINPOL_POSITIVE,
.bt656_enable = 1,
.pix_order = CCDC_PIXORDER_CBYCRY,
.buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED
},
};
/* Raw Bayer formats */
static u32 ccdc_raw_bayer_pix_formats[] =
{V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
/* Raw YUV formats */
static u32 ccdc_raw_yuv_pix_formats[] =
{V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
/* register access routines */
static inline u32 regr(u32 offset)
{
return __raw_readl(ccdc_cfg.base_addr + offset);
}
static inline void regw(u32 val, u32 offset)
{
__raw_writel(val, ccdc_cfg.base_addr + offset);
}
static void ccdc_enable(int en)
{
unsigned int temp;
temp = regr(SYNCEN);
temp &= (~CCDC_SYNCEN_VDHDEN_MASK);
temp |= (en & CCDC_SYNCEN_VDHDEN_MASK);
regw(temp, SYNCEN);
}
static void ccdc_enable_output_to_sdram(int en)
{
unsigned int temp;
temp = regr(SYNCEN);
temp &= (~(CCDC_SYNCEN_WEN_MASK));
temp |= ((en << CCDC_SYNCEN_WEN_SHIFT) & CCDC_SYNCEN_WEN_MASK);
regw(temp, SYNCEN);
}
static void ccdc_config_gain_offset(void)
{
/* configure gain */
regw(ccdc_cfg.bayer.gain.r_ye, RYEGAIN);
regw(ccdc_cfg.bayer.gain.gr_cy, GRCYGAIN);
regw(ccdc_cfg.bayer.gain.gb_g, GBGGAIN);
regw(ccdc_cfg.bayer.gain.b_mg, BMGGAIN);
/* configure offset */
regw(ccdc_cfg.bayer.ccdc_offset, OFFSET);
}
/*
* ccdc_restore_defaults()
* This function restore power on defaults in the ccdc registers
*/
static int ccdc_restore_defaults(void)
{
int i;
dev_dbg(ccdc_cfg.dev, "\nstarting ccdc_restore_defaults...");
/* set all registers to zero */
for (i = 0; i <= CCDC_REG_LAST; i += 4)
regw(0, i);
/* now override the values with power on defaults in registers */
regw(MODESET_DEFAULT, MODESET);
/* no culling support */
regw(CULH_DEFAULT, CULH);
regw(CULV_DEFAULT, CULV);
/* Set default Gain and Offset */
ccdc_cfg.bayer.gain.r_ye = GAIN_DEFAULT;
ccdc_cfg.bayer.gain.gb_g = GAIN_DEFAULT;
ccdc_cfg.bayer.gain.gr_cy = GAIN_DEFAULT;
ccdc_cfg.bayer.gain.b_mg = GAIN_DEFAULT;
ccdc_config_gain_offset();
regw(OUTCLIP_DEFAULT, OUTCLIP);
regw(LSCCFG2_DEFAULT, LSCCFG2);
/* select ccdc input */
if (vpss_select_ccdc_source(VPSS_CCDCIN)) {
dev_dbg(ccdc_cfg.dev, "\ncouldn't select ccdc input source");
return -EFAULT;
}
/* select ccdc clock */
if (vpss_enable_clock(VPSS_CCDC_CLOCK, 1) < 0) {
dev_dbg(ccdc_cfg.dev, "\ncouldn't enable ccdc clock");
return -EFAULT;
}
dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_restore_defaults...");
return 0;
}
static int ccdc_open(struct device *device)
{
return ccdc_restore_defaults();
}
static int ccdc_close(struct device *device)
{
/* disable clock */
vpss_enable_clock(VPSS_CCDC_CLOCK, 0);
/* do nothing for now */
return 0;
}
/*
* ccdc_setwin()
* This function will configure the window size to
* be capture in CCDC reg.
*/
static void ccdc_setwin(struct v4l2_rect *image_win,
enum ccdc_frmfmt frm_fmt, int ppc)
{
int horz_start, horz_nr_pixels;
int vert_start, vert_nr_lines;
int mid_img = 0;
dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_setwin...");
/*
* ppc - per pixel count. indicates how many pixels per cell
* output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
* raw capture this is 1
*/
horz_start = image_win->left << (ppc - 1);
horz_nr_pixels = ((image_win->width) << (ppc - 1)) - 1;
/* Writing the horizontal info into the registers */
regw(horz_start, SPH);
regw(horz_nr_pixels, NPH);
vert_start = image_win->top;
if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
vert_nr_lines = (image_win->height >> 1) - 1;
vert_start >>= 1;
/* Since first line doesn't have any data */
vert_start += 1;
/* configure VDINT0 and VDINT1 */
regw(vert_start, VDINT0);
} else {
/* Since first line doesn't have any data */
vert_start += 1;
vert_nr_lines = image_win->height - 1;
/* configure VDINT0 and VDINT1 */
mid_img = vert_start + (image_win->height / 2);
regw(vert_start, VDINT0);
regw(mid_img, VDINT1);
}
regw(vert_start & CCDC_START_VER_ONE_MASK, SLV0);
regw(vert_start & CCDC_START_VER_TWO_MASK, SLV1);
regw(vert_nr_lines & CCDC_NUM_LINES_VER, NLV);
dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_setwin...");
}
/* This function will configure CCDC for YCbCr video capture */
static void ccdc_config_ycbcr(void)
{
struct ccdc_params_ycbcr *params = &ccdc_cfg.ycbcr;
u32 temp;
/* first set the CCDC power on defaults values in all registers */
dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_ycbcr...");
ccdc_restore_defaults();
/* configure pixel format & video frame format */
temp = (((params->pix_fmt & CCDC_INPUT_MODE_MASK) <<
CCDC_INPUT_MODE_SHIFT) |
((params->frm_fmt & CCDC_FRM_FMT_MASK) <<
CCDC_FRM_FMT_SHIFT));
/* setup BT.656 sync mode */
if (params->bt656_enable) {
regw(CCDC_REC656IF_BT656_EN, REC656IF);
/*
* configure the FID, VD, HD pin polarity fld,hd pol positive,
* vd negative, 8-bit pack mode
*/
temp |= CCDC_VD_POL_NEGATIVE;
} else { /* y/c external sync mode */
temp |= (((params->fid_pol & CCDC_FID_POL_MASK) <<
CCDC_FID_POL_SHIFT) |
((params->hd_pol & CCDC_HD_POL_MASK) <<
CCDC_HD_POL_SHIFT) |
((params->vd_pol & CCDC_VD_POL_MASK) <<
CCDC_VD_POL_SHIFT));
}
/* pack the data to 8-bit */
temp |= CCDC_DATA_PACK_ENABLE;
regw(temp, MODESET);
/* configure video window */
ccdc_setwin(&params->win, params->frm_fmt, 2);
/* configure the order of y cb cr in SD-RAM */
temp = (params->pix_order << CCDC_Y8POS_SHIFT);
temp |= CCDC_LATCH_ON_VSYNC_DISABLE | CCDC_CCDCFG_FIDMD_NO_LATCH_VSYNC;
regw(temp, CCDCFG);
/*
* configure the horizontal line offset. This is done by rounding up
* width to a multiple of 16 pixels and multiply by two to account for
* y:cb:cr 4:2:2 data
*/
regw(((params->win.width * 2 + 31) >> 5), HSIZE);
/* configure the memory line offset */
if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED) {
/* two fields are interleaved in memory */
regw(CCDC_SDOFST_FIELD_INTERLEAVED, SDOFST);
}
dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_config_ycbcr...\n");
}
/*
* ccdc_config_black_clamp()
* configure parameters for Optical Black Clamp
*/
static void ccdc_config_black_clamp(struct ccdc_black_clamp *bclamp)
{
u32 val;
if (!bclamp->b_clamp_enable) {
/* configure DCSub */
regw(bclamp->dc_sub & CCDC_BLK_DC_SUB_MASK, DCSUB);
regw(0x0000, CLAMP);
return;
}
/* Enable the Black clamping, set sample lines and pixels */
val = (bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) |
((bclamp->sample_pixel & CCDC_BLK_SAMPLE_LN_MASK) <<
CCDC_BLK_SAMPLE_LN_SHIFT) | CCDC_BLK_CLAMP_ENABLE;
regw(val, CLAMP);
/* If Black clamping is enable then make dcsub 0 */
val = (bclamp->sample_ln & CCDC_NUM_LINE_CALC_MASK)
<< CCDC_NUM_LINE_CALC_SHIFT;
regw(val, DCSUB);
}
/*
* ccdc_config_black_compense()
* configure parameters for Black Compensation
*/
static void ccdc_config_black_compense(struct ccdc_black_compensation *bcomp)
{
u32 val;
val = (bcomp->b & CCDC_BLK_COMP_MASK) |
((bcomp->gb & CCDC_BLK_COMP_MASK) <<
CCDC_BLK_COMP_GB_COMP_SHIFT);
regw(val, BLKCMP1);
val = ((bcomp->gr & CCDC_BLK_COMP_MASK) <<
CCDC_BLK_COMP_GR_COMP_SHIFT) |
((bcomp->r & CCDC_BLK_COMP_MASK) <<
CCDC_BLK_COMP_R_COMP_SHIFT);
regw(val, BLKCMP0);
}
/*
* ccdc_write_dfc_entry()
* write an entry in the dfc table.
*/
static int ccdc_write_dfc_entry(int index, struct ccdc_vertical_dft *dfc)
{
/* TODO This is to be re-visited and adjusted */
#define DFC_WRITE_WAIT_COUNT 1000
u32 val, count = DFC_WRITE_WAIT_COUNT;
regw(dfc->dft_corr_vert[index], DFCMEM0);
regw(dfc->dft_corr_horz[index], DFCMEM1);
regw(dfc->dft_corr_sub1[index], DFCMEM2);
regw(dfc->dft_corr_sub2[index], DFCMEM3);
regw(dfc->dft_corr_sub3[index], DFCMEM4);
/* set WR bit to write */
val = regr(DFCMEMCTL) | CCDC_DFCMEMCTL_DFCMWR_MASK;
regw(val, DFCMEMCTL);
/*
* Assume, it is very short. If we get an error, we need to
* adjust this value
*/
while (regr(DFCMEMCTL) & CCDC_DFCMEMCTL_DFCMWR_MASK)
count--;
/*
* TODO We expect the count to be non-zero to be successful. Adjust
* the count if write requires more time
*/
if (count) {
dev_err(ccdc_cfg.dev, "defect table write timeout !!!\n");
return -1;
}
return 0;
}
/*
* ccdc_config_vdfc()
* configure parameters for Vertical Defect Correction
*/
static int ccdc_config_vdfc(struct ccdc_vertical_dft *dfc)
{
u32 val;
int i;
/* Configure General Defect Correction. The table used is from IPIPE */
val = dfc->gen_dft_en & CCDC_DFCCTL_GDFCEN_MASK;
/* Configure Vertical Defect Correction if needed */
if (!dfc->ver_dft_en) {
/* Enable only General Defect Correction */
regw(val, DFCCTL);
return 0;
}
if (dfc->table_size > CCDC_DFT_TABLE_SIZE)
return -EINVAL;
val |= CCDC_DFCCTL_VDFC_DISABLE;
val |= (dfc->dft_corr_ctl.vdfcsl & CCDC_DFCCTL_VDFCSL_MASK) <<
CCDC_DFCCTL_VDFCSL_SHIFT;
val |= (dfc->dft_corr_ctl.vdfcuda & CCDC_DFCCTL_VDFCUDA_MASK) <<
CCDC_DFCCTL_VDFCUDA_SHIFT;
val |= (dfc->dft_corr_ctl.vdflsft & CCDC_DFCCTL_VDFLSFT_MASK) <<
CCDC_DFCCTL_VDFLSFT_SHIFT;
regw(val , DFCCTL);
/* clear address ptr to offset 0 */
val = CCDC_DFCMEMCTL_DFCMARST_MASK << CCDC_DFCMEMCTL_DFCMARST_SHIFT;
/* write defect table entries */
for (i = 0; i < dfc->table_size; i++) {
/* increment address for non zero index */
if (i != 0)
val = CCDC_DFCMEMCTL_INC_ADDR;
regw(val, DFCMEMCTL);
if (ccdc_write_dfc_entry(i, dfc) < 0)
return -EFAULT;
}
/* update saturation level and enable dfc */
regw(dfc->saturation_ctl & CCDC_VDC_DFCVSAT_MASK, DFCVSAT);
val = regr(DFCCTL) | (CCDC_DFCCTL_VDFCEN_MASK <<
CCDC_DFCCTL_VDFCEN_SHIFT);
regw(val, DFCCTL);
return 0;
}
/*
* ccdc_config_csc()
* configure parameters for color space conversion
* Each register CSCM0-7 has two values in S8Q5 format.
*/
static void ccdc_config_csc(struct ccdc_csc *csc)
{
u32 val1 = 0, val2;
int i;
if (!csc->enable)
return;
/* Enable the CSC sub-module */
regw(CCDC_CSC_ENABLE, CSCCTL);
/* Converting the co-eff as per the format of the register */
for (i = 0; i < CCDC_CSC_COEFF_TABLE_SIZE; i++) {
if ((i % 2) == 0) {
/* CSCM - LSB */
val1 = (csc->coeff[i].integer &
CCDC_CSC_COEF_INTEG_MASK)
<< CCDC_CSC_COEF_INTEG_SHIFT;
/*
* convert decimal part to binary. Use 2 decimal
* precision, user values range from .00 - 0.99
*/
val1 |= (((csc->coeff[i].decimal &
CCDC_CSC_COEF_DECIMAL_MASK) *
CCDC_CSC_DEC_MAX) / 100);
} else {
/* CSCM - MSB */
val2 = (csc->coeff[i].integer &
CCDC_CSC_COEF_INTEG_MASK)
<< CCDC_CSC_COEF_INTEG_SHIFT;
val2 |= (((csc->coeff[i].decimal &
CCDC_CSC_COEF_DECIMAL_MASK) *
CCDC_CSC_DEC_MAX) / 100);
val2 <<= CCDC_CSCM_MSB_SHIFT;
val2 |= val1;
regw(val2, (CSCM0 + ((i - 1) << 1)));
}
}
}
/*
* ccdc_config_color_patterns()
* configure parameters for color patterns
*/
static void ccdc_config_color_patterns(struct ccdc_col_pat *pat0,
struct ccdc_col_pat *pat1)
{
u32 val;
val = (pat0->olop | (pat0->olep << 2) | (pat0->elop << 4) |
(pat0->elep << 6) | (pat1->olop << 8) | (pat1->olep << 10) |
(pat1->elop << 12) | (pat1->elep << 14));
regw(val, COLPTN);
}
/* This function will configure CCDC for Raw mode image capture */
static int ccdc_config_raw(void)
{
struct ccdc_params_raw *params = &ccdc_cfg.bayer;
struct ccdc_config_params_raw *config_params =
&ccdc_cfg.bayer.config_params;
unsigned int val;
dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_raw...");
/* restore power on defaults to register */
ccdc_restore_defaults();
/* CCDCFG register:
* set CCD Not to swap input since input is RAW data
* set FID detection function to Latch at V-Sync
* set WENLOG - ccdc valid area to AND
* set TRGSEL to WENBIT
* set EXTRG to DISABLE
* disable latching function on VSYNC - shadowed registers
*/
regw(CCDC_YCINSWP_RAW | CCDC_CCDCFG_FIDMD_LATCH_VSYNC |
CCDC_CCDCFG_WENLOG_AND | CCDC_CCDCFG_TRGSEL_WEN |
CCDC_CCDCFG_EXTRG_DISABLE | CCDC_LATCH_ON_VSYNC_DISABLE, CCDCFG);
/*
* Set VDHD direction to input, input type to raw input
* normal data polarity, do not use external WEN
*/
val = (CCDC_VDHDOUT_INPUT | CCDC_RAW_IP_MODE | CCDC_DATAPOL_NORMAL |
CCDC_EXWEN_DISABLE);
/*
* Configure the vertical sync polarity (MODESET.VDPOL), horizontal
* sync polarity (MODESET.HDPOL), field id polarity (MODESET.FLDPOL),
* frame format(progressive or interlace), & pixel format (Input mode)
*/
val |= (((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) |
((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) |
((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) |
((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) |
((params->pix_fmt & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT));
/* set pack for alaw compression */
if ((config_params->data_sz == CCDC_DATA_8BITS) ||
config_params->alaw.enable)
val |= CCDC_DATA_PACK_ENABLE;
/* Configure for LPF */
if (config_params->lpf_enable)
val |= (config_params->lpf_enable & CCDC_LPF_MASK) <<
CCDC_LPF_SHIFT;
/* Configure the data shift */
val |= (config_params->datasft & CCDC_DATASFT_MASK) <<
CCDC_DATASFT_SHIFT;
regw(val , MODESET);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to MODESET...\n", val);
/* Configure the Median Filter threshold */
regw((config_params->med_filt_thres) & CCDC_MED_FILT_THRESH, MEDFILT);
/* Configure GAMMAWD register. defaur 11-2, and Mosaic cfa pattern */
val = CCDC_GAMMA_BITS_11_2 << CCDC_GAMMAWD_INPUT_SHIFT |
CCDC_CFA_MOSAIC;
/* Enable and configure aLaw register if needed */
if (config_params->alaw.enable) {
val |= (CCDC_ALAW_ENABLE |
((config_params->alaw.gamma_wd &
CCDC_ALAW_GAMMA_WD_MASK) <<
CCDC_GAMMAWD_INPUT_SHIFT));
}
/* Configure Median filter1 & filter2 */
val |= ((config_params->mfilt1 << CCDC_MFILT1_SHIFT) |
(config_params->mfilt2 << CCDC_MFILT2_SHIFT));
regw(val, GAMMAWD);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to GAMMAWD...\n", val);
/* configure video window */
ccdc_setwin(&params->win, params->frm_fmt, 1);
/* Optical Clamp Averaging */
ccdc_config_black_clamp(&config_params->blk_clamp);
/* Black level compensation */
ccdc_config_black_compense(&config_params->blk_comp);
/* Vertical Defect Correction if needed */
if (ccdc_config_vdfc(&config_params->vertical_dft) < 0)
return -EFAULT;
/* color space conversion */
ccdc_config_csc(&config_params->csc);
/* color pattern */
ccdc_config_color_patterns(&config_params->col_pat_field0,
&config_params->col_pat_field1);
/* Configure the Gain & offset control */
ccdc_config_gain_offset();
dev_dbg(ccdc_cfg.dev, "\nWriting %x to COLPTN...\n", val);
/* Configure DATAOFST register */
val = (config_params->data_offset.horz_offset & CCDC_DATAOFST_MASK) <<
CCDC_DATAOFST_H_SHIFT;
val |= (config_params->data_offset.vert_offset & CCDC_DATAOFST_MASK) <<
CCDC_DATAOFST_V_SHIFT;
regw(val, DATAOFST);
/* configuring HSIZE register */
val = (params->horz_flip_enable & CCDC_HSIZE_FLIP_MASK) <<
CCDC_HSIZE_FLIP_SHIFT;
/* If pack 8 is enable then 1 pixel will take 1 byte */
if ((config_params->data_sz == CCDC_DATA_8BITS) ||
config_params->alaw.enable) {
val |= (((params->win.width) + 31) >> 5) &
CCDC_HSIZE_VAL_MASK;
/* adjust to multiple of 32 */
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to HSIZE...\n",
(((params->win.width) + 31) >> 5) &
CCDC_HSIZE_VAL_MASK);
} else {
/* else one pixel will take 2 byte */
val |= (((params->win.width * 2) + 31) >> 5) &
CCDC_HSIZE_VAL_MASK;
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to HSIZE...\n",
(((params->win.width * 2) + 31) >> 5) &
CCDC_HSIZE_VAL_MASK);
}
regw(val, HSIZE);
/* Configure SDOFST register */
if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
if (params->image_invert_enable) {
/* For interlace inverse mode */
regw(CCDC_SDOFST_INTERLACE_INVERSE, SDOFST);
dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
CCDC_SDOFST_INTERLACE_INVERSE);
} else {
/* For interlace non inverse mode */
regw(CCDC_SDOFST_INTERLACE_NORMAL, SDOFST);
dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
CCDC_SDOFST_INTERLACE_NORMAL);
}
} else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
if (params->image_invert_enable) {
/* For progessive inverse mode */
regw(CCDC_SDOFST_PROGRESSIVE_INVERSE, SDOFST);
dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
CCDC_SDOFST_PROGRESSIVE_INVERSE);
} else {
/* For progessive non inverse mode */
regw(CCDC_SDOFST_PROGRESSIVE_NORMAL, SDOFST);
dev_dbg(ccdc_cfg.dev, "\nWriting %x to SDOFST...\n",
CCDC_SDOFST_PROGRESSIVE_NORMAL);
}
}
dev_dbg(ccdc_cfg.dev, "\nend of ccdc_config_raw...");
return 0;
}
static int ccdc_configure(void)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
return ccdc_config_raw();
else
ccdc_config_ycbcr();
return 0;
}
static int ccdc_set_buftype(enum ccdc_buftype buf_type)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
ccdc_cfg.bayer.buf_type = buf_type;
else
ccdc_cfg.ycbcr.buf_type = buf_type;
return 0;
}
static enum ccdc_buftype ccdc_get_buftype(void)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
return ccdc_cfg.bayer.buf_type;
return ccdc_cfg.ycbcr.buf_type;
}
static int ccdc_enum_pix(u32 *pix, int i)
{
int ret = -EINVAL;
if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) {
*pix = ccdc_raw_bayer_pix_formats[i];
ret = 0;
}
} else {
if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) {
*pix = ccdc_raw_yuv_pix_formats[i];
ret = 0;
}
}
return ret;
}
static int ccdc_set_pixel_format(u32 pixfmt)
{
struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw;
if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
ccdc_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
if (pixfmt == V4L2_PIX_FMT_SBGGR8)
alaw->enable = 1;
else if (pixfmt != V4L2_PIX_FMT_SBGGR16)
return -EINVAL;
} else {
if (pixfmt == V4L2_PIX_FMT_YUYV)
ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
else if (pixfmt == V4L2_PIX_FMT_UYVY)
ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
else
return -EINVAL;
}
return 0;
}
static u32 ccdc_get_pixel_format(void)
{
struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw;
u32 pixfmt;
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
if (alaw->enable)
pixfmt = V4L2_PIX_FMT_SBGGR8;
else
pixfmt = V4L2_PIX_FMT_SBGGR16;
else {
if (ccdc_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
pixfmt = V4L2_PIX_FMT_YUYV;
else
pixfmt = V4L2_PIX_FMT_UYVY;
}
return pixfmt;
}
static int ccdc_set_image_window(struct v4l2_rect *win)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
ccdc_cfg.bayer.win = *win;
else
ccdc_cfg.ycbcr.win = *win;
return 0;
}
static void ccdc_get_image_window(struct v4l2_rect *win)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
*win = ccdc_cfg.bayer.win;
else
*win = ccdc_cfg.ycbcr.win;
}
static unsigned int ccdc_get_line_length(void)
{
struct ccdc_config_params_raw *config_params =
&ccdc_cfg.bayer.config_params;
unsigned int len;
if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
if ((config_params->alaw.enable) ||
(config_params->data_sz == CCDC_DATA_8BITS))
len = ccdc_cfg.bayer.win.width;
else
len = ccdc_cfg.bayer.win.width * 2;
} else
len = ccdc_cfg.ycbcr.win.width * 2;
return ALIGN(len, 32);
}
static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
ccdc_cfg.bayer.frm_fmt = frm_fmt;
else
ccdc_cfg.ycbcr.frm_fmt = frm_fmt;
return 0;
}
static enum ccdc_frmfmt ccdc_get_frame_format(void)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
return ccdc_cfg.bayer.frm_fmt;
else
return ccdc_cfg.ycbcr.frm_fmt;
}
static int ccdc_getfid(void)
{
return (regr(MODESET) >> 15) & 1;
}
/* misc operations */
static inline void ccdc_setfbaddr(unsigned long addr)
{
regw((addr >> 21) & 0x007f, STADRH);
regw((addr >> 5) & 0x0ffff, STADRL);
}
static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params)
{
ccdc_cfg.if_type = params->if_type;
switch (params->if_type) {
case VPFE_BT656:
case VPFE_YCBCR_SYNC_16:
case VPFE_YCBCR_SYNC_8:
ccdc_cfg.ycbcr.vd_pol = params->vdpol;
ccdc_cfg.ycbcr.hd_pol = params->hdpol;
break;
default:
/* TODO add support for raw bayer here */
return -EINVAL;
}
return 0;
}
static const struct ccdc_hw_device ccdc_hw_dev = {
.name = "DM355 CCDC",
.owner = THIS_MODULE,
.hw_ops = {
.open = ccdc_open,
.close = ccdc_close,
.enable = ccdc_enable,
.enable_out_to_sdram = ccdc_enable_output_to_sdram,
.set_hw_if_params = ccdc_set_hw_if_params,
.configure = ccdc_configure,
.set_buftype = ccdc_set_buftype,
.get_buftype = ccdc_get_buftype,
.enum_pix = ccdc_enum_pix,
.set_pixel_format = ccdc_set_pixel_format,
.get_pixel_format = ccdc_get_pixel_format,
.set_frame_format = ccdc_set_frame_format,
.get_frame_format = ccdc_get_frame_format,
.set_image_window = ccdc_set_image_window,
.get_image_window = ccdc_get_image_window,
.get_line_length = ccdc_get_line_length,
.setfbaddr = ccdc_setfbaddr,
.getfid = ccdc_getfid,
},
};
static int dm355_ccdc_probe(struct platform_device *pdev)
{
void (*setup_pinmux)(void);
struct resource *res;
int status = 0;
/*
* first try to register with vpfe. If not correct platform, then we
* don't have to iomap
*/
status = vpfe_register_ccdc_device(&ccdc_hw_dev);
if (status < 0)
return status;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
status = -ENODEV;
goto fail_nores;
}
res = request_mem_region(res->start, resource_size(res), res->name);
if (!res) {
status = -EBUSY;
goto fail_nores;
}
ccdc_cfg.base_addr = ioremap(res->start, resource_size(res));
if (!ccdc_cfg.base_addr) {
status = -ENOMEM;
goto fail_nomem;
}
/* Platform data holds setup_pinmux function ptr */
if (NULL == pdev->dev.platform_data) {
status = -ENODEV;
goto fail_nomap;
}
setup_pinmux = pdev->dev.platform_data;
/*
* setup Mux configuration for ccdc which may be different for
* different SoCs using this CCDC
*/
setup_pinmux();
ccdc_cfg.dev = &pdev->dev;
printk(KERN_NOTICE "%s is registered with vpfe.\n", ccdc_hw_dev.name);
return 0;
fail_nomap:
iounmap(ccdc_cfg.base_addr);
fail_nomem:
release_mem_region(res->start, resource_size(res));
fail_nores:
vpfe_unregister_ccdc_device(&ccdc_hw_dev);
return status;
}
static int dm355_ccdc_remove(struct platform_device *pdev)
{
struct resource *res;
iounmap(ccdc_cfg.base_addr);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(res->start, resource_size(res));
vpfe_unregister_ccdc_device(&ccdc_hw_dev);
return 0;
}
static struct platform_driver dm355_ccdc_driver = {
.driver = {
.name = "dm355_ccdc",
},
.remove = dm355_ccdc_remove,
.probe = dm355_ccdc_probe,
};
module_platform_driver(dm355_ccdc_driver);

308
drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc.h
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@ -1,308 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2005-2009 Texas Instruments Inc
*/
#ifndef _DM355_CCDC_H
#define _DM355_CCDC_H
#include <media/davinci/ccdc_types.h>
#include <media/davinci/vpfe_types.h>
/* enum for No of pixel per line to be avg. in Black Clamping */
enum ccdc_sample_length {
CCDC_SAMPLE_1PIXELS,
CCDC_SAMPLE_2PIXELS,
CCDC_SAMPLE_4PIXELS,
CCDC_SAMPLE_8PIXELS,
CCDC_SAMPLE_16PIXELS
};
/* enum for No of lines in Black Clamping */
enum ccdc_sample_line {
CCDC_SAMPLE_1LINES,
CCDC_SAMPLE_2LINES,
CCDC_SAMPLE_4LINES,
CCDC_SAMPLE_8LINES,
CCDC_SAMPLE_16LINES
};
/* enum for Alaw gamma width */
enum ccdc_gamma_width {
CCDC_GAMMA_BITS_13_4,
CCDC_GAMMA_BITS_12_3,
CCDC_GAMMA_BITS_11_2,
CCDC_GAMMA_BITS_10_1,
CCDC_GAMMA_BITS_09_0
};
enum ccdc_colpats {
CCDC_RED,
CCDC_GREEN_RED,
CCDC_GREEN_BLUE,
CCDC_BLUE
};
struct ccdc_col_pat {
enum ccdc_colpats olop;
enum ccdc_colpats olep;
enum ccdc_colpats elop;
enum ccdc_colpats elep;
};
enum ccdc_datasft {
CCDC_DATA_NO_SHIFT,
CCDC_DATA_SHIFT_1BIT,
CCDC_DATA_SHIFT_2BIT,
CCDC_DATA_SHIFT_3BIT,
CCDC_DATA_SHIFT_4BIT,
CCDC_DATA_SHIFT_5BIT,
CCDC_DATA_SHIFT_6BIT
};
enum ccdc_data_size {
CCDC_DATA_16BITS,
CCDC_DATA_15BITS,
CCDC_DATA_14BITS,
CCDC_DATA_13BITS,
CCDC_DATA_12BITS,
CCDC_DATA_11BITS,
CCDC_DATA_10BITS,
CCDC_DATA_8BITS
};
enum ccdc_mfilt1 {
CCDC_NO_MEDIAN_FILTER1,
CCDC_AVERAGE_FILTER1,
CCDC_MEDIAN_FILTER1
};
enum ccdc_mfilt2 {
CCDC_NO_MEDIAN_FILTER2,
CCDC_AVERAGE_FILTER2,
CCDC_MEDIAN_FILTER2
};
/* structure for ALaw */
struct ccdc_a_law {
/* Enable/disable A-Law */
unsigned char enable;
/* Gamma Width Input */
enum ccdc_gamma_width gamma_wd;
};
/* structure for Black Clamping */
struct ccdc_black_clamp {
/* only if bClampEnable is TRUE */
unsigned char b_clamp_enable;
/* only if bClampEnable is TRUE */
enum ccdc_sample_length sample_pixel;
/* only if bClampEnable is TRUE */
enum ccdc_sample_line sample_ln;
/* only if bClampEnable is TRUE */
unsigned short start_pixel;
/* only if bClampEnable is FALSE */
unsigned short sgain;
unsigned short dc_sub;
};
/* structure for Black Level Compensation */
struct ccdc_black_compensation {
/* Constant value to subtract from Red component */
unsigned char r;
/* Constant value to subtract from Gr component */
unsigned char gr;
/* Constant value to subtract from Blue component */
unsigned char b;
/* Constant value to subtract from Gb component */
unsigned char gb;
};
struct ccdc_float {
int integer;
unsigned int decimal;
};
#define CCDC_CSC_COEFF_TABLE_SIZE 16
/* structure for color space converter */
struct ccdc_csc {
unsigned char enable;
/*
* S8Q5. Use 2 decimal precision, user values range from -3.00 to 3.99.
* example - to use 1.03, set integer part as 1, and decimal part as 3
* to use -1.03, set integer part as -1 and decimal part as 3
*/
struct ccdc_float coeff[CCDC_CSC_COEFF_TABLE_SIZE];
};
/* Structures for Vertical Defect Correction*/
enum ccdc_vdf_csl {
CCDC_VDF_NORMAL,
CCDC_VDF_HORZ_INTERPOL_SAT,
CCDC_VDF_HORZ_INTERPOL
};
enum ccdc_vdf_cuda {
CCDC_VDF_WHOLE_LINE_CORRECT,
CCDC_VDF_UPPER_DISABLE
};
enum ccdc_dfc_mwr {
CCDC_DFC_MWR_WRITE_COMPLETE,
CCDC_DFC_WRITE_REG
};
enum ccdc_dfc_mrd {
CCDC_DFC_READ_COMPLETE,
CCDC_DFC_READ_REG
};
enum ccdc_dfc_ma_rst {
CCDC_DFC_INCR_ADDR,
CCDC_DFC_CLR_ADDR
};
enum ccdc_dfc_mclr {
CCDC_DFC_CLEAR_COMPLETE,
CCDC_DFC_CLEAR
};
struct ccdc_dft_corr_ctl {
enum ccdc_vdf_csl vdfcsl;
enum ccdc_vdf_cuda vdfcuda;
unsigned int vdflsft;
};
struct ccdc_dft_corr_mem_ctl {
enum ccdc_dfc_mwr dfcmwr;
enum ccdc_dfc_mrd dfcmrd;
enum ccdc_dfc_ma_rst dfcmarst;
enum ccdc_dfc_mclr dfcmclr;
};
#define CCDC_DFT_TABLE_SIZE 16
/*
* Main Structure for vertical defect correction. Vertical defect
* correction can correct up to 16 defects if defects less than 16
* then pad the rest with 0
*/
struct ccdc_vertical_dft {
unsigned char ver_dft_en;
unsigned char gen_dft_en;
unsigned int saturation_ctl;
struct ccdc_dft_corr_ctl dft_corr_ctl;
struct ccdc_dft_corr_mem_ctl dft_corr_mem_ctl;
int table_size;
unsigned int dft_corr_horz[CCDC_DFT_TABLE_SIZE];
unsigned int dft_corr_vert[CCDC_DFT_TABLE_SIZE];
unsigned int dft_corr_sub1[CCDC_DFT_TABLE_SIZE];
unsigned int dft_corr_sub2[CCDC_DFT_TABLE_SIZE];
unsigned int dft_corr_sub3[CCDC_DFT_TABLE_SIZE];
};
struct ccdc_data_offset {
unsigned char horz_offset;
unsigned char vert_offset;
};
/*
* Structure for CCDC configuration parameters for raw capture mode passed
* by application
*/
struct ccdc_config_params_raw {
/* data shift to be applied before storing */
enum ccdc_datasft datasft;
/* data size value from 8 to 16 bits */
enum ccdc_data_size data_sz;
/* median filter for sdram */
enum ccdc_mfilt1 mfilt1;
enum ccdc_mfilt2 mfilt2;
/* low pass filter enable/disable */
unsigned char lpf_enable;
/* Threshold of median filter */
int med_filt_thres;
/*
* horz and vertical data offset. Applicable for defect correction
* and lsc
*/
struct ccdc_data_offset data_offset;
/* Structure for Optional A-Law */
struct ccdc_a_law alaw;
/* Structure for Optical Black Clamp */
struct ccdc_black_clamp blk_clamp;
/* Structure for Black Compensation */
struct ccdc_black_compensation blk_comp;
/* structure for vertical Defect Correction Module Configuration */
struct ccdc_vertical_dft vertical_dft;
/* structure for color space converter Module Configuration */
struct ccdc_csc csc;
/* color patters for bayer capture */
struct ccdc_col_pat col_pat_field0;
struct ccdc_col_pat col_pat_field1;
};
#ifdef __KERNEL__
#include <linux/io.h>
#define CCDC_WIN_PAL {0, 0, 720, 576}
#define CCDC_WIN_VGA {0, 0, 640, 480}
struct ccdc_params_ycbcr {
/* pixel format */
enum ccdc_pixfmt pix_fmt;
/* progressive or interlaced frame */
enum ccdc_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field id polarity */
enum vpfe_pin_pol fid_pol;
/* vertical sync polarity */
enum vpfe_pin_pol vd_pol;
/* horizontal sync polarity */
enum vpfe_pin_pol hd_pol;
/* enable BT.656 embedded sync mode */
int bt656_enable;
/* cb:y:cr:y or y:cb:y:cr in memory */
enum ccdc_pixorder pix_order;
/* interleaved or separated fields */
enum ccdc_buftype buf_type;
};
/* Gain applied to Raw Bayer data */
struct ccdc_gain {
unsigned short r_ye;
unsigned short gr_cy;
unsigned short gb_g;
unsigned short b_mg;
};
/* Structure for CCDC configuration parameters for raw capture mode */
struct ccdc_params_raw {
/* pixel format */
enum ccdc_pixfmt pix_fmt;
/* progressive or interlaced frame */
enum ccdc_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field id polarity */
enum vpfe_pin_pol fid_pol;
/* vertical sync polarity */
enum vpfe_pin_pol vd_pol;
/* horizontal sync polarity */
enum vpfe_pin_pol hd_pol;
/* interleaved or separated fields */
enum ccdc_buftype buf_type;
/* Gain values */
struct ccdc_gain gain;
/* offset */
unsigned int ccdc_offset;
/* horizontal flip enable */
unsigned char horz_flip_enable;
/*
* enable to store the image in inverse order in memory
* (bottom to top)
*/
unsigned char image_invert_enable;
/* Configurable part of raw data */
struct ccdc_config_params_raw config_params;
};
#endif
#endif /* DM355_CCDC_H */

297
drivers/staging/media/deprecated/vpfe_capture/dm355_ccdc_regs.h
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@ -1,297 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2005-2009 Texas Instruments Inc
*/
#ifndef _DM355_CCDC_REGS_H
#define _DM355_CCDC_REGS_H
/**************************************************************************\
* Register OFFSET Definitions
\**************************************************************************/
#define SYNCEN 0x00
#define MODESET 0x04
#define HDWIDTH 0x08
#define VDWIDTH 0x0c
#define PPLN 0x10
#define LPFR 0x14
#define SPH 0x18
#define NPH 0x1c
#define SLV0 0x20
#define SLV1 0x24
#define NLV 0x28
#define CULH 0x2c
#define CULV 0x30
#define HSIZE 0x34
#define SDOFST 0x38
#define STADRH 0x3c
#define STADRL 0x40
#define CLAMP 0x44
#define DCSUB 0x48
#define COLPTN 0x4c
#define BLKCMP0 0x50
#define BLKCMP1 0x54
#define MEDFILT 0x58
#define RYEGAIN 0x5c
#define GRCYGAIN 0x60
#define GBGGAIN 0x64
#define BMGGAIN 0x68
#define OFFSET 0x6c
#define OUTCLIP 0x70
#define VDINT0 0x74
#define VDINT1 0x78
#define RSV0 0x7c
#define GAMMAWD 0x80
#define REC656IF 0x84
#define CCDCFG 0x88
#define FMTCFG 0x8c
#define FMTPLEN 0x90
#define FMTSPH 0x94
#define FMTLNH 0x98
#define FMTSLV 0x9c
#define FMTLNV 0xa0
#define FMTRLEN 0xa4
#define FMTHCNT 0xa8
#define FMT_ADDR_PTR_B 0xac
#define FMT_ADDR_PTR(i) (FMT_ADDR_PTR_B + (i * 4))
#define FMTPGM_VF0 0xcc
#define FMTPGM_VF1 0xd0
#define FMTPGM_AP0 0xd4
#define FMTPGM_AP1 0xd8
#define FMTPGM_AP2 0xdc
#define FMTPGM_AP3 0xe0
#define FMTPGM_AP4 0xe4
#define FMTPGM_AP5 0xe8
#define FMTPGM_AP6 0xec
#define FMTPGM_AP7 0xf0
#define LSCCFG1 0xf4
#define LSCCFG2 0xf8
#define LSCH0 0xfc
#define LSCV0 0x100
#define LSCKH 0x104
#define LSCKV 0x108
#define LSCMEMCTL 0x10c
#define LSCMEMD 0x110
#define LSCMEMQ 0x114
#define DFCCTL 0x118
#define DFCVSAT 0x11c
#define DFCMEMCTL 0x120
#define DFCMEM0 0x124
#define DFCMEM1 0x128
#define DFCMEM2 0x12c
#define DFCMEM3 0x130
#define DFCMEM4 0x134
#define CSCCTL 0x138
#define CSCM0 0x13c
#define CSCM1 0x140
#define CSCM2 0x144
#define CSCM3 0x148
#define CSCM4 0x14c
#define CSCM5 0x150
#define CSCM6 0x154
#define CSCM7 0x158
#define DATAOFST 0x15c
#define CCDC_REG_LAST DATAOFST
/**************************************************************
* Define for various register bit mask and shifts for CCDC
*
**************************************************************/
#define CCDC_RAW_IP_MODE 0
#define CCDC_VDHDOUT_INPUT 0
#define CCDC_YCINSWP_RAW (0 << 4)
#define CCDC_EXWEN_DISABLE 0
#define CCDC_DATAPOL_NORMAL 0
#define CCDC_CCDCFG_FIDMD_LATCH_VSYNC 0
#define CCDC_CCDCFG_FIDMD_NO_LATCH_VSYNC (1 << 6)
#define CCDC_CCDCFG_WENLOG_AND 0
#define CCDC_CCDCFG_TRGSEL_WEN 0
#define CCDC_CCDCFG_EXTRG_DISABLE 0
#define CCDC_CFA_MOSAIC 0
#define CCDC_Y8POS_SHIFT 11
#define CCDC_VDC_DFCVSAT_MASK 0x3fff
#define CCDC_DATAOFST_MASK 0x0ff
#define CCDC_DATAOFST_H_SHIFT 0
#define CCDC_DATAOFST_V_SHIFT 8
#define CCDC_GAMMAWD_CFA_MASK 1
#define CCDC_GAMMAWD_CFA_SHIFT 5
#define CCDC_GAMMAWD_INPUT_SHIFT 2
#define CCDC_FID_POL_MASK 1
#define CCDC_FID_POL_SHIFT 4
#define CCDC_HD_POL_MASK 1
#define CCDC_HD_POL_SHIFT 3
#define CCDC_VD_POL_MASK 1
#define CCDC_VD_POL_SHIFT 2
#define CCDC_VD_POL_NEGATIVE (1 << 2)
#define CCDC_FRM_FMT_MASK 1
#define CCDC_FRM_FMT_SHIFT 7
#define CCDC_DATA_SZ_MASK 7
#define CCDC_DATA_SZ_SHIFT 8
#define CCDC_VDHDOUT_MASK 1
#define CCDC_VDHDOUT_SHIFT 0
#define CCDC_EXWEN_MASK 1
#define CCDC_EXWEN_SHIFT 5
#define CCDC_INPUT_MODE_MASK 3
#define CCDC_INPUT_MODE_SHIFT 12
#define CCDC_PIX_FMT_MASK 3
#define CCDC_PIX_FMT_SHIFT 12
#define CCDC_DATAPOL_MASK 1
#define CCDC_DATAPOL_SHIFT 6
#define CCDC_WEN_ENABLE (1 << 1)
#define CCDC_VDHDEN_ENABLE (1 << 16)
#define CCDC_LPF_ENABLE (1 << 14)
#define CCDC_ALAW_ENABLE 1
#define CCDC_ALAW_GAMMA_WD_MASK 7
#define CCDC_REC656IF_BT656_EN 3
#define CCDC_FMTCFG_FMTMODE_MASK 3
#define CCDC_FMTCFG_FMTMODE_SHIFT 1
#define CCDC_FMTCFG_LNUM_MASK 3
#define CCDC_FMTCFG_LNUM_SHIFT 4
#define CCDC_FMTCFG_ADDRINC_MASK 7
#define CCDC_FMTCFG_ADDRINC_SHIFT 8
#define CCDC_CCDCFG_FIDMD_SHIFT 6
#define CCDC_CCDCFG_WENLOG_SHIFT 8
#define CCDC_CCDCFG_TRGSEL_SHIFT 9
#define CCDC_CCDCFG_EXTRG_SHIFT 10
#define CCDC_CCDCFG_MSBINVI_SHIFT 13
#define CCDC_HSIZE_FLIP_SHIFT 12
#define CCDC_HSIZE_FLIP_MASK 1
#define CCDC_HSIZE_VAL_MASK 0xFFF
#define CCDC_SDOFST_FIELD_INTERLEAVED 0x249
#define CCDC_SDOFST_INTERLACE_INVERSE 0x4B6D
#define CCDC_SDOFST_INTERLACE_NORMAL 0x0B6D
#define CCDC_SDOFST_PROGRESSIVE_INVERSE 0x4000
#define CCDC_SDOFST_PROGRESSIVE_NORMAL 0
#define CCDC_START_PX_HOR_MASK 0x7FFF
#define CCDC_NUM_PX_HOR_MASK 0x7FFF
#define CCDC_START_VER_ONE_MASK 0x7FFF
#define CCDC_START_VER_TWO_MASK 0x7FFF
#define CCDC_NUM_LINES_VER 0x7FFF
#define CCDC_BLK_CLAMP_ENABLE (1 << 15)
#define CCDC_BLK_SGAIN_MASK 0x1F
#define CCDC_BLK_ST_PXL_MASK 0x1FFF
#define CCDC_BLK_SAMPLE_LN_MASK 3
#define CCDC_BLK_SAMPLE_LN_SHIFT 13
#define CCDC_NUM_LINE_CALC_MASK 3
#define CCDC_NUM_LINE_CALC_SHIFT 14
#define CCDC_BLK_DC_SUB_MASK 0x3FFF
#define CCDC_BLK_COMP_MASK 0xFF
#define CCDC_BLK_COMP_GB_COMP_SHIFT 8
#define CCDC_BLK_COMP_GR_COMP_SHIFT 0
#define CCDC_BLK_COMP_R_COMP_SHIFT 8
#define CCDC_LATCH_ON_VSYNC_DISABLE (1 << 15)
#define CCDC_LATCH_ON_VSYNC_ENABLE (0 << 15)
#define CCDC_FPC_ENABLE (1 << 15)
#define CCDC_FPC_FPC_NUM_MASK 0x7FFF
#define CCDC_DATA_PACK_ENABLE (1 << 11)
#define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF
#define CCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF
#define CCDC_FMT_HORZ_FMTSPH_SHIFT 16
#define CCDC_FMT_VERT_FMTLNV_MASK 0x1FFF
#define CCDC_FMT_VERT_FMTSLV_MASK 0x1FFF
#define CCDC_FMT_VERT_FMTSLV_SHIFT 16
#define CCDC_VP_OUT_VERT_NUM_MASK 0x3FFF
#define CCDC_VP_OUT_VERT_NUM_SHIFT 17
#define CCDC_VP_OUT_HORZ_NUM_MASK 0x1FFF
#define CCDC_VP_OUT_HORZ_NUM_SHIFT 4
#define CCDC_VP_OUT_HORZ_ST_MASK 0xF
#define CCDC_CSC_COEF_INTEG_MASK 7
#define CCDC_CSC_COEF_DECIMAL_MASK 0x1f
#define CCDC_CSC_COEF_INTEG_SHIFT 5
#define CCDC_CSCM_MSB_SHIFT 8
#define CCDC_CSC_ENABLE 1
#define CCDC_CSC_DEC_MAX 32
#define CCDC_MFILT1_SHIFT 10
#define CCDC_MFILT2_SHIFT 8
#define CCDC_MED_FILT_THRESH 0x3FFF
#define CCDC_LPF_MASK 1
#define CCDC_LPF_SHIFT 14
#define CCDC_OFFSET_MASK 0x3FF
#define CCDC_DATASFT_MASK 7
#define CCDC_DATASFT_SHIFT 8
#define CCDC_DF_ENABLE 1
#define CCDC_FMTPLEN_P0_MASK 0xF
#define CCDC_FMTPLEN_P1_MASK 0xF
#define CCDC_FMTPLEN_P2_MASK 7
#define CCDC_FMTPLEN_P3_MASK 7
#define CCDC_FMTPLEN_P0_SHIFT 0
#define CCDC_FMTPLEN_P1_SHIFT 4
#define CCDC_FMTPLEN_P2_SHIFT 8
#define CCDC_FMTPLEN_P3_SHIFT 12
#define CCDC_FMTSPH_MASK 0x1FFF
#define CCDC_FMTLNH_MASK 0x1FFF
#define CCDC_FMTSLV_MASK 0x1FFF
#define CCDC_FMTLNV_MASK 0x7FFF
#define CCDC_FMTRLEN_MASK 0x1FFF
#define CCDC_FMTHCNT_MASK 0x1FFF
#define CCDC_ADP_INIT_MASK 0x1FFF
#define CCDC_ADP_LINE_SHIFT 13
#define CCDC_ADP_LINE_MASK 3
#define CCDC_FMTPGN_APTR_MASK 7
#define CCDC_DFCCTL_GDFCEN_MASK 1
#define CCDC_DFCCTL_VDFCEN_MASK 1
#define CCDC_DFCCTL_VDFC_DISABLE (0 << 4)
#define CCDC_DFCCTL_VDFCEN_SHIFT 4
#define CCDC_DFCCTL_VDFCSL_MASK 3
#define CCDC_DFCCTL_VDFCSL_SHIFT 5
#define CCDC_DFCCTL_VDFCUDA_MASK 1
#define CCDC_DFCCTL_VDFCUDA_SHIFT 7
#define CCDC_DFCCTL_VDFLSFT_MASK 3
#define CCDC_DFCCTL_VDFLSFT_SHIFT 8
#define CCDC_DFCMEMCTL_DFCMARST_MASK 1
#define CCDC_DFCMEMCTL_DFCMARST_SHIFT 2
#define CCDC_DFCMEMCTL_DFCMWR_MASK 1
#define CCDC_DFCMEMCTL_DFCMWR_SHIFT 0
#define CCDC_DFCMEMCTL_INC_ADDR (0 << 2)
#define CCDC_LSCCFG_GFTSF_MASK 7
#define CCDC_LSCCFG_GFTSF_SHIFT 1
#define CCDC_LSCCFG_GFTINV_MASK 0xf
#define CCDC_LSCCFG_GFTINV_SHIFT 4
#define CCDC_LSC_GFTABLE_SEL_MASK 3
#define CCDC_LSC_GFTABLE_EPEL_SHIFT 8
#define CCDC_LSC_GFTABLE_OPEL_SHIFT 10
#define CCDC_LSC_GFTABLE_EPOL_SHIFT 12
#define CCDC_LSC_GFTABLE_OPOL_SHIFT 14
#define CCDC_LSC_GFMODE_MASK 3
#define CCDC_LSC_GFMODE_SHIFT 4
#define CCDC_LSC_DISABLE 0
#define CCDC_LSC_ENABLE 1
#define CCDC_LSC_TABLE1_SLC 0
#define CCDC_LSC_TABLE2_SLC 1
#define CCDC_LSC_TABLE3_SLC 2
#define CCDC_LSC_MEMADDR_RESET (1 << 2)
#define CCDC_LSC_MEMADDR_INCR (0 << 2)
#define CCDC_LSC_FRAC_MASK_T1 0xFF
#define CCDC_LSC_INT_MASK 3
#define CCDC_LSC_FRAC_MASK 0x3FFF
#define CCDC_LSC_CENTRE_MASK 0x3FFF
#define CCDC_LSC_COEF_MASK 0xff
#define CCDC_LSC_COEFL_SHIFT 0
#define CCDC_LSC_COEFU_SHIFT 8
#define CCDC_GAIN_MASK 0x7FF
#define CCDC_SYNCEN_VDHDEN_MASK (1 << 0)
#define CCDC_SYNCEN_WEN_MASK (1 << 1)
#define CCDC_SYNCEN_WEN_SHIFT 1
/* Power on Defaults in hardware */
#define MODESET_DEFAULT 0x200
#define CULH_DEFAULT 0xFFFF
#define CULV_DEFAULT 0xFF
#define GAIN_DEFAULT 256
#define OUTCLIP_DEFAULT 0x3FFF
#define LSCCFG2_DEFAULT 0xE
#endif

879
drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc.c
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@ -1,879 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2006-2009 Texas Instruments Inc
*
* CCDC hardware module for DM6446
* ------------------------------
*
* This module is for configuring CCD controller of DM6446 VPFE to capture
* Raw yuv or Bayer RGB data from a decoder. CCDC has several modules
* such as Defect Pixel Correction, Color Space Conversion etc to
* pre-process the Raw Bayer RGB data, before writing it to SDRAM.
* This file is named DM644x so that other variants such DM6443
* may be supported using the same module.
*
* TODO: Test Raw bayer parameter settings and bayer capture
* Split module parameter structure to module specific ioctl structs
* investigate if enum used for user space type definition
* to be replaced by #defines or integer
*/
#include <linux/platform_device.h>
#include <linux/uaccess.h>
#include <linux/videodev2.h>
#include <linux/gfp.h>
#include <linux/err.h>
#include <linux/module.h>
#include "dm644x_ccdc.h"
#include <media/davinci/vpss.h>
#include "dm644x_ccdc_regs.h"
#include "ccdc_hw_device.h"
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("CCDC Driver for DM6446");
MODULE_AUTHOR("Texas Instruments");
static struct ccdc_oper_config {
struct device *dev;
/* CCDC interface type */
enum vpfe_hw_if_type if_type;
/* Raw Bayer configuration */
struct ccdc_params_raw bayer;
/* YCbCr configuration */
struct ccdc_params_ycbcr ycbcr;
/* ccdc base address */
void __iomem *base_addr;
} ccdc_cfg = {
/* Raw configurations */
.bayer = {
.pix_fmt = CCDC_PIXFMT_RAW,
.frm_fmt = CCDC_FRMFMT_PROGRESSIVE,
.win = CCDC_WIN_VGA,
.fid_pol = VPFE_PINPOL_POSITIVE,
.vd_pol = VPFE_PINPOL_POSITIVE,
.hd_pol = VPFE_PINPOL_POSITIVE,
.config_params = {
.data_sz = CCDC_DATA_10BITS,
},
},
.ycbcr = {
.pix_fmt = CCDC_PIXFMT_YCBCR_8BIT,
.frm_fmt = CCDC_FRMFMT_INTERLACED,
.win = CCDC_WIN_PAL,
.fid_pol = VPFE_PINPOL_POSITIVE,
.vd_pol = VPFE_PINPOL_POSITIVE,
.hd_pol = VPFE_PINPOL_POSITIVE,
.bt656_enable = 1,
.pix_order = CCDC_PIXORDER_CBYCRY,
.buf_type = CCDC_BUFTYPE_FLD_INTERLEAVED
},
};
#define CCDC_MAX_RAW_YUV_FORMATS 2
/* Raw Bayer formats */
static u32 ccdc_raw_bayer_pix_formats[] =
{V4L2_PIX_FMT_SBGGR8, V4L2_PIX_FMT_SBGGR16};
/* Raw YUV formats */
static u32 ccdc_raw_yuv_pix_formats[] =
{V4L2_PIX_FMT_UYVY, V4L2_PIX_FMT_YUYV};
/* CCDC Save/Restore context */
static u32 ccdc_ctx[CCDC_REG_END / sizeof(u32)];
/* register access routines */
static inline u32 regr(u32 offset)
{
return __raw_readl(ccdc_cfg.base_addr + offset);
}
static inline void regw(u32 val, u32 offset)
{
__raw_writel(val, ccdc_cfg.base_addr + offset);
}
static void ccdc_enable(int flag)
{
regw(flag, CCDC_PCR);
}
static void ccdc_enable_vport(int flag)
{
if (flag)
/* enable video port */
regw(CCDC_ENABLE_VIDEO_PORT, CCDC_FMTCFG);
else
regw(CCDC_DISABLE_VIDEO_PORT, CCDC_FMTCFG);
}
/*
* ccdc_setwin()
* This function will configure the window size
* to be capture in CCDC reg
*/
static void ccdc_setwin(struct v4l2_rect *image_win,
enum ccdc_frmfmt frm_fmt,
int ppc)
{
int horz_start, horz_nr_pixels;
int vert_start, vert_nr_lines;
int val = 0, mid_img = 0;
dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_setwin...");
/*
* ppc - per pixel count. indicates how many pixels per cell
* output to SDRAM. example, for ycbcr, it is one y and one c, so 2.
* raw capture this is 1
*/
horz_start = image_win->left << (ppc - 1);
horz_nr_pixels = (image_win->width << (ppc - 1)) - 1;
regw((horz_start << CCDC_HORZ_INFO_SPH_SHIFT) | horz_nr_pixels,
CCDC_HORZ_INFO);
vert_start = image_win->top;
if (frm_fmt == CCDC_FRMFMT_INTERLACED) {
vert_nr_lines = (image_win->height >> 1) - 1;
vert_start >>= 1;
/* Since first line doesn't have any data */
vert_start += 1;
/* configure VDINT0 */
val = (vert_start << CCDC_VDINT_VDINT0_SHIFT);
regw(val, CCDC_VDINT);
} else {
/* Since first line doesn't have any data */
vert_start += 1;
vert_nr_lines = image_win->height - 1;
/*
* configure VDINT0 and VDINT1. VDINT1 will be at half
* of image height
*/
mid_img = vert_start + (image_win->height / 2);
val = (vert_start << CCDC_VDINT_VDINT0_SHIFT) |
(mid_img & CCDC_VDINT_VDINT1_MASK);
regw(val, CCDC_VDINT);
}
regw((vert_start << CCDC_VERT_START_SLV0_SHIFT) | vert_start,
CCDC_VERT_START);
regw(vert_nr_lines, CCDC_VERT_LINES);
dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_setwin...");
}
static void ccdc_readregs(void)
{
unsigned int val = 0;
val = regr(CCDC_ALAW);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to ALAW...\n", val);
val = regr(CCDC_CLAMP);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to CLAMP...\n", val);
val = regr(CCDC_DCSUB);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to DCSUB...\n", val);
val = regr(CCDC_BLKCMP);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to BLKCMP...\n", val);
val = regr(CCDC_FPC_ADDR);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FPC_ADDR...\n", val);
val = regr(CCDC_FPC);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FPC...\n", val);
val = regr(CCDC_FMTCFG);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMTCFG...\n", val);
val = regr(CCDC_COLPTN);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to COLPTN...\n", val);
val = regr(CCDC_FMT_HORZ);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMT_HORZ...\n", val);
val = regr(CCDC_FMT_VERT);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to FMT_VERT...\n", val);
val = regr(CCDC_HSIZE_OFF);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to HSIZE_OFF...\n", val);
val = regr(CCDC_SDOFST);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to SDOFST...\n", val);
val = regr(CCDC_VP_OUT);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VP_OUT...\n", val);
val = regr(CCDC_SYN_MODE);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to SYN_MODE...\n", val);
val = regr(CCDC_HORZ_INFO);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to HORZ_INFO...\n", val);
val = regr(CCDC_VERT_START);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VERT_START...\n", val);
val = regr(CCDC_VERT_LINES);
dev_notice(ccdc_cfg.dev, "\nReading 0x%x to VERT_LINES...\n", val);
}
static int ccdc_close(struct device *dev)
{
return 0;
}
/*
* ccdc_restore_defaults()
* This function will write defaults to all CCDC registers
*/
static void ccdc_restore_defaults(void)
{
int i;
/* disable CCDC */
ccdc_enable(0);
/* set all registers to default value */
for (i = 4; i <= 0x94; i += 4)
regw(0, i);
regw(CCDC_NO_CULLING, CCDC_CULLING);
regw(CCDC_GAMMA_BITS_11_2, CCDC_ALAW);
}
static int ccdc_open(struct device *device)
{
ccdc_restore_defaults();
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
ccdc_enable_vport(1);
return 0;
}
static void ccdc_sbl_reset(void)
{
vpss_clear_wbl_overflow(VPSS_PCR_CCDC_WBL_O);
}
/*
* ccdc_config_ycbcr()
* This function will configure CCDC for YCbCr video capture
*/
static void ccdc_config_ycbcr(void)
{
struct ccdc_params_ycbcr *params = &ccdc_cfg.ycbcr;
u32 syn_mode;
dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_ycbcr...");
/*
* first restore the CCDC registers to default values
* This is important since we assume default values to be set in
* a lot of registers that we didn't touch
*/
ccdc_restore_defaults();
/*
* configure pixel format, frame format, configure video frame
* format, enable output to SDRAM, enable internal timing generator
* and 8bit pack mode
*/
syn_mode = (((params->pix_fmt & CCDC_SYN_MODE_INPMOD_MASK) <<
CCDC_SYN_MODE_INPMOD_SHIFT) |
((params->frm_fmt & CCDC_SYN_FLDMODE_MASK) <<
CCDC_SYN_FLDMODE_SHIFT) | CCDC_VDHDEN_ENABLE |
CCDC_WEN_ENABLE | CCDC_DATA_PACK_ENABLE);
/* setup BT.656 sync mode */
if (params->bt656_enable) {
regw(CCDC_REC656IF_BT656_EN, CCDC_REC656IF);
/*
* configure the FID, VD, HD pin polarity,
* fld,hd pol positive, vd negative, 8-bit data
*/
syn_mode |= CCDC_SYN_MODE_VD_POL_NEGATIVE;
if (ccdc_cfg.if_type == VPFE_BT656_10BIT)
syn_mode |= CCDC_SYN_MODE_10BITS;
else
syn_mode |= CCDC_SYN_MODE_8BITS;
} else {
/* y/c external sync mode */
syn_mode |= (((params->fid_pol & CCDC_FID_POL_MASK) <<
CCDC_FID_POL_SHIFT) |
((params->hd_pol & CCDC_HD_POL_MASK) <<
CCDC_HD_POL_SHIFT) |
((params->vd_pol & CCDC_VD_POL_MASK) <<
CCDC_VD_POL_SHIFT));
}
regw(syn_mode, CCDC_SYN_MODE);
/* configure video window */
ccdc_setwin(&params->win, params->frm_fmt, 2);
/*
* configure the order of y cb cr in SDRAM, and disable latch
* internal register on vsync
*/
if (ccdc_cfg.if_type == VPFE_BT656_10BIT)
regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
CCDC_LATCH_ON_VSYNC_DISABLE | CCDC_CCDCFG_BW656_10BIT,
CCDC_CCDCFG);
else
regw((params->pix_order << CCDC_CCDCFG_Y8POS_SHIFT) |
CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
/*
* configure the horizontal line offset. This should be a
* on 32 byte boundary. So clear LSB 5 bits
*/
regw(((params->win.width * 2 + 31) & ~0x1f), CCDC_HSIZE_OFF);
/* configure the memory line offset */
if (params->buf_type == CCDC_BUFTYPE_FLD_INTERLEAVED)
/* two fields are interleaved in memory */
regw(CCDC_SDOFST_FIELD_INTERLEAVED, CCDC_SDOFST);
ccdc_sbl_reset();
dev_dbg(ccdc_cfg.dev, "\nEnd of ccdc_config_ycbcr...\n");
}
static void ccdc_config_black_clamp(struct ccdc_black_clamp *bclamp)
{
u32 val;
if (!bclamp->enable) {
/* configure DCSub */
val = (bclamp->dc_sub) & CCDC_BLK_DC_SUB_MASK;
regw(val, CCDC_DCSUB);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to DCSUB...\n", val);
regw(CCDC_CLAMP_DEFAULT_VAL, CCDC_CLAMP);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x0000 to CLAMP...\n");
return;
}
/*
* Configure gain, Start pixel, No of line to be avg,
* No of pixel/line to be avg, & Enable the Black clamping
*/
val = ((bclamp->sgain & CCDC_BLK_SGAIN_MASK) |
((bclamp->start_pixel & CCDC_BLK_ST_PXL_MASK) <<
CCDC_BLK_ST_PXL_SHIFT) |
((bclamp->sample_ln & CCDC_BLK_SAMPLE_LINE_MASK) <<
CCDC_BLK_SAMPLE_LINE_SHIFT) |
((bclamp->sample_pixel & CCDC_BLK_SAMPLE_LN_MASK) <<
CCDC_BLK_SAMPLE_LN_SHIFT) | CCDC_BLK_CLAMP_ENABLE);
regw(val, CCDC_CLAMP);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to CLAMP...\n", val);
/* If Black clamping is enable then make dcsub 0 */
regw(CCDC_DCSUB_DEFAULT_VAL, CCDC_DCSUB);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x00000000 to DCSUB...\n");
}
static void ccdc_config_black_compense(struct ccdc_black_compensation *bcomp)
{
u32 val;
val = ((bcomp->b & CCDC_BLK_COMP_MASK) |
((bcomp->gb & CCDC_BLK_COMP_MASK) <<
CCDC_BLK_COMP_GB_COMP_SHIFT) |
((bcomp->gr & CCDC_BLK_COMP_MASK) <<
CCDC_BLK_COMP_GR_COMP_SHIFT) |
((bcomp->r & CCDC_BLK_COMP_MASK) <<
CCDC_BLK_COMP_R_COMP_SHIFT));
regw(val, CCDC_BLKCMP);
}
/*
* ccdc_config_raw()
* This function will configure CCDC for Raw capture mode
*/
static void ccdc_config_raw(void)
{
struct ccdc_params_raw *params = &ccdc_cfg.bayer;
struct ccdc_config_params_raw *config_params =
&ccdc_cfg.bayer.config_params;
unsigned int syn_mode = 0;
unsigned int val;
dev_dbg(ccdc_cfg.dev, "\nStarting ccdc_config_raw...");
/* Reset CCDC */
ccdc_restore_defaults();
/* Disable latching function registers on VSYNC */
regw(CCDC_LATCH_ON_VSYNC_DISABLE, CCDC_CCDCFG);
/*
* Configure the vertical sync polarity(SYN_MODE.VDPOL),
* horizontal sync polarity (SYN_MODE.HDPOL), frame id polarity
* (SYN_MODE.FLDPOL), frame format(progressive or interlace),
* data size(SYNMODE.DATSIZ), &pixel format (Input mode), output
* SDRAM, enable internal timing generator
*/
syn_mode =
(((params->vd_pol & CCDC_VD_POL_MASK) << CCDC_VD_POL_SHIFT) |
((params->hd_pol & CCDC_HD_POL_MASK) << CCDC_HD_POL_SHIFT) |
((params->fid_pol & CCDC_FID_POL_MASK) << CCDC_FID_POL_SHIFT) |
((params->frm_fmt & CCDC_FRM_FMT_MASK) << CCDC_FRM_FMT_SHIFT) |
((config_params->data_sz & CCDC_DATA_SZ_MASK) <<
CCDC_DATA_SZ_SHIFT) |
((params->pix_fmt & CCDC_PIX_FMT_MASK) << CCDC_PIX_FMT_SHIFT) |
CCDC_WEN_ENABLE | CCDC_VDHDEN_ENABLE);
/* Enable and configure aLaw register if needed */
if (config_params->alaw.enable) {
val = ((config_params->alaw.gamma_wd &
CCDC_ALAW_GAMMA_WD_MASK) | CCDC_ALAW_ENABLE);
regw(val, CCDC_ALAW);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to ALAW...\n", val);
}
/* Configure video window */
ccdc_setwin(&params->win, params->frm_fmt, CCDC_PPC_RAW);
/* Configure Black Clamp */
ccdc_config_black_clamp(&config_params->blk_clamp);
/* Configure Black level compensation */
ccdc_config_black_compense(&config_params->blk_comp);
/* If data size is 8 bit then pack the data */
if ((config_params->data_sz == CCDC_DATA_8BITS) ||
config_params->alaw.enable)
syn_mode |= CCDC_DATA_PACK_ENABLE;
/* disable video port */
val = CCDC_DISABLE_VIDEO_PORT;
if (config_params->data_sz == CCDC_DATA_8BITS)
val |= (CCDC_DATA_10BITS & CCDC_FMTCFG_VPIN_MASK)
<< CCDC_FMTCFG_VPIN_SHIFT;
else
val |= (config_params->data_sz & CCDC_FMTCFG_VPIN_MASK)
<< CCDC_FMTCFG_VPIN_SHIFT;
/* Write value in FMTCFG */
regw(val, CCDC_FMTCFG);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMTCFG...\n", val);
/* Configure the color pattern according to mt9t001 sensor */
regw(CCDC_COLPTN_VAL, CCDC_COLPTN);
dev_dbg(ccdc_cfg.dev, "\nWriting 0xBB11BB11 to COLPTN...\n");
/*
* Configure Data formatter(Video port) pixel selection
* (FMT_HORZ, FMT_VERT)
*/
val = ((params->win.left & CCDC_FMT_HORZ_FMTSPH_MASK) <<
CCDC_FMT_HORZ_FMTSPH_SHIFT) |
(params->win.width & CCDC_FMT_HORZ_FMTLNH_MASK);
regw(val, CCDC_FMT_HORZ);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMT_HORZ...\n", val);
val = (params->win.top & CCDC_FMT_VERT_FMTSLV_MASK)
<< CCDC_FMT_VERT_FMTSLV_SHIFT;
if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE)
val |= (params->win.height) & CCDC_FMT_VERT_FMTLNV_MASK;
else
val |= (params->win.height >> 1) & CCDC_FMT_VERT_FMTLNV_MASK;
dev_dbg(ccdc_cfg.dev, "\nparams->win.height 0x%x ...\n",
params->win.height);
regw(val, CCDC_FMT_VERT);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to FMT_VERT...\n", val);
dev_dbg(ccdc_cfg.dev, "\nbelow regw(val, FMT_VERT)...");
/*
* Configure Horizontal offset register. If pack 8 is enabled then
* 1 pixel will take 1 byte
*/
if ((config_params->data_sz == CCDC_DATA_8BITS) ||
config_params->alaw.enable)
regw((params->win.width + CCDC_32BYTE_ALIGN_VAL) &
CCDC_HSIZE_OFF_MASK, CCDC_HSIZE_OFF);
else
/* else one pixel will take 2 byte */
regw(((params->win.width * CCDC_TWO_BYTES_PER_PIXEL) +
CCDC_32BYTE_ALIGN_VAL) & CCDC_HSIZE_OFF_MASK,
CCDC_HSIZE_OFF);
/* Set value for SDOFST */
if (params->frm_fmt == CCDC_FRMFMT_INTERLACED) {
if (params->image_invert_enable) {
/* For intelace inverse mode */
regw(CCDC_INTERLACED_IMAGE_INVERT, CCDC_SDOFST);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x4B6D to SDOFST..\n");
}
else {
/* For intelace non inverse mode */
regw(CCDC_INTERLACED_NO_IMAGE_INVERT, CCDC_SDOFST);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x0249 to SDOFST..\n");
}
} else if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE) {
regw(CCDC_PROGRESSIVE_NO_IMAGE_INVERT, CCDC_SDOFST);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x0000 to SDOFST...\n");
}
/*
* Configure video port pixel selection (VPOUT)
* Here -1 is to make the height value less than FMT_VERT.FMTLNV
*/
if (params->frm_fmt == CCDC_FRMFMT_PROGRESSIVE)
val = (((params->win.height - 1) & CCDC_VP_OUT_VERT_NUM_MASK))
<< CCDC_VP_OUT_VERT_NUM_SHIFT;
else
val =
((((params->win.height >> CCDC_INTERLACED_HEIGHT_SHIFT) -
1) & CCDC_VP_OUT_VERT_NUM_MASK)) <<
CCDC_VP_OUT_VERT_NUM_SHIFT;
val |= ((((params->win.width))) & CCDC_VP_OUT_HORZ_NUM_MASK)
<< CCDC_VP_OUT_HORZ_NUM_SHIFT;
val |= (params->win.left) & CCDC_VP_OUT_HORZ_ST_MASK;
regw(val, CCDC_VP_OUT);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to VP_OUT...\n", val);
regw(syn_mode, CCDC_SYN_MODE);
dev_dbg(ccdc_cfg.dev, "\nWriting 0x%x to SYN_MODE...\n", syn_mode);
ccdc_sbl_reset();
dev_dbg(ccdc_cfg.dev, "\nend of ccdc_config_raw...");
ccdc_readregs();
}
static int ccdc_configure(void)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
ccdc_config_raw();
else
ccdc_config_ycbcr();
return 0;
}
static int ccdc_set_buftype(enum ccdc_buftype buf_type)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
ccdc_cfg.bayer.buf_type = buf_type;
else
ccdc_cfg.ycbcr.buf_type = buf_type;
return 0;
}
static enum ccdc_buftype ccdc_get_buftype(void)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
return ccdc_cfg.bayer.buf_type;
return ccdc_cfg.ycbcr.buf_type;
}
static int ccdc_enum_pix(u32 *pix, int i)
{
int ret = -EINVAL;
if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
if (i < ARRAY_SIZE(ccdc_raw_bayer_pix_formats)) {
*pix = ccdc_raw_bayer_pix_formats[i];
ret = 0;
}
} else {
if (i < ARRAY_SIZE(ccdc_raw_yuv_pix_formats)) {
*pix = ccdc_raw_yuv_pix_formats[i];
ret = 0;
}
}
return ret;
}
static int ccdc_set_pixel_format(u32 pixfmt)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
ccdc_cfg.bayer.pix_fmt = CCDC_PIXFMT_RAW;
if (pixfmt == V4L2_PIX_FMT_SBGGR8)
ccdc_cfg.bayer.config_params.alaw.enable = 1;
else if (pixfmt != V4L2_PIX_FMT_SBGGR16)
return -EINVAL;
} else {
if (pixfmt == V4L2_PIX_FMT_YUYV)
ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_YCBYCR;
else if (pixfmt == V4L2_PIX_FMT_UYVY)
ccdc_cfg.ycbcr.pix_order = CCDC_PIXORDER_CBYCRY;
else
return -EINVAL;
}
return 0;
}
static u32 ccdc_get_pixel_format(void)
{
struct ccdc_a_law *alaw = &ccdc_cfg.bayer.config_params.alaw;
u32 pixfmt;
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
if (alaw->enable)
pixfmt = V4L2_PIX_FMT_SBGGR8;
else
pixfmt = V4L2_PIX_FMT_SBGGR16;
else {
if (ccdc_cfg.ycbcr.pix_order == CCDC_PIXORDER_YCBYCR)
pixfmt = V4L2_PIX_FMT_YUYV;
else
pixfmt = V4L2_PIX_FMT_UYVY;
}
return pixfmt;
}
static int ccdc_set_image_window(struct v4l2_rect *win)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
ccdc_cfg.bayer.win = *win;
else
ccdc_cfg.ycbcr.win = *win;
return 0;
}
static void ccdc_get_image_window(struct v4l2_rect *win)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
*win = ccdc_cfg.bayer.win;
else
*win = ccdc_cfg.ycbcr.win;
}
static unsigned int ccdc_get_line_length(void)
{
struct ccdc_config_params_raw *config_params =
&ccdc_cfg.bayer.config_params;
unsigned int len;
if (ccdc_cfg.if_type == VPFE_RAW_BAYER) {
if ((config_params->alaw.enable) ||
(config_params->data_sz == CCDC_DATA_8BITS))
len = ccdc_cfg.bayer.win.width;
else
len = ccdc_cfg.bayer.win.width * 2;
} else
len = ccdc_cfg.ycbcr.win.width * 2;
return ALIGN(len, 32);
}
static int ccdc_set_frame_format(enum ccdc_frmfmt frm_fmt)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
ccdc_cfg.bayer.frm_fmt = frm_fmt;
else
ccdc_cfg.ycbcr.frm_fmt = frm_fmt;
return 0;
}
static enum ccdc_frmfmt ccdc_get_frame_format(void)
{
if (ccdc_cfg.if_type == VPFE_RAW_BAYER)
return ccdc_cfg.bayer.frm_fmt;
else
return ccdc_cfg.ycbcr.frm_fmt;
}
static int ccdc_getfid(void)
{
return (regr(CCDC_SYN_MODE) >> 15) & 1;
}
/* misc operations */
static inline void ccdc_setfbaddr(unsigned long addr)
{
regw(addr & 0xffffffe0, CCDC_SDR_ADDR);
}
static int ccdc_set_hw_if_params(struct vpfe_hw_if_param *params)
{
ccdc_cfg.if_type = params->if_type;
switch (params->if_type) {
case VPFE_BT656:
case VPFE_YCBCR_SYNC_16:
case VPFE_YCBCR_SYNC_8:
case VPFE_BT656_10BIT:
ccdc_cfg.ycbcr.vd_pol = params->vdpol;
ccdc_cfg.ycbcr.hd_pol = params->hdpol;
break;
default:
/* TODO add support for raw bayer here */
return -EINVAL;
}
return 0;
}
static void ccdc_save_context(void)
{
ccdc_ctx[CCDC_PCR >> 2] = regr(CCDC_PCR);
ccdc_ctx[CCDC_SYN_MODE >> 2] = regr(CCDC_SYN_MODE);
ccdc_ctx[CCDC_HD_VD_WID >> 2] = regr(CCDC_HD_VD_WID);
ccdc_ctx[CCDC_PIX_LINES >> 2] = regr(CCDC_PIX_LINES);
ccdc_ctx[CCDC_HORZ_INFO >> 2] = regr(CCDC_HORZ_INFO);
ccdc_ctx[CCDC_VERT_START >> 2] = regr(CCDC_VERT_START);
ccdc_ctx[CCDC_VERT_LINES >> 2] = regr(CCDC_VERT_LINES);
ccdc_ctx[CCDC_CULLING >> 2] = regr(CCDC_CULLING);
ccdc_ctx[CCDC_HSIZE_OFF >> 2] = regr(CCDC_HSIZE_OFF);
ccdc_ctx[CCDC_SDOFST >> 2] = regr(CCDC_SDOFST);
ccdc_ctx[CCDC_SDR_ADDR >> 2] = regr(CCDC_SDR_ADDR);
ccdc_ctx[CCDC_CLAMP >> 2] = regr(CCDC_CLAMP);
ccdc_ctx[CCDC_DCSUB >> 2] = regr(CCDC_DCSUB);
ccdc_ctx[CCDC_COLPTN >> 2] = regr(CCDC_COLPTN);
ccdc_ctx[CCDC_BLKCMP >> 2] = regr(CCDC_BLKCMP);
ccdc_ctx[CCDC_FPC >> 2] = regr(CCDC_FPC);
ccdc_ctx[CCDC_FPC_ADDR >> 2] = regr(CCDC_FPC_ADDR);
ccdc_ctx[CCDC_VDINT >> 2] = regr(CCDC_VDINT);
ccdc_ctx[CCDC_ALAW >> 2] = regr(CCDC_ALAW);
ccdc_ctx[CCDC_REC656IF >> 2] = regr(CCDC_REC656IF);
ccdc_ctx[CCDC_CCDCFG >> 2] = regr(CCDC_CCDCFG);
ccdc_ctx[CCDC_FMTCFG >> 2] = regr(CCDC_FMTCFG);
ccdc_ctx[CCDC_FMT_HORZ >> 2] = regr(CCDC_FMT_HORZ);
ccdc_ctx[CCDC_FMT_VERT >> 2] = regr(CCDC_FMT_VERT);
ccdc_ctx[CCDC_FMT_ADDR0 >> 2] = regr(CCDC_FMT_ADDR0);
ccdc_ctx[CCDC_FMT_ADDR1 >> 2] = regr(CCDC_FMT_ADDR1);
ccdc_ctx[CCDC_FMT_ADDR2 >> 2] = regr(CCDC_FMT_ADDR2);
ccdc_ctx[CCDC_FMT_ADDR3 >> 2] = regr(CCDC_FMT_ADDR3);
ccdc_ctx[CCDC_FMT_ADDR4 >> 2] = regr(CCDC_FMT_ADDR4);
ccdc_ctx[CCDC_FMT_ADDR5 >> 2] = regr(CCDC_FMT_ADDR5);
ccdc_ctx[CCDC_FMT_ADDR6 >> 2] = regr(CCDC_FMT_ADDR6);
ccdc_ctx[CCDC_FMT_ADDR7 >> 2] = regr(CCDC_FMT_ADDR7);
ccdc_ctx[CCDC_PRGEVEN_0 >> 2] = regr(CCDC_PRGEVEN_0);
ccdc_ctx[CCDC_PRGEVEN_1 >> 2] = regr(CCDC_PRGEVEN_1);
ccdc_ctx[CCDC_PRGODD_0 >> 2] = regr(CCDC_PRGODD_0);
ccdc_ctx[CCDC_PRGODD_1 >> 2] = regr(CCDC_PRGODD_1);
ccdc_ctx[CCDC_VP_OUT >> 2] = regr(CCDC_VP_OUT);
}
static void ccdc_restore_context(void)
{
regw(ccdc_ctx[CCDC_SYN_MODE >> 2], CCDC_SYN_MODE);
regw(ccdc_ctx[CCDC_HD_VD_WID >> 2], CCDC_HD_VD_WID);
regw(ccdc_ctx[CCDC_PIX_LINES >> 2], CCDC_PIX_LINES);
regw(ccdc_ctx[CCDC_HORZ_INFO >> 2], CCDC_HORZ_INFO);
regw(ccdc_ctx[CCDC_VERT_START >> 2], CCDC_VERT_START);
regw(ccdc_ctx[CCDC_VERT_LINES >> 2], CCDC_VERT_LINES);
regw(ccdc_ctx[CCDC_CULLING >> 2], CCDC_CULLING);
regw(ccdc_ctx[CCDC_HSIZE_OFF >> 2], CCDC_HSIZE_OFF);
regw(ccdc_ctx[CCDC_SDOFST >> 2], CCDC_SDOFST);
regw(ccdc_ctx[CCDC_SDR_ADDR >> 2], CCDC_SDR_ADDR);
regw(ccdc_ctx[CCDC_CLAMP >> 2], CCDC_CLAMP);
regw(ccdc_ctx[CCDC_DCSUB >> 2], CCDC_DCSUB);
regw(ccdc_ctx[CCDC_COLPTN >> 2], CCDC_COLPTN);
regw(ccdc_ctx[CCDC_BLKCMP >> 2], CCDC_BLKCMP);
regw(ccdc_ctx[CCDC_FPC >> 2], CCDC_FPC);
regw(ccdc_ctx[CCDC_FPC_ADDR >> 2], CCDC_FPC_ADDR);
regw(ccdc_ctx[CCDC_VDINT >> 2], CCDC_VDINT);
regw(ccdc_ctx[CCDC_ALAW >> 2], CCDC_ALAW);
regw(ccdc_ctx[CCDC_REC656IF >> 2], CCDC_REC656IF);
regw(ccdc_ctx[CCDC_CCDCFG >> 2], CCDC_CCDCFG);
regw(ccdc_ctx[CCDC_FMTCFG >> 2], CCDC_FMTCFG);
regw(ccdc_ctx[CCDC_FMT_HORZ >> 2], CCDC_FMT_HORZ);
regw(ccdc_ctx[CCDC_FMT_VERT >> 2], CCDC_FMT_VERT);
regw(ccdc_ctx[CCDC_FMT_ADDR0 >> 2], CCDC_FMT_ADDR0);
regw(ccdc_ctx[CCDC_FMT_ADDR1 >> 2], CCDC_FMT_ADDR1);
regw(ccdc_ctx[CCDC_FMT_ADDR2 >> 2], CCDC_FMT_ADDR2);
regw(ccdc_ctx[CCDC_FMT_ADDR3 >> 2], CCDC_FMT_ADDR3);
regw(ccdc_ctx[CCDC_FMT_ADDR4 >> 2], CCDC_FMT_ADDR4);
regw(ccdc_ctx[CCDC_FMT_ADDR5 >> 2], CCDC_FMT_ADDR5);
regw(ccdc_ctx[CCDC_FMT_ADDR6 >> 2], CCDC_FMT_ADDR6);
regw(ccdc_ctx[CCDC_FMT_ADDR7 >> 2], CCDC_FMT_ADDR7);
regw(ccdc_ctx[CCDC_PRGEVEN_0 >> 2], CCDC_PRGEVEN_0);
regw(ccdc_ctx[CCDC_PRGEVEN_1 >> 2], CCDC_PRGEVEN_1);
regw(ccdc_ctx[CCDC_PRGODD_0 >> 2], CCDC_PRGODD_0);
regw(ccdc_ctx[CCDC_PRGODD_1 >> 2], CCDC_PRGODD_1);
regw(ccdc_ctx[CCDC_VP_OUT >> 2], CCDC_VP_OUT);
regw(ccdc_ctx[CCDC_PCR >> 2], CCDC_PCR);
}
static const struct ccdc_hw_device ccdc_hw_dev = {
.name = "DM6446 CCDC",
.owner = THIS_MODULE,
.hw_ops = {
.open = ccdc_open,
.close = ccdc_close,
.reset = ccdc_sbl_reset,
.enable = ccdc_enable,
.set_hw_if_params = ccdc_set_hw_if_params,
.configure = ccdc_configure,
.set_buftype = ccdc_set_buftype,
.get_buftype = ccdc_get_buftype,
.enum_pix = ccdc_enum_pix,
.set_pixel_format = ccdc_set_pixel_format,
.get_pixel_format = ccdc_get_pixel_format,
.set_frame_format = ccdc_set_frame_format,
.get_frame_format = ccdc_get_frame_format,
.set_image_window = ccdc_set_image_window,
.get_image_window = ccdc_get_image_window,
.get_line_length = ccdc_get_line_length,
.setfbaddr = ccdc_setfbaddr,
.getfid = ccdc_getfid,
},
};
static int dm644x_ccdc_probe(struct platform_device *pdev)
{
struct resource *res;
int status = 0;
/*
* first try to register with vpfe. If not correct platform, then we
* don't have to iomap
*/
status = vpfe_register_ccdc_device(&ccdc_hw_dev);
if (status < 0)
return status;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
status = -ENODEV;
goto fail_nores;
}
res = request_mem_region(res->start, resource_size(res), res->name);
if (!res) {
status = -EBUSY;
goto fail_nores;
}
ccdc_cfg.base_addr = ioremap(res->start, resource_size(res));
if (!ccdc_cfg.base_addr) {
status = -ENOMEM;
goto fail_nomem;
}
ccdc_cfg.dev = &pdev->dev;
printk(KERN_NOTICE "%s is registered with vpfe.\n", ccdc_hw_dev.name);
return 0;
fail_nomem:
release_mem_region(res->start, resource_size(res));
fail_nores:
vpfe_unregister_ccdc_device(&ccdc_hw_dev);
return status;
}
static int dm644x_ccdc_remove(struct platform_device *pdev)
{
struct resource *res;
iounmap(ccdc_cfg.base_addr);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
release_mem_region(res->start, resource_size(res));
vpfe_unregister_ccdc_device(&ccdc_hw_dev);
return 0;
}
static int dm644x_ccdc_suspend(struct device *dev)
{
/* Save CCDC context */
ccdc_save_context();
/* Disable CCDC */
ccdc_enable(0);
return 0;
}
static int dm644x_ccdc_resume(struct device *dev)
{
/* Restore CCDC context */
ccdc_restore_context();
return 0;
}
static const struct dev_pm_ops dm644x_ccdc_pm_ops = {
.suspend = dm644x_ccdc_suspend,
.resume = dm644x_ccdc_resume,
};
static struct platform_driver dm644x_ccdc_driver = {
.driver = {
.name = "dm644x_ccdc",
.pm = &dm644x_ccdc_pm_ops,
},
.remove = dm644x_ccdc_remove,
.probe = dm644x_ccdc_probe,
};
module_platform_driver(dm644x_ccdc_driver);

171
drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2006-2009 Texas Instruments Inc
*/
#ifndef _DM644X_CCDC_H
#define _DM644X_CCDC_H
#include <media/davinci/ccdc_types.h>
#include <media/davinci/vpfe_types.h>
/* enum for No of pixel per line to be avg. in Black Clamping*/
enum ccdc_sample_length {
CCDC_SAMPLE_1PIXELS,
CCDC_SAMPLE_2PIXELS,
CCDC_SAMPLE_4PIXELS,
CCDC_SAMPLE_8PIXELS,
CCDC_SAMPLE_16PIXELS
};
/* enum for No of lines in Black Clamping */
enum ccdc_sample_line {
CCDC_SAMPLE_1LINES,
CCDC_SAMPLE_2LINES,
CCDC_SAMPLE_4LINES,
CCDC_SAMPLE_8LINES,
CCDC_SAMPLE_16LINES
};
/* enum for Alaw gamma width */
enum ccdc_gamma_width {
CCDC_GAMMA_BITS_15_6, /* use bits 15-6 for gamma */
CCDC_GAMMA_BITS_14_5,
CCDC_GAMMA_BITS_13_4,
CCDC_GAMMA_BITS_12_3,
CCDC_GAMMA_BITS_11_2,
CCDC_GAMMA_BITS_10_1,
CCDC_GAMMA_BITS_09_0 /* use bits 9-0 for gamma */
};
/* returns the highest bit used for the gamma */
static inline u8 ccdc_gamma_width_max_bit(enum ccdc_gamma_width width)
{
return 15 - width;
}
enum ccdc_data_size {
CCDC_DATA_16BITS,
CCDC_DATA_15BITS,
CCDC_DATA_14BITS,
CCDC_DATA_13BITS,
CCDC_DATA_12BITS,
CCDC_DATA_11BITS,
CCDC_DATA_10BITS,
CCDC_DATA_8BITS
};
/* returns the highest bit used for this data size */
static inline u8 ccdc_data_size_max_bit(enum ccdc_data_size sz)
{
return sz == CCDC_DATA_8BITS ? 7 : 15 - sz;
}
/* structure for ALaw */
struct ccdc_a_law {
/* Enable/disable A-Law */
unsigned char enable;
/* Gamma Width Input */
enum ccdc_gamma_width gamma_wd;
};
/* structure for Black Clamping */
struct ccdc_black_clamp {
unsigned char enable;
/* only if bClampEnable is TRUE */
enum ccdc_sample_length sample_pixel;
/* only if bClampEnable is TRUE */
enum ccdc_sample_line sample_ln;
/* only if bClampEnable is TRUE */
unsigned short start_pixel;
/* only if bClampEnable is TRUE */
unsigned short sgain;
/* only if bClampEnable is FALSE */
unsigned short dc_sub;
};
/* structure for Black Level Compensation */
struct ccdc_black_compensation {
/* Constant value to subtract from Red component */
char r;
/* Constant value to subtract from Gr component */
char gr;
/* Constant value to subtract from Blue component */
char b;
/* Constant value to subtract from Gb component */
char gb;
};
/* Structure for CCDC configuration parameters for raw capture mode passed
* by application
*/
struct ccdc_config_params_raw {
/* data size value from 8 to 16 bits */
enum ccdc_data_size data_sz;
/* Structure for Optional A-Law */
struct ccdc_a_law alaw;
/* Structure for Optical Black Clamp */
struct ccdc_black_clamp blk_clamp;
/* Structure for Black Compensation */
struct ccdc_black_compensation blk_comp;
};
#ifdef __KERNEL__
#include <linux/io.h>
/* Define to enable/disable video port */
#define FP_NUM_BYTES 4
/* Define for extra pixel/line and extra lines/frame */
#define NUM_EXTRAPIXELS 8
#define NUM_EXTRALINES 8
/* settings for commonly used video formats */
#define CCDC_WIN_PAL {0, 0, 720, 576}
/* ntsc square pixel */
#define CCDC_WIN_VGA {0, 0, (640 + NUM_EXTRAPIXELS), (480 + NUM_EXTRALINES)}
/* Structure for CCDC configuration parameters for raw capture mode */
struct ccdc_params_raw {
/* pixel format */
enum ccdc_pixfmt pix_fmt;
/* progressive or interlaced frame */
enum ccdc_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field id polarity */
enum vpfe_pin_pol fid_pol;
/* vertical sync polarity */
enum vpfe_pin_pol vd_pol;
/* horizontal sync polarity */
enum vpfe_pin_pol hd_pol;
/* interleaved or separated fields */
enum ccdc_buftype buf_type;
/*
* enable to store the image in inverse
* order in memory(bottom to top)
*/
unsigned char image_invert_enable;
/* configurable parameters */
struct ccdc_config_params_raw config_params;
};
struct ccdc_params_ycbcr {
/* pixel format */
enum ccdc_pixfmt pix_fmt;
/* progressive or interlaced frame */
enum ccdc_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field id polarity */
enum vpfe_pin_pol fid_pol;
/* vertical sync polarity */
enum vpfe_pin_pol vd_pol;
/* horizontal sync polarity */
enum vpfe_pin_pol hd_pol;
/* enable BT.656 embedded sync mode */
int bt656_enable;
/* cb:y:cr:y or y:cb:y:cr in memory */
enum ccdc_pixorder pix_order;
/* interleaved or separated fields */
enum ccdc_buftype buf_type;
};
#endif
#endif /* _DM644X_CCDC_H */

140
drivers/staging/media/deprecated/vpfe_capture/dm644x_ccdc_regs.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2006-2009 Texas Instruments Inc
*/
#ifndef _DM644X_CCDC_REGS_H
#define _DM644X_CCDC_REGS_H
/**************************************************************************\
* Register OFFSET Definitions
\**************************************************************************/
#define CCDC_PID 0x0
#define CCDC_PCR 0x4
#define CCDC_SYN_MODE 0x8
#define CCDC_HD_VD_WID 0xc
#define CCDC_PIX_LINES 0x10
#define CCDC_HORZ_INFO 0x14
#define CCDC_VERT_START 0x18
#define CCDC_VERT_LINES 0x1c
#define CCDC_CULLING 0x20
#define CCDC_HSIZE_OFF 0x24
#define CCDC_SDOFST 0x28
#define CCDC_SDR_ADDR 0x2c
#define CCDC_CLAMP 0x30
#define CCDC_DCSUB 0x34
#define CCDC_COLPTN 0x38
#define CCDC_BLKCMP 0x3c
#define CCDC_FPC 0x40
#define CCDC_FPC_ADDR 0x44
#define CCDC_VDINT 0x48
#define CCDC_ALAW 0x4c
#define CCDC_REC656IF 0x50
#define CCDC_CCDCFG 0x54
#define CCDC_FMTCFG 0x58
#define CCDC_FMT_HORZ 0x5c
#define CCDC_FMT_VERT 0x60
#define CCDC_FMT_ADDR0 0x64
#define CCDC_FMT_ADDR1 0x68
#define CCDC_FMT_ADDR2 0x6c
#define CCDC_FMT_ADDR3 0x70
#define CCDC_FMT_ADDR4 0x74
#define CCDC_FMT_ADDR5 0x78
#define CCDC_FMT_ADDR6 0x7c
#define CCDC_FMT_ADDR7 0x80
#define CCDC_PRGEVEN_0 0x84
#define CCDC_PRGEVEN_1 0x88
#define CCDC_PRGODD_0 0x8c
#define CCDC_PRGODD_1 0x90
#define CCDC_VP_OUT 0x94
#define CCDC_REG_END 0x98
/***************************************************************
* Define for various register bit mask and shifts for CCDC
****************************************************************/
#define CCDC_FID_POL_MASK 1
#define CCDC_FID_POL_SHIFT 4
#define CCDC_HD_POL_MASK 1
#define CCDC_HD_POL_SHIFT 3
#define CCDC_VD_POL_MASK 1
#define CCDC_VD_POL_SHIFT 2
#define CCDC_HSIZE_OFF_MASK 0xffffffe0
#define CCDC_32BYTE_ALIGN_VAL 31
#define CCDC_FRM_FMT_MASK 0x1
#define CCDC_FRM_FMT_SHIFT 7
#define CCDC_DATA_SZ_MASK 7
#define CCDC_DATA_SZ_SHIFT 8
#define CCDC_PIX_FMT_MASK 3
#define CCDC_PIX_FMT_SHIFT 12
#define CCDC_VP2SDR_DISABLE 0xFFFBFFFF
#define CCDC_WEN_ENABLE BIT(17)
#define CCDC_SDR2RSZ_DISABLE 0xFFF7FFFF
#define CCDC_VDHDEN_ENABLE BIT(16)
#define CCDC_LPF_ENABLE BIT(14)
#define CCDC_ALAW_ENABLE BIT(3)
#define CCDC_ALAW_GAMMA_WD_MASK 7
#define CCDC_BLK_CLAMP_ENABLE BIT(31)
#define CCDC_BLK_SGAIN_MASK 0x1F
#define CCDC_BLK_ST_PXL_MASK 0x7FFF
#define CCDC_BLK_ST_PXL_SHIFT 10
#define CCDC_BLK_SAMPLE_LN_MASK 7
#define CCDC_BLK_SAMPLE_LN_SHIFT 28
#define CCDC_BLK_SAMPLE_LINE_MASK 7
#define CCDC_BLK_SAMPLE_LINE_SHIFT 25
#define CCDC_BLK_DC_SUB_MASK 0x03FFF
#define CCDC_BLK_COMP_MASK 0xFF
#define CCDC_BLK_COMP_GB_COMP_SHIFT 8
#define CCDC_BLK_COMP_GR_COMP_SHIFT 16
#define CCDC_BLK_COMP_R_COMP_SHIFT 24
#define CCDC_LATCH_ON_VSYNC_DISABLE BIT(15)
#define CCDC_FPC_ENABLE BIT(15)
#define CCDC_FPC_DISABLE 0
#define CCDC_FPC_FPC_NUM_MASK 0x7FFF
#define CCDC_DATA_PACK_ENABLE BIT(11)
#define CCDC_FMTCFG_VPIN_MASK 7
#define CCDC_FMTCFG_VPIN_SHIFT 12
#define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF
#define CCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF
#define CCDC_FMT_HORZ_FMTSPH_SHIFT 16
#define CCDC_FMT_VERT_FMTLNV_MASK 0x1FFF
#define CCDC_FMT_VERT_FMTSLV_MASK 0x1FFF
#define CCDC_FMT_VERT_FMTSLV_SHIFT 16
#define CCDC_VP_OUT_VERT_NUM_MASK 0x3FFF
#define CCDC_VP_OUT_VERT_NUM_SHIFT 17
#define CCDC_VP_OUT_HORZ_NUM_MASK 0x1FFF
#define CCDC_VP_OUT_HORZ_NUM_SHIFT 4
#define CCDC_VP_OUT_HORZ_ST_MASK 0xF
#define CCDC_HORZ_INFO_SPH_SHIFT 16
#define CCDC_VERT_START_SLV0_SHIFT 16
#define CCDC_VDINT_VDINT0_SHIFT 16
#define CCDC_VDINT_VDINT1_MASK 0xFFFF
#define CCDC_PPC_RAW 1
#define CCDC_DCSUB_DEFAULT_VAL 0
#define CCDC_CLAMP_DEFAULT_VAL 0
#define CCDC_ENABLE_VIDEO_PORT 0x8000
#define CCDC_DISABLE_VIDEO_PORT 0
#define CCDC_COLPTN_VAL 0xBB11BB11
#define CCDC_TWO_BYTES_PER_PIXEL 2
#define CCDC_INTERLACED_IMAGE_INVERT 0x4B6D
#define CCDC_INTERLACED_NO_IMAGE_INVERT 0x0249
#define CCDC_PROGRESSIVE_IMAGE_INVERT 0x4000
#define CCDC_PROGRESSIVE_NO_IMAGE_INVERT 0
#define CCDC_INTERLACED_HEIGHT_SHIFT 1
#define CCDC_SYN_MODE_INPMOD_SHIFT 12
#define CCDC_SYN_MODE_INPMOD_MASK 3
#define CCDC_SYN_MODE_8BITS (7 << 8)
#define CCDC_SYN_MODE_10BITS (6 << 8)
#define CCDC_SYN_MODE_11BITS (5 << 8)
#define CCDC_SYN_MODE_12BITS (4 << 8)
#define CCDC_SYN_MODE_13BITS (3 << 8)
#define CCDC_SYN_MODE_14BITS (2 << 8)
#define CCDC_SYN_MODE_15BITS (1 << 8)
#define CCDC_SYN_MODE_16BITS (0 << 8)
#define CCDC_SYN_FLDMODE_MASK 1
#define CCDC_SYN_FLDMODE_SHIFT 7
#define CCDC_REC656IF_BT656_EN 3
#define CCDC_SYN_MODE_VD_POL_NEGATIVE BIT(2)
#define CCDC_CCDCFG_Y8POS_SHIFT 11
#define CCDC_CCDCFG_BW656_10BIT BIT(5)
#define CCDC_SDOFST_FIELD_INTERLEAVED 0x249
#define CCDC_NO_CULLING 0xffff00ff
#endif

1127
drivers/staging/media/deprecated/vpfe_capture/isif.c
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518
drivers/staging/media/deprecated/vpfe_capture/isif.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2008-2009 Texas Instruments Inc
*
* isif header file
*/
#ifndef _ISIF_H
#define _ISIF_H
#include <media/davinci/ccdc_types.h>
#include <media/davinci/vpfe_types.h>
/* isif float type S8Q8/U8Q8 */
struct isif_float_8 {
/* 8 bit integer part */
__u8 integer;
/* 8 bit decimal part */
__u8 decimal;
};
/* isif float type U16Q16/S16Q16 */
struct isif_float_16 {
/* 16 bit integer part */
__u16 integer;
/* 16 bit decimal part */
__u16 decimal;
};
/************************************************************************
* Vertical Defect Correction parameters
***********************************************************************/
/* Defect Correction (DFC) table entry */
struct isif_vdfc_entry {
/* vertical position of defect */
__u16 pos_vert;
/* horizontal position of defect */
__u16 pos_horz;
/*
* Defect level of Vertical line defect position. This is subtracted
* from the data at the defect position
*/
__u8 level_at_pos;
/*
* Defect level of the pixels upper than the vertical line defect.
* This is subtracted from the data
*/
__u8 level_up_pixels;
/*
* Defect level of the pixels lower than the vertical line defect.
* This is subtracted from the data
*/
__u8 level_low_pixels;
};
#define ISIF_VDFC_TABLE_SIZE 8
struct isif_dfc {
/* enable vertical defect correction */
__u8 en;
/* Defect level subtraction. Just fed through if saturating */
#define ISIF_VDFC_NORMAL 0
/*
* Defect level subtraction. Horizontal interpolation ((i-2)+(i+2))/2
* if data saturating
*/
#define ISIF_VDFC_HORZ_INTERPOL_IF_SAT 1
/* Horizontal interpolation (((i-2)+(i+2))/2) */
#define ISIF_VDFC_HORZ_INTERPOL 2
/* one of the vertical defect correction modes above */
__u8 corr_mode;
/* 0 - whole line corrected, 1 - not pixels upper than the defect */
__u8 corr_whole_line;
#define ISIF_VDFC_NO_SHIFT 0
#define ISIF_VDFC_SHIFT_1 1
#define ISIF_VDFC_SHIFT_2 2
#define ISIF_VDFC_SHIFT_3 3
#define ISIF_VDFC_SHIFT_4 4
/*
* defect level shift value. level_at_pos, level_upper_pos,
* and level_lower_pos can be shifted up by this value. Choose
* one of the values above
*/
__u8 def_level_shift;
/* defect saturation level */
__u16 def_sat_level;
/* number of vertical defects. Max is ISIF_VDFC_TABLE_SIZE */
__u16 num_vdefects;
/* VDFC table ptr */
struct isif_vdfc_entry table[ISIF_VDFC_TABLE_SIZE];
};
struct isif_horz_bclamp {
/* Horizontal clamp disabled. Only vertical clamp value is subtracted */
#define ISIF_HORZ_BC_DISABLE 0
/*
* Horizontal clamp value is calculated and subtracted from image data
* along with vertical clamp value
*/
#define ISIF_HORZ_BC_CLAMP_CALC_ENABLED 1
/*
* Horizontal clamp value calculated from previous image is subtracted
* from image data along with vertical clamp value.
*/
#define ISIF_HORZ_BC_CLAMP_NOT_UPDATED 2
/* horizontal clamp mode. One of the values above */
__u8 mode;
/*
* pixel value limit enable.
* 0 - limit disabled
* 1 - pixel value limited to 1023
*/
__u8 clamp_pix_limit;
/* Select Most left window for bc calculation */
#define ISIF_SEL_MOST_LEFT_WIN 0
/* Select Most right window for bc calculation */
#define ISIF_SEL_MOST_RIGHT_WIN 1
/* Select most left or right window for clamp val calculation */
__u8 base_win_sel_calc;
/* Window count per color for calculation. range 1-32 */
__u8 win_count_calc;
/* Window start position - horizontal for calculation. 0 - 8191 */
__u16 win_start_h_calc;
/* Window start position - vertical for calculation 0 - 8191 */
__u16 win_start_v_calc;
#define ISIF_HORZ_BC_SZ_H_2PIXELS 0
#define ISIF_HORZ_BC_SZ_H_4PIXELS 1
#define ISIF_HORZ_BC_SZ_H_8PIXELS 2
#define ISIF_HORZ_BC_SZ_H_16PIXELS 3
/* Width of the sample window in pixels for calculation */
__u8 win_h_sz_calc;
#define ISIF_HORZ_BC_SZ_V_32PIXELS 0
#define ISIF_HORZ_BC_SZ_V_64PIXELS 1
#define ISIF_HORZ_BC_SZ_V_128PIXELS 2
#define ISIF_HORZ_BC_SZ_V_256PIXELS 3
/* Height of the sample window in pixels for calculation */
__u8 win_v_sz_calc;
};
/************************************************************************
* Black Clamp parameters
***********************************************************************/
struct isif_vert_bclamp {
/* Reset value used is the clamp value calculated */
#define ISIF_VERT_BC_USE_HORZ_CLAMP_VAL 0
/* Reset value used is reset_clamp_val configured */
#define ISIF_VERT_BC_USE_CONFIG_CLAMP_VAL 1
/* No update, previous image value is used */
#define ISIF_VERT_BC_NO_UPDATE 2
/*
* Reset value selector for vertical clamp calculation. Use one of
* the above values
*/
__u8 reset_val_sel;
/* U8Q8. Line average coefficient used in vertical clamp calculation */
__u8 line_ave_coef;
/* Height of the optical black region for calculation */
__u16 ob_v_sz_calc;
/* Optical black region start position - horizontal. 0 - 8191 */
__u16 ob_start_h;
/* Optical black region start position - vertical 0 - 8191 */
__u16 ob_start_v;
};
struct isif_black_clamp {
/*
* This offset value is added irrespective of the clamp enable status.
* S13
*/
__u16 dc_offset;
/*
* Enable black/digital clamp value to be subtracted from the image data
*/
__u8 en;
/*
* black clamp mode. same/separate clamp for 4 colors
* 0 - disable - same clamp value for all colors
* 1 - clamp value calculated separately for all colors
*/
__u8 bc_mode_color;
/* Vertical start position for bc subtraction */
__u16 vert_start_sub;
/* Black clamp for horizontal direction */
struct isif_horz_bclamp horz;
/* Black clamp for vertical direction */
struct isif_vert_bclamp vert;
};
/*************************************************************************
** Color Space Conversion (CSC)
*************************************************************************/
#define ISIF_CSC_NUM_COEFF 16
struct isif_color_space_conv {
/* Enable color space conversion */
__u8 en;
/*
* csc coefficient table. S8Q5, M00 at index 0, M01 at index 1, and
* so forth
*/
struct isif_float_8 coeff[ISIF_CSC_NUM_COEFF];
};
/*************************************************************************
** Black Compensation parameters
*************************************************************************/
struct isif_black_comp {
/* Comp for Red */
__s8 r_comp;
/* Comp for Gr */
__s8 gr_comp;
/* Comp for Blue */
__s8 b_comp;
/* Comp for Gb */
__s8 gb_comp;
};
/*************************************************************************
** Gain parameters
*************************************************************************/
struct isif_gain {
/* Gain for Red or ye */
struct isif_float_16 r_ye;
/* Gain for Gr or cy */
struct isif_float_16 gr_cy;
/* Gain for Gb or g */
struct isif_float_16 gb_g;
/* Gain for Blue or mg */
struct isif_float_16 b_mg;
};
#define ISIF_LINEAR_TAB_SIZE 192
/*************************************************************************
** Linearization parameters
*************************************************************************/
struct isif_linearize {
/* Enable or Disable linearization of data */
__u8 en;
/* Shift value applied */
__u8 corr_shft;
/* scale factor applied U11Q10 */
struct isif_float_16 scale_fact;
/* Size of the linear table */
__u16 table[ISIF_LINEAR_TAB_SIZE];
};
/* Color patterns */
#define ISIF_RED 0
#define ISIF_GREEN_RED 1
#define ISIF_GREEN_BLUE 2
#define ISIF_BLUE 3
struct isif_col_pat {
__u8 olop;
__u8 olep;
__u8 elop;
__u8 elep;
};
/*************************************************************************
** Data formatter parameters
*************************************************************************/
struct isif_fmtplen {
/*
* number of program entries for SET0, range 1 - 16
* when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is
* ISIF_COMBINE
*/
__u16 plen0;
/*
* number of program entries for SET1, range 1 - 16
* when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is
* ISIF_COMBINE
*/
__u16 plen1;
/**
* number of program entries for SET2, range 1 - 16
* when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is
* ISIF_COMBINE
*/
__u16 plen2;
/**
* number of program entries for SET3, range 1 - 16
* when fmtmode is ISIF_SPLIT, 1 - 8 when fmtmode is
* ISIF_COMBINE
*/
__u16 plen3;
};
struct isif_fmt_cfg {
#define ISIF_SPLIT 0
#define ISIF_COMBINE 1
/* Split or combine or line alternate */
__u8 fmtmode;
/* enable or disable line alternating mode */
__u8 ln_alter_en;
#define ISIF_1LINE 0
#define ISIF_2LINES 1
#define ISIF_3LINES 2
#define ISIF_4LINES 3
/* Split/combine line number */
__u8 lnum;
/* Address increment Range 1 - 16 */
__u8 addrinc;
};
struct isif_fmt_addr_ptr {
/* Initial address */
__u32 init_addr;
/* output line number */
#define ISIF_1STLINE 0
#define ISIF_2NDLINE 1
#define ISIF_3RDLINE 2
#define ISIF_4THLINE 3
__u8 out_line;
};
struct isif_fmtpgm_ap {
/* program address pointer */
__u8 pgm_aptr;
/* program address increment or decrement */
__u8 pgmupdt;
};
struct isif_data_formatter {
/* Enable/Disable data formatter */
__u8 en;
/* data formatter configuration */
struct isif_fmt_cfg cfg;
/* Formatter program entries length */
struct isif_fmtplen plen;
/* first pixel in a line fed to formatter */
__u16 fmtrlen;
/* HD interval for output line. Only valid when split line */
__u16 fmthcnt;
/* formatter address pointers */
struct isif_fmt_addr_ptr fmtaddr_ptr[16];
/* program enable/disable */
__u8 pgm_en[32];
/* program address pointers */
struct isif_fmtpgm_ap fmtpgm_ap[32];
};
struct isif_df_csc {
/* Color Space Conversion configuration, 0 - csc, 1 - df */
__u8 df_or_csc;
/* csc configuration valid if df_or_csc is 0 */
struct isif_color_space_conv csc;
/* data formatter configuration valid if df_or_csc is 1 */
struct isif_data_formatter df;
/* start pixel in a line at the input */
__u32 start_pix;
/* number of pixels in input line */
__u32 num_pixels;
/* start line at the input */
__u32 start_line;
/* number of lines at the input */
__u32 num_lines;
};
struct isif_gain_offsets_adj {
/* Gain adjustment per color */
struct isif_gain gain;
/* Offset adjustment */
__u16 offset;
/* Enable or Disable Gain adjustment for SDRAM data */
__u8 gain_sdram_en;
/* Enable or Disable Gain adjustment for IPIPE data */
__u8 gain_ipipe_en;
/* Enable or Disable Gain adjustment for H3A data */
__u8 gain_h3a_en;
/* Enable or Disable Gain adjustment for SDRAM data */
__u8 offset_sdram_en;
/* Enable or Disable Gain adjustment for IPIPE data */
__u8 offset_ipipe_en;
/* Enable or Disable Gain adjustment for H3A data */
__u8 offset_h3a_en;
};
struct isif_cul {
/* Horizontal Cull pattern for odd lines */
__u8 hcpat_odd;
/* Horizontal Cull pattern for even lines */
__u8 hcpat_even;
/* Vertical Cull pattern */
__u8 vcpat;
/* Enable or disable lpf. Apply when cull is enabled */
__u8 en_lpf;
};
struct isif_compress {
#define ISIF_ALAW 0
#define ISIF_DPCM 1
#define ISIF_NO_COMPRESSION 2
/* Compression Algorithm used */
__u8 alg;
/* Choose Predictor1 for DPCM compression */
#define ISIF_DPCM_PRED1 0
/* Choose Predictor2 for DPCM compression */
#define ISIF_DPCM_PRED2 1
/* Predictor for DPCM compression */
__u8 pred;
};
/* all the stuff in this struct will be provided by userland */
struct isif_config_params_raw {
/* Linearization parameters for image sensor data input */
struct isif_linearize linearize;
/* Data formatter or CSC */
struct isif_df_csc df_csc;
/* Defect Pixel Correction (DFC) configuration */
struct isif_dfc dfc;
/* Black/Digital Clamp configuration */
struct isif_black_clamp bclamp;
/* Gain, offset adjustments */
struct isif_gain_offsets_adj gain_offset;
/* Culling */
struct isif_cul culling;
/* A-Law and DPCM compression options */
struct isif_compress compress;
/* horizontal offset for Gain/LSC/DFC */
__u16 horz_offset;
/* vertical offset for Gain/LSC/DFC */
__u16 vert_offset;
/* color pattern for field 0 */
struct isif_col_pat col_pat_field0;
/* color pattern for field 1 */
struct isif_col_pat col_pat_field1;
#define ISIF_NO_SHIFT 0
#define ISIF_1BIT_SHIFT 1
#define ISIF_2BIT_SHIFT 2
#define ISIF_3BIT_SHIFT 3
#define ISIF_4BIT_SHIFT 4
#define ISIF_5BIT_SHIFT 5
#define ISIF_6BIT_SHIFT 6
/* Data shift applied before storing to SDRAM */
__u8 data_shift;
/* enable input test pattern generation */
__u8 test_pat_gen;
};
#ifdef __KERNEL__
struct isif_ycbcr_config {
/* isif pixel format */
enum ccdc_pixfmt pix_fmt;
/* isif frame format */
enum ccdc_frmfmt frm_fmt;
/* ISIF crop window */
struct v4l2_rect win;
/* field polarity */
enum vpfe_pin_pol fid_pol;
/* interface VD polarity */
enum vpfe_pin_pol vd_pol;
/* interface HD polarity */
enum vpfe_pin_pol hd_pol;
/* isif pix order. Only used for ycbcr capture */
enum ccdc_pixorder pix_order;
/* isif buffer type. Only used for ycbcr capture */
enum ccdc_buftype buf_type;
};
/* MSB of image data connected to sensor port */
enum isif_data_msb {
ISIF_BIT_MSB_15,
ISIF_BIT_MSB_14,
ISIF_BIT_MSB_13,
ISIF_BIT_MSB_12,
ISIF_BIT_MSB_11,
ISIF_BIT_MSB_10,
ISIF_BIT_MSB_9,
ISIF_BIT_MSB_8,
ISIF_BIT_MSB_7
};
enum isif_cfa_pattern {
ISIF_CFA_PAT_MOSAIC,
ISIF_CFA_PAT_STRIPE
};
struct isif_params_raw {
/* isif pixel format */
enum ccdc_pixfmt pix_fmt;
/* isif frame format */
enum ccdc_frmfmt frm_fmt;
/* video window */
struct v4l2_rect win;
/* field polarity */
enum vpfe_pin_pol fid_pol;
/* interface VD polarity */
enum vpfe_pin_pol vd_pol;
/* interface HD polarity */
enum vpfe_pin_pol hd_pol;
/* buffer type. Applicable for interlaced mode */
enum ccdc_buftype buf_type;
/* Gain values */
struct isif_gain gain;
/* cfa pattern */
enum isif_cfa_pattern cfa_pat;
/* Data MSB position */
enum isif_data_msb data_msb;
/* Enable horizontal flip */
unsigned char horz_flip_en;
/* Enable image invert vertically */
unsigned char image_invert_en;
/* all the userland defined stuff*/
struct isif_config_params_raw config_params;
};
enum isif_data_pack {
ISIF_PACK_16BIT,
ISIF_PACK_12BIT,
ISIF_PACK_8BIT
};
#define ISIF_WIN_NTSC {0, 0, 720, 480}
#define ISIF_WIN_VGA {0, 0, 640, 480}
#endif
#endif

256
drivers/staging/media/deprecated/vpfe_capture/isif_regs.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2008-2009 Texas Instruments Inc
*/
#ifndef _ISIF_REGS_H
#define _ISIF_REGS_H
/* ISIF registers relative offsets */
#define SYNCEN 0x00
#define MODESET 0x04
#define HDW 0x08
#define VDW 0x0c
#define PPLN 0x10
#define LPFR 0x14
#define SPH 0x18
#define LNH 0x1c
#define SLV0 0x20
#define SLV1 0x24
#define LNV 0x28
#define CULH 0x2c
#define CULV 0x30
#define HSIZE 0x34
#define SDOFST 0x38
#define CADU 0x3c
#define CADL 0x40
#define LINCFG0 0x44
#define LINCFG1 0x48
#define CCOLP 0x4c
#define CRGAIN 0x50
#define CGRGAIN 0x54
#define CGBGAIN 0x58
#define CBGAIN 0x5c
#define COFSTA 0x60
#define FLSHCFG0 0x64
#define FLSHCFG1 0x68
#define FLSHCFG2 0x6c
#define VDINT0 0x70
#define VDINT1 0x74
#define VDINT2 0x78
#define MISC 0x7c
#define CGAMMAWD 0x80
#define REC656IF 0x84
#define CCDCFG 0x88
/*****************************************************
* Defect Correction registers
*****************************************************/
#define DFCCTL 0x8c
#define VDFSATLV 0x90
#define DFCMEMCTL 0x94
#define DFCMEM0 0x98
#define DFCMEM1 0x9c
#define DFCMEM2 0xa0
#define DFCMEM3 0xa4
#define DFCMEM4 0xa8
/****************************************************
* Black Clamp registers
****************************************************/
#define CLAMPCFG 0xac
#define CLDCOFST 0xb0
#define CLSV 0xb4
#define CLHWIN0 0xb8
#define CLHWIN1 0xbc
#define CLHWIN2 0xc0
#define CLVRV 0xc4
#define CLVWIN0 0xc8
#define CLVWIN1 0xcc
#define CLVWIN2 0xd0
#define CLVWIN3 0xd4
/****************************************************
* Lense Shading Correction
****************************************************/
#define DATAHOFST 0xd8
#define DATAVOFST 0xdc
#define LSCHVAL 0xe0
#define LSCVVAL 0xe4
#define TWODLSCCFG 0xe8
#define TWODLSCOFST 0xec
#define TWODLSCINI 0xf0
#define TWODLSCGRBU 0xf4
#define TWODLSCGRBL 0xf8
#define TWODLSCGROF 0xfc
#define TWODLSCORBU 0x100
#define TWODLSCORBL 0x104
#define TWODLSCOROF 0x108
#define TWODLSCIRQEN 0x10c
#define TWODLSCIRQST 0x110
/****************************************************
* Data formatter
****************************************************/
#define FMTCFG 0x114
#define FMTPLEN 0x118
#define FMTSPH 0x11c
#define FMTLNH 0x120
#define FMTSLV 0x124
#define FMTLNV 0x128
#define FMTRLEN 0x12c
#define FMTHCNT 0x130
#define FMTAPTR_BASE 0x134
/* Below macro for addresses FMTAPTR0 - FMTAPTR15 */
#define FMTAPTR(i) (FMTAPTR_BASE + (i * 4))
#define FMTPGMVF0 0x174
#define FMTPGMVF1 0x178
#define FMTPGMAPU0 0x17c
#define FMTPGMAPU1 0x180
#define FMTPGMAPS0 0x184
#define FMTPGMAPS1 0x188
#define FMTPGMAPS2 0x18c
#define FMTPGMAPS3 0x190
#define FMTPGMAPS4 0x194
#define FMTPGMAPS5 0x198
#define FMTPGMAPS6 0x19c
#define FMTPGMAPS7 0x1a0
/************************************************
* Color Space Converter
************************************************/
#define CSCCTL 0x1a4
#define CSCM0 0x1a8
#define CSCM1 0x1ac
#define CSCM2 0x1b0
#define CSCM3 0x1b4
#define CSCM4 0x1b8
#define CSCM5 0x1bc
#define CSCM6 0x1c0
#define CSCM7 0x1c4
#define OBWIN0 0x1c8
#define OBWIN1 0x1cc
#define OBWIN2 0x1d0
#define OBWIN3 0x1d4
#define OBVAL0 0x1d8
#define OBVAL1 0x1dc
#define OBVAL2 0x1e0
#define OBVAL3 0x1e4
#define OBVAL4 0x1e8
#define OBVAL5 0x1ec
#define OBVAL6 0x1f0
#define OBVAL7 0x1f4
#define CLKCTL 0x1f8
/* Masks & Shifts below */
#define START_PX_HOR_MASK 0x7FFF
#define NUM_PX_HOR_MASK 0x7FFF
#define START_VER_ONE_MASK 0x7FFF
#define START_VER_TWO_MASK 0x7FFF
#define NUM_LINES_VER 0x7FFF
/* gain - offset masks */
#define GAIN_INTEGER_SHIFT 9
#define OFFSET_MASK 0xFFF
#define GAIN_SDRAM_EN_SHIFT 12
#define GAIN_IPIPE_EN_SHIFT 13
#define GAIN_H3A_EN_SHIFT 14
#define OFST_SDRAM_EN_SHIFT 8
#define OFST_IPIPE_EN_SHIFT 9
#define OFST_H3A_EN_SHIFT 10
#define GAIN_OFFSET_EN_MASK 0x7700
/* Culling */
#define CULL_PAT_EVEN_LINE_SHIFT 8
/* CCDCFG register */
#define ISIF_YCINSWP_RAW (0x00 << 4)
#define ISIF_YCINSWP_YCBCR (0x01 << 4)
#define ISIF_CCDCFG_FIDMD_LATCH_VSYNC (0x00 << 6)
#define ISIF_CCDCFG_WENLOG_AND (0x00 << 8)
#define ISIF_CCDCFG_TRGSEL_WEN (0x00 << 9)
#define ISIF_CCDCFG_EXTRG_DISABLE (0x00 << 10)
#define ISIF_LATCH_ON_VSYNC_DISABLE (0x01 << 15)
#define ISIF_LATCH_ON_VSYNC_ENABLE (0x00 << 15)
#define ISIF_DATA_PACK_MASK 3
#define ISIF_DATA_PACK16 0
#define ISIF_DATA_PACK12 1
#define ISIF_DATA_PACK8 2
#define ISIF_PIX_ORDER_SHIFT 11
#define ISIF_BW656_ENABLE (0x01 << 5)
/* MODESET registers */
#define ISIF_VDHDOUT_INPUT (0x00 << 0)
#define ISIF_INPUT_SHIFT 12
#define ISIF_RAW_INPUT_MODE 0
#define ISIF_FID_POL_SHIFT 4
#define ISIF_HD_POL_SHIFT 3
#define ISIF_VD_POL_SHIFT 2
#define ISIF_DATAPOL_NORMAL 0
#define ISIF_DATAPOL_SHIFT 6
#define ISIF_EXWEN_DISABLE 0
#define ISIF_EXWEN_SHIFT 5
#define ISIF_FRM_FMT_SHIFT 7
#define ISIF_DATASFT_SHIFT 8
#define ISIF_LPF_SHIFT 14
#define ISIF_LPF_MASK 1
/* GAMMAWD registers */
#define ISIF_ALAW_GAMMA_WD_MASK 0xF
#define ISIF_ALAW_GAMMA_WD_SHIFT 1
#define ISIF_ALAW_ENABLE 1
#define ISIF_GAMMAWD_CFA_SHIFT 5
/* HSIZE registers */
#define ISIF_HSIZE_FLIP_MASK 1
#define ISIF_HSIZE_FLIP_SHIFT 12
/* MISC registers */
#define ISIF_DPCM_EN_SHIFT 12
#define ISIF_DPCM_PREDICTOR_SHIFT 13
/* Black clamp related */
#define ISIF_BC_MODE_COLOR_SHIFT 4
#define ISIF_HORZ_BC_MODE_SHIFT 1
#define ISIF_HORZ_BC_WIN_SEL_SHIFT 5
#define ISIF_HORZ_BC_PIX_LIMIT_SHIFT 6
#define ISIF_HORZ_BC_WIN_H_SIZE_SHIFT 8
#define ISIF_HORZ_BC_WIN_V_SIZE_SHIFT 12
#define ISIF_VERT_BC_RST_VAL_SEL_SHIFT 4
#define ISIF_VERT_BC_LINE_AVE_COEF_SHIFT 8
/* VDFC registers */
#define ISIF_VDFC_EN_SHIFT 4
#define ISIF_VDFC_CORR_MOD_SHIFT 5
#define ISIF_VDFC_CORR_WHOLE_LN_SHIFT 7
#define ISIF_VDFC_LEVEL_SHFT_SHIFT 8
#define ISIF_VDFC_POS_MASK 0x1FFF
#define ISIF_DFCMEMCTL_DFCMARST_SHIFT 2
/* CSC registers */
#define ISIF_CSC_COEF_INTEG_MASK 7
#define ISIF_CSC_COEF_DECIMAL_MASK 0x1f
#define ISIF_CSC_COEF_INTEG_SHIFT 5
#define ISIF_CSCM_MSB_SHIFT 8
#define ISIF_DF_CSC_SPH_MASK 0x1FFF
#define ISIF_DF_CSC_LNH_MASK 0x1FFF
#define ISIF_DF_CSC_SLV_MASK 0x1FFF
#define ISIF_DF_CSC_LNV_MASK 0x1FFF
#define ISIF_DF_NUMLINES 0x7FFF
#define ISIF_DF_NUMPIX 0x1FFF
/* Offsets for LSC/DFC/Gain */
#define ISIF_DATA_H_OFFSET_MASK 0x1FFF
#define ISIF_DATA_V_OFFSET_MASK 0x1FFF
/* Linearization */
#define ISIF_LIN_CORRSFT_SHIFT 4
#define ISIF_LIN_SCALE_FACT_INTEG_SHIFT 10
/* Pattern registers */
#define ISIF_PG_EN (1 << 3)
#define ISIF_SEL_PG_SRC (3 << 4)
#define ISIF_PG_VD_POL_SHIFT 0
#define ISIF_PG_HD_POL_SHIFT 1
/*random other junk*/
#define ISIF_SYNCEN_VDHDEN_MASK (1 << 0)
#define ISIF_SYNCEN_WEN_MASK (1 << 1)
#define ISIF_SYNCEN_WEN_SHIFT 1
#endif

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drivers/staging/media/deprecated/vpfe_capture/vpfe_capture.c
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30
include/media/davinci/ccdc_types.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2008-2009 Texas Instruments Inc
*
**************************************************************************/
#ifndef _CCDC_TYPES_H
#define _CCDC_TYPES_H
enum ccdc_pixfmt {
CCDC_PIXFMT_RAW,
CCDC_PIXFMT_YCBCR_16BIT,
CCDC_PIXFMT_YCBCR_8BIT
};
enum ccdc_frmfmt {
CCDC_FRMFMT_PROGRESSIVE,
CCDC_FRMFMT_INTERLACED
};
/* PIXEL ORDER IN MEMORY from LSB to MSB */
/* only applicable for 8-bit input mode */
enum ccdc_pixorder {
CCDC_PIXORDER_YCBYCR,
CCDC_PIXORDER_CBYCRY,
};
enum ccdc_buftype {
CCDC_BUFTYPE_FLD_INTERLEAVED,
CCDC_BUFTYPE_FLD_SEPARATED
};
#endif