Merge branch 'clk-qcom' into clk-next
- Enable CPU clks on Qualcomm MSM8996 SoCs * clk-qcom: clk: qcom: Add CPU clock driver for msm8996 dt-bindings: clk: qcom: Add bindings for CPU clock for msm8996 soc: qcom: Separate kryo l2 accessors from PMU driver clk: qcom: Fix return value check in apss_ipq6018_probe()
This commit is contained in:
Stephen Boyd
Коммит
d39fc26556
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@ -0,0 +1,56 @@
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,kryocc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm clock controller for MSM8996 CPUs
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maintainers:
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- Loic Poulain <loic.poulain@linaro.org>
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description: |
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Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster
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and clock 1 is for Perf cluster.
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properties:
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compatible:
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enum:
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- qcom,msm8996-apcc
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clocks:
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items:
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- description: Primary PLL clock for power cluster (little)
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- description: Primary PLL clock for perf cluster (big)
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- description: Alternate PLL clock for power cluster (little)
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- description: Alternate PLL clock for perf cluster (big)
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clock-names:
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items:
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- const: pwrcl_pll
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- const: perfcl_pll
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- const: pwrcl_alt_pll
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- const: perfcl_alt_pll
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required:
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- compatible
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- reg
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- '#clock-cells'
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additionalProperties: false
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examples:
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# Example for msm8996
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- |
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kryocc: clock-controller@6400000 {
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compatible = "qcom,msm8996-apcc";
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reg = <0x6400000 0x90000>;
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#clock-cells = <1>;
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};
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...
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@ -37,6 +37,15 @@ config QCOM_CLK_APCS_MSM8916
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Say Y if you want to support CPU frequency scaling on devices
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such as msm8916.
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config QCOM_CLK_APCC_MSM8996
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tristate "MSM8996 CPU Clock Controller"
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select QCOM_KRYO_L2_ACCESSORS
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depends on ARM64
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help
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Support for the CPU clock controller on msm8996 devices.
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Say Y if you want to support CPU clock scaling using CPUfreq
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drivers for dyanmic power management.
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config QCOM_CLK_RPM
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tristate "RPM based Clock Controller"
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depends on MFD_QCOM_RPM
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@ -44,6 +44,7 @@ obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
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obj-$(CONFIG_MSM_MMCC_8998) += mmcc-msm8998.o
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obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
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obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
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obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += clk-cpu-8996.o
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obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
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obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
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obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
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@ -87,8 +87,8 @@ static int apss_ipq6018_probe(struct platform_device *pdev)
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struct regmap *regmap;
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regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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if (!regmap)
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return -ENODEV;
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return qcom_cc_really_probe(pdev, &apss_ipq6018_desc, regmap);
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}
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@ -47,6 +47,12 @@ struct pll_vco {
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u32 val;
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};
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#define VCO(a, b, c) { \
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.val = a,\
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.min_freq = b,\
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.max_freq = c,\
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}
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/**
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* struct clk_alpha_pll - phase locked loop (PLL)
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* @offset: base address of registers
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@ -0,0 +1,538 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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/*
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* Each of the CPU clusters (Power and Perf) on msm8996 are
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* clocked via 2 PLLs, a primary and alternate. There are also
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* 2 Mux'es, a primary and secondary all connected together
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* as shown below
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*
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* +-------+
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* XO | |
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* +------------------>0 |
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* | |
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* PLL/2 | SMUX +----+
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* +------->1 | |
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* | | | |
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* | +-------+ | +-------+
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* | +---->0 |
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* | | |
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* +---------------+ | +----------->1 | CPU clk
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* |Primary PLL +----+ PLL_EARLY | | +------>
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* | +------+-----------+ +------>2 PMUX |
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* +---------------+ | | | |
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* | +------+ | +-->3 |
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* +--^+ ACD +-----+ | +-------+
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* +---------------+ +------+ |
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* |Alt PLL | |
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* | +---------------------------+
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* +---------------+ PLL_EARLY
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*
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* The primary PLL is what drives the CPU clk, except for times
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* when we are reprogramming the PLL itself (for rate changes) when
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* we temporarily switch to an alternate PLL.
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*
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* The primary PLL operates on a single VCO range, between 600MHz
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* and 3GHz. However the CPUs do support OPPs with frequencies
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* between 300MHz and 600MHz. In order to support running the CPUs
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* at those frequencies we end up having to lock the PLL at twice
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* the rate and drive the CPU clk via the PLL/2 output and SMUX.
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*
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* So for frequencies above 600MHz we follow the following path
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* Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
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* and for frequencies between 300MHz and 600MHz we follow
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* Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
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*
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* ACD stands for Adaptive Clock Distribution and is used to
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* detect voltage droops.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <soc/qcom/kryo-l2-accessors.h>
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#include "clk-alpha-pll.h"
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#include "clk-regmap.h"
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enum _pmux_input {
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DIV_2_INDEX = 0,
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PLL_INDEX,
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ACD_INDEX,
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ALT_INDEX,
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NUM_OF_PMUX_INPUTS
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};
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#define DIV_2_THRESHOLD 600000000
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#define PWRCL_REG_OFFSET 0x0
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#define PERFCL_REG_OFFSET 0x80000
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#define MUX_OFFSET 0x40
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#define ALT_PLL_OFFSET 0x100
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#define SSSCTL_OFFSET 0x160
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static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_ALPHA_VAL] = 0x08,
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[PLL_OFF_USER_CTL] = 0x10,
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[PLL_OFF_CONFIG_CTL] = 0x18,
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[PLL_OFF_CONFIG_CTL_U] = 0x1c,
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[PLL_OFF_TEST_CTL] = 0x20,
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[PLL_OFF_TEST_CTL_U] = 0x24,
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[PLL_OFF_STATUS] = 0x28,
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};
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static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_ALPHA_VAL] = 0x08,
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[PLL_OFF_ALPHA_VAL_U] = 0x0c,
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[PLL_OFF_USER_CTL] = 0x10,
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[PLL_OFF_USER_CTL_U] = 0x14,
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[PLL_OFF_CONFIG_CTL] = 0x18,
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[PLL_OFF_TEST_CTL] = 0x20,
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[PLL_OFF_TEST_CTL_U] = 0x24,
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[PLL_OFF_STATUS] = 0x28,
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};
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/* PLLs */
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static const struct alpha_pll_config hfpll_config = {
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.l = 60,
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.config_ctl_val = 0x200d4aa8,
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.config_ctl_hi_val = 0x006,
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.pre_div_mask = BIT(12),
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.post_div_mask = 0x3 << 8,
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.post_div_val = 0x1 << 8,
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.main_output_mask = BIT(0),
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.early_output_mask = BIT(3),
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};
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static struct clk_alpha_pll perfcl_pll = {
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.offset = PERFCL_REG_OFFSET,
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.regs = prim_pll_regs,
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.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "perfcl_pll",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_alpha_pll_huayra_ops,
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},
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};
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static struct clk_alpha_pll pwrcl_pll = {
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.offset = PWRCL_REG_OFFSET,
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.regs = prim_pll_regs,
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.flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pwrcl_pll",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_alpha_pll_huayra_ops,
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},
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};
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static const struct pll_vco alt_pll_vco_modes[] = {
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VCO(3, 250000000, 500000000),
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VCO(2, 500000000, 750000000),
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VCO(1, 750000000, 1000000000),
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VCO(0, 1000000000, 2150400000),
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};
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static const struct alpha_pll_config altpll_config = {
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.l = 16,
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.vco_val = 0x3 << 20,
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.vco_mask = 0x3 << 20,
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.config_ctl_val = 0x4001051b,
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.post_div_mask = 0x3 << 8,
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.post_div_val = 0x1 << 8,
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.main_output_mask = BIT(0),
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.early_output_mask = BIT(3),
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};
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static struct clk_alpha_pll perfcl_alt_pll = {
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.offset = PERFCL_REG_OFFSET + ALT_PLL_OFFSET,
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.regs = alt_pll_regs,
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.vco_table = alt_pll_vco_modes,
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.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
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.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "perfcl_alt_pll",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_alpha_pll_hwfsm_ops,
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},
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};
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static struct clk_alpha_pll pwrcl_alt_pll = {
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.offset = PWRCL_REG_OFFSET + ALT_PLL_OFFSET,
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.regs = alt_pll_regs,
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.vco_table = alt_pll_vco_modes,
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.num_vco = ARRAY_SIZE(alt_pll_vco_modes),
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.flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
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.clkr.hw.init = &(struct clk_init_data) {
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.name = "pwrcl_alt_pll",
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.parent_names = (const char *[]){ "xo" },
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.num_parents = 1,
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.ops = &clk_alpha_pll_hwfsm_ops,
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},
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};
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struct clk_cpu_8996_mux {
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u32 reg;
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u8 shift;
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u8 width;
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struct notifier_block nb;
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struct clk_hw *pll;
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struct clk_hw *pll_div_2;
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struct clk_regmap clkr;
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};
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static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
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void *data);
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#define to_clk_cpu_8996_mux_nb(_nb) \
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container_of(_nb, struct clk_cpu_8996_mux, nb)
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static inline struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw)
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{
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return container_of(to_clk_regmap(hw), struct clk_cpu_8996_mux, clkr);
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}
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static u8 clk_cpu_8996_mux_get_parent(struct clk_hw *hw)
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{
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struct clk_regmap *clkr = to_clk_regmap(hw);
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struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
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u32 mask = GENMASK(cpuclk->width - 1, 0);
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u32 val;
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regmap_read(clkr->regmap, cpuclk->reg, &val);
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val >>= cpuclk->shift;
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return val & mask;
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}
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static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_regmap *clkr = to_clk_regmap(hw);
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struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
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u32 mask = GENMASK(cpuclk->width + cpuclk->shift - 1, cpuclk->shift);
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u32 val;
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val = index;
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val <<= cpuclk->shift;
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return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val);
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}
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static int clk_cpu_8996_mux_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
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struct clk_hw *parent = cpuclk->pll;
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if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) {
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if (req->rate < (DIV_2_THRESHOLD / 2))
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return -EINVAL;
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parent = cpuclk->pll_div_2;
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}
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req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
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req->best_parent_hw = parent;
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return 0;
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}
|
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static const struct clk_ops clk_cpu_8996_mux_ops = {
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.set_parent = clk_cpu_8996_mux_set_parent,
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.get_parent = clk_cpu_8996_mux_get_parent,
|
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.determine_rate = clk_cpu_8996_mux_determine_rate,
|
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};
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static struct clk_cpu_8996_mux pwrcl_smux = {
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.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
|
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.shift = 2,
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.width = 2,
|
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.clkr.hw.init = &(struct clk_init_data) {
|
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.name = "pwrcl_smux",
|
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.parent_names = (const char *[]){
|
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"xo",
|
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"pwrcl_pll_main",
|
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},
|
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.num_parents = 2,
|
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.ops = &clk_cpu_8996_mux_ops,
|
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.flags = CLK_SET_RATE_PARENT,
|
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},
|
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};
|
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|
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static struct clk_cpu_8996_mux perfcl_smux = {
|
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.reg = PERFCL_REG_OFFSET + MUX_OFFSET,
|
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.shift = 2,
|
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.width = 2,
|
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.clkr.hw.init = &(struct clk_init_data) {
|
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.name = "perfcl_smux",
|
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.parent_names = (const char *[]){
|
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"xo",
|
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"perfcl_pll_main",
|
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},
|
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.num_parents = 2,
|
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.ops = &clk_cpu_8996_mux_ops,
|
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.flags = CLK_SET_RATE_PARENT,
|
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},
|
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};
|
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|
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static struct clk_cpu_8996_mux pwrcl_pmux = {
|
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.reg = PWRCL_REG_OFFSET + MUX_OFFSET,
|
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.shift = 0,
|
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.width = 2,
|
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.pll = &pwrcl_pll.clkr.hw,
|
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.pll_div_2 = &pwrcl_smux.clkr.hw,
|
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.nb.notifier_call = cpu_clk_notifier_cb,
|
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.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "pwrcl_pmux",
|
||||
.parent_names = (const char *[]){
|
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"pwrcl_smux",
|
||||
"pwrcl_pll",
|
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"pwrcl_pll_acd",
|
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"pwrcl_alt_pll",
|
||||
},
|
||||
.num_parents = 4,
|
||||
.ops = &clk_cpu_8996_mux_ops,
|
||||
/* CPU clock is critical and should never be gated */
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_cpu_8996_mux perfcl_pmux = {
|
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.reg = PERFCL_REG_OFFSET + MUX_OFFSET,
|
||||
.shift = 0,
|
||||
.width = 2,
|
||||
.pll = &perfcl_pll.clkr.hw,
|
||||
.pll_div_2 = &perfcl_smux.clkr.hw,
|
||||
.nb.notifier_call = cpu_clk_notifier_cb,
|
||||
.clkr.hw.init = &(struct clk_init_data) {
|
||||
.name = "perfcl_pmux",
|
||||
.parent_names = (const char *[]){
|
||||
"perfcl_smux",
|
||||
"perfcl_pll",
|
||||
"perfcl_pll_acd",
|
||||
"perfcl_alt_pll",
|
||||
},
|
||||
.num_parents = 4,
|
||||
.ops = &clk_cpu_8996_mux_ops,
|
||||
/* CPU clock is critical and should never be gated */
|
||||
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct regmap_config cpu_msm8996_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x80210,
|
||||
.fast_io = true,
|
||||
.val_format_endian = REGMAP_ENDIAN_LITTLE,
|
||||
};
|
||||
|
||||
struct clk_regmap *cpu_msm8996_clks[] = {
|
||||
&perfcl_pll.clkr,
|
||||
&pwrcl_pll.clkr,
|
||||
&perfcl_alt_pll.clkr,
|
||||
&pwrcl_alt_pll.clkr,
|
||||
&perfcl_smux.clkr,
|
||||
&pwrcl_smux.clkr,
|
||||
&perfcl_pmux.clkr,
|
||||
&pwrcl_pmux.clkr,
|
||||
};
|
||||
|
||||
static int qcom_cpu_clk_msm8996_register_clks(struct device *dev,
|
||||
struct regmap *regmap)
|
||||
{
|
||||
int i, ret;
|
||||
|
||||
perfcl_smux.pll = clk_hw_register_fixed_factor(dev, "perfcl_pll_main",
|
||||
"perfcl_pll",
|
||||
CLK_SET_RATE_PARENT,
|
||||
1, 2);
|
||||
if (IS_ERR(perfcl_smux.pll)) {
|
||||
dev_err(dev, "Failed to initialize perfcl_pll_main\n");
|
||||
return PTR_ERR(perfcl_smux.pll);
|
||||
}
|
||||
|
||||
pwrcl_smux.pll = clk_hw_register_fixed_factor(dev, "pwrcl_pll_main",
|
||||
"pwrcl_pll",
|
||||
CLK_SET_RATE_PARENT,
|
||||
1, 2);
|
||||
if (IS_ERR(pwrcl_smux.pll)) {
|
||||
dev_err(dev, "Failed to initialize pwrcl_pll_main\n");
|
||||
clk_hw_unregister(perfcl_smux.pll);
|
||||
return PTR_ERR(pwrcl_smux.pll);
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cpu_msm8996_clks); i++) {
|
||||
ret = devm_clk_register_regmap(dev, cpu_msm8996_clks[i]);
|
||||
if (ret) {
|
||||
clk_hw_unregister(perfcl_smux.pll);
|
||||
clk_hw_unregister(pwrcl_smux.pll);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
|
||||
clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config);
|
||||
clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
|
||||
clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
|
||||
|
||||
/* Enable alt PLLs */
|
||||
clk_prepare_enable(pwrcl_alt_pll.clkr.hw.clk);
|
||||
clk_prepare_enable(perfcl_alt_pll.clkr.hw.clk);
|
||||
|
||||
clk_notifier_register(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
|
||||
clk_notifier_register(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int qcom_cpu_clk_msm8996_unregister_clks(void)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
ret = clk_notifier_unregister(pwrcl_pmux.clkr.hw.clk, &pwrcl_pmux.nb);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_notifier_unregister(perfcl_pmux.clkr.hw.clk, &perfcl_pmux.nb);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
clk_hw_unregister(perfcl_smux.pll);
|
||||
clk_hw_unregister(pwrcl_smux.pll);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define CPU_AFINITY_MASK 0xFFF
|
||||
#define PWRCL_CPU_REG_MASK 0x3
|
||||
#define PERFCL_CPU_REG_MASK 0x103
|
||||
|
||||
#define L2ACDCR_REG 0x580ULL
|
||||
#define L2ACDTD_REG 0x581ULL
|
||||
#define L2ACDDVMRC_REG 0x584ULL
|
||||
#define L2ACDSSCR_REG 0x589ULL
|
||||
|
||||
static DEFINE_SPINLOCK(qcom_clk_acd_lock);
|
||||
static void __iomem *base;
|
||||
|
||||
static void qcom_cpu_clk_msm8996_acd_init(void __iomem *base)
|
||||
{
|
||||
u64 hwid;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&qcom_clk_acd_lock, flags);
|
||||
|
||||
hwid = read_cpuid_mpidr() & CPU_AFINITY_MASK;
|
||||
|
||||
kryo_l2_set_indirect_reg(L2ACDTD_REG, 0x00006a11);
|
||||
kryo_l2_set_indirect_reg(L2ACDDVMRC_REG, 0x000e0f0f);
|
||||
kryo_l2_set_indirect_reg(L2ACDSSCR_REG, 0x00000601);
|
||||
|
||||
if (PWRCL_CPU_REG_MASK == (hwid | PWRCL_CPU_REG_MASK)) {
|
||||
writel(0xf, base + PWRCL_REG_OFFSET + SSSCTL_OFFSET);
|
||||
kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd);
|
||||
}
|
||||
|
||||
if (PERFCL_CPU_REG_MASK == (hwid | PERFCL_CPU_REG_MASK)) {
|
||||
kryo_l2_set_indirect_reg(L2ACDCR_REG, 0x002c5ffd);
|
||||
writel(0xf, base + PERFCL_REG_OFFSET + SSSCTL_OFFSET);
|
||||
}
|
||||
|
||||
spin_unlock_irqrestore(&qcom_clk_acd_lock, flags);
|
||||
}
|
||||
|
||||
static int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event,
|
||||
void *data)
|
||||
{
|
||||
struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb);
|
||||
struct clk_notifier_data *cnd = data;
|
||||
int ret;
|
||||
|
||||
switch (event) {
|
||||
case PRE_RATE_CHANGE:
|
||||
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX);
|
||||
qcom_cpu_clk_msm8996_acd_init(base);
|
||||
break;
|
||||
case POST_RATE_CHANGE:
|
||||
if (cnd->new_rate < DIV_2_THRESHOLD)
|
||||
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
|
||||
DIV_2_INDEX);
|
||||
else
|
||||
ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw,
|
||||
ACD_INDEX);
|
||||
break;
|
||||
default:
|
||||
ret = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
return notifier_from_errno(ret);
|
||||
};
|
||||
|
||||
static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct regmap *regmap;
|
||||
struct clk_hw_onecell_data *data;
|
||||
struct device *dev = &pdev->dev;
|
||||
int ret;
|
||||
|
||||
data = devm_kzalloc(dev, struct_size(data, hws, 2), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
regmap = devm_regmap_init_mmio(dev, base, &cpu_msm8996_regmap_config);
|
||||
if (IS_ERR(regmap))
|
||||
return PTR_ERR(regmap);
|
||||
|
||||
ret = qcom_cpu_clk_msm8996_register_clks(dev, regmap);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
qcom_cpu_clk_msm8996_acd_init(base);
|
||||
|
||||
data->hws[0] = &pwrcl_pmux.clkr.hw;
|
||||
data->hws[1] = &perfcl_pmux.clkr.hw;
|
||||
data->num = 2;
|
||||
|
||||
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data);
|
||||
}
|
||||
|
||||
static int qcom_cpu_clk_msm8996_driver_remove(struct platform_device *pdev)
|
||||
{
|
||||
return qcom_cpu_clk_msm8996_unregister_clks();
|
||||
}
|
||||
|
||||
static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = {
|
||||
{ .compatible = "qcom,msm8996-apcc" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qcom_cpu_clk_msm8996_match_table);
|
||||
|
||||
static struct platform_driver qcom_cpu_clk_msm8996_driver = {
|
||||
.probe = qcom_cpu_clk_msm8996_driver_probe,
|
||||
.remove = qcom_cpu_clk_msm8996_driver_remove,
|
||||
.driver = {
|
||||
.name = "qcom-msm8996-apcc",
|
||||
.of_match_table = qcom_cpu_clk_msm8996_match_table,
|
||||
},
|
||||
};
|
||||
module_platform_driver(qcom_cpu_clk_msm8996_driver);
|
||||
|
||||
MODULE_DESCRIPTION("QCOM MSM8996 CPU Clock Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -82,6 +82,7 @@ config FSL_IMX8_DDR_PMU
|
|||
config QCOM_L2_PMU
|
||||
bool "Qualcomm Technologies L2-cache PMU"
|
||||
depends on ARCH_QCOM && ARM64 && ACPI
|
||||
select QCOM_KRYO_L2_ACCESSORS
|
||||
help
|
||||
Provides support for the L2 cache performance monitor unit (PMU)
|
||||
in Qualcomm Technologies processors.
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#include <asm/barrier.h>
|
||||
#include <asm/local64.h>
|
||||
#include <asm/sysreg.h>
|
||||
#include <soc/qcom/kryo-l2-accessors.h>
|
||||
|
||||
#define MAX_L2_CTRS 9
|
||||
|
||||
|
|
@ -79,8 +80,6 @@
|
|||
#define L2_COUNTER_RELOAD BIT_ULL(31)
|
||||
#define L2_CYCLE_COUNTER_RELOAD BIT_ULL(63)
|
||||
|
||||
#define L2CPUSRSELR_EL1 sys_reg(3, 3, 15, 0, 6)
|
||||
#define L2CPUSRDR_EL1 sys_reg(3, 3, 15, 0, 7)
|
||||
|
||||
#define reg_idx(reg, i) (((i) * IA_L2_REG_OFFSET) + reg##_BASE)
|
||||
|
||||
|
|
@ -99,48 +98,7 @@
|
|||
#define L2_EVENT_STREX 0x421
|
||||
#define L2_EVENT_CLREX 0x422
|
||||
|
||||
static DEFINE_RAW_SPINLOCK(l2_access_lock);
|
||||
|
||||
/**
|
||||
* set_l2_indirect_reg: write value to an L2 register
|
||||
* @reg: Address of L2 register.
|
||||
* @value: Value to be written to register.
|
||||
*
|
||||
* Use architecturally required barriers for ordering between system register
|
||||
* accesses
|
||||
*/
|
||||
static void set_l2_indirect_reg(u64 reg, u64 val)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&l2_access_lock, flags);
|
||||
write_sysreg_s(reg, L2CPUSRSELR_EL1);
|
||||
isb();
|
||||
write_sysreg_s(val, L2CPUSRDR_EL1);
|
||||
isb();
|
||||
raw_spin_unlock_irqrestore(&l2_access_lock, flags);
|
||||
}
|
||||
|
||||
/**
|
||||
* get_l2_indirect_reg: read an L2 register value
|
||||
* @reg: Address of L2 register.
|
||||
*
|
||||
* Use architecturally required barriers for ordering between system register
|
||||
* accesses
|
||||
*/
|
||||
static u64 get_l2_indirect_reg(u64 reg)
|
||||
{
|
||||
u64 val;
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&l2_access_lock, flags);
|
||||
write_sysreg_s(reg, L2CPUSRSELR_EL1);
|
||||
isb();
|
||||
val = read_sysreg_s(L2CPUSRDR_EL1);
|
||||
raw_spin_unlock_irqrestore(&l2_access_lock, flags);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
struct cluster_pmu;
|
||||
|
||||
|
|
@ -211,28 +169,28 @@ static inline struct cluster_pmu *get_cluster_pmu(
|
|||
static void cluster_pmu_reset(void)
|
||||
{
|
||||
/* Reset all counters */
|
||||
set_l2_indirect_reg(L2PMCR, L2PMCR_RESET_ALL);
|
||||
set_l2_indirect_reg(L2PMCNTENCLR, l2_counter_present_mask);
|
||||
set_l2_indirect_reg(L2PMINTENCLR, l2_counter_present_mask);
|
||||
set_l2_indirect_reg(L2PMOVSCLR, l2_counter_present_mask);
|
||||
kryo_l2_set_indirect_reg(L2PMCR, L2PMCR_RESET_ALL);
|
||||
kryo_l2_set_indirect_reg(L2PMCNTENCLR, l2_counter_present_mask);
|
||||
kryo_l2_set_indirect_reg(L2PMINTENCLR, l2_counter_present_mask);
|
||||
kryo_l2_set_indirect_reg(L2PMOVSCLR, l2_counter_present_mask);
|
||||
}
|
||||
|
||||
static inline void cluster_pmu_enable(void)
|
||||
{
|
||||
set_l2_indirect_reg(L2PMCR, L2PMCR_COUNTERS_ENABLE);
|
||||
kryo_l2_set_indirect_reg(L2PMCR, L2PMCR_COUNTERS_ENABLE);
|
||||
}
|
||||
|
||||
static inline void cluster_pmu_disable(void)
|
||||
{
|
||||
set_l2_indirect_reg(L2PMCR, L2PMCR_COUNTERS_DISABLE);
|
||||
kryo_l2_set_indirect_reg(L2PMCR, L2PMCR_COUNTERS_DISABLE);
|
||||
}
|
||||
|
||||
static inline void cluster_pmu_counter_set_value(u32 idx, u64 value)
|
||||
{
|
||||
if (idx == l2_cycle_ctr_idx)
|
||||
set_l2_indirect_reg(L2PMCCNTR, value);
|
||||
kryo_l2_set_indirect_reg(L2PMCCNTR, value);
|
||||
else
|
||||
set_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx), value);
|
||||
kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx), value);
|
||||
}
|
||||
|
||||
static inline u64 cluster_pmu_counter_get_value(u32 idx)
|
||||
|
|
@ -240,46 +198,46 @@ static inline u64 cluster_pmu_counter_get_value(u32 idx)
|
|||
u64 value;
|
||||
|
||||
if (idx == l2_cycle_ctr_idx)
|
||||
value = get_l2_indirect_reg(L2PMCCNTR);
|
||||
value = kryo_l2_get_indirect_reg(L2PMCCNTR);
|
||||
else
|
||||
value = get_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx));
|
||||
value = kryo_l2_get_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx));
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static inline void cluster_pmu_counter_enable(u32 idx)
|
||||
{
|
||||
set_l2_indirect_reg(L2PMCNTENSET, idx_to_reg_bit(idx));
|
||||
kryo_l2_set_indirect_reg(L2PMCNTENSET, idx_to_reg_bit(idx));
|
||||
}
|
||||
|
||||
static inline void cluster_pmu_counter_disable(u32 idx)
|
||||
{
|
||||
set_l2_indirect_reg(L2PMCNTENCLR, idx_to_reg_bit(idx));
|
||||
kryo_l2_set_indirect_reg(L2PMCNTENCLR, idx_to_reg_bit(idx));
|
||||
}
|
||||
|
||||
static inline void cluster_pmu_counter_enable_interrupt(u32 idx)
|
||||
{
|
||||
set_l2_indirect_reg(L2PMINTENSET, idx_to_reg_bit(idx));
|
||||
kryo_l2_set_indirect_reg(L2PMINTENSET, idx_to_reg_bit(idx));
|
||||
}
|
||||
|
||||
static inline void cluster_pmu_counter_disable_interrupt(u32 idx)
|
||||
{
|
||||
set_l2_indirect_reg(L2PMINTENCLR, idx_to_reg_bit(idx));
|
||||
kryo_l2_set_indirect_reg(L2PMINTENCLR, idx_to_reg_bit(idx));
|
||||
}
|
||||
|
||||
static inline void cluster_pmu_set_evccntcr(u32 val)
|
||||
{
|
||||
set_l2_indirect_reg(L2PMCCNTCR, val);
|
||||
kryo_l2_set_indirect_reg(L2PMCCNTCR, val);
|
||||
}
|
||||
|
||||
static inline void cluster_pmu_set_evcntcr(u32 ctr, u32 val)
|
||||
{
|
||||
set_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTCR, ctr), val);
|
||||
kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVCNTCR, ctr), val);
|
||||
}
|
||||
|
||||
static inline void cluster_pmu_set_evtyper(u32 ctr, u32 val)
|
||||
{
|
||||
set_l2_indirect_reg(reg_idx(IA_L2PMXEVTYPER, ctr), val);
|
||||
kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVTYPER, ctr), val);
|
||||
}
|
||||
|
||||
static void cluster_pmu_set_resr(struct cluster_pmu *cluster,
|
||||
|
|
@ -295,11 +253,11 @@ static void cluster_pmu_set_resr(struct cluster_pmu *cluster,
|
|||
|
||||
spin_lock_irqsave(&cluster->pmu_lock, flags);
|
||||
|
||||
resr_val = get_l2_indirect_reg(L2PMRESR);
|
||||
resr_val = kryo_l2_get_indirect_reg(L2PMRESR);
|
||||
resr_val &= ~(L2PMRESR_GROUP_MASK << shift);
|
||||
resr_val |= field;
|
||||
resr_val |= L2PMRESR_EN;
|
||||
set_l2_indirect_reg(L2PMRESR, resr_val);
|
||||
kryo_l2_set_indirect_reg(L2PMRESR, resr_val);
|
||||
|
||||
spin_unlock_irqrestore(&cluster->pmu_lock, flags);
|
||||
}
|
||||
|
|
@ -315,14 +273,14 @@ static inline void cluster_pmu_set_evfilter_sys_mode(u32 ctr)
|
|||
L2PMXEVFILTER_ORGFILTER_IDINDEP |
|
||||
L2PMXEVFILTER_ORGFILTER_ALL;
|
||||
|
||||
set_l2_indirect_reg(reg_idx(IA_L2PMXEVFILTER, ctr), val);
|
||||
kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVFILTER, ctr), val);
|
||||
}
|
||||
|
||||
static inline u32 cluster_pmu_getreset_ovsr(void)
|
||||
{
|
||||
u32 result = get_l2_indirect_reg(L2PMOVSSET);
|
||||
u32 result = kryo_l2_get_indirect_reg(L2PMOVSSET);
|
||||
|
||||
set_l2_indirect_reg(L2PMOVSCLR, result);
|
||||
kryo_l2_set_indirect_reg(L2PMOVSCLR, result);
|
||||
return result;
|
||||
}
|
||||
|
||||
|
|
@ -767,7 +725,7 @@ static int get_num_counters(void)
|
|||
{
|
||||
int val;
|
||||
|
||||
val = get_l2_indirect_reg(L2PMCR);
|
||||
val = kryo_l2_get_indirect_reg(L2PMCR);
|
||||
|
||||
/*
|
||||
* Read number of counters from L2PMCR and add 1
|
||||
|
|
|
|||
|
|
@ -53,6 +53,10 @@ config QCOM_LLCC
|
|||
SDM845. This provides interfaces to clients that use the LLCC.
|
||||
Say yes here to enable LLCC slice driver.
|
||||
|
||||
config QCOM_KRYO_L2_ACCESSORS
|
||||
bool
|
||||
depends on ARCH_QCOM && ARM64 || COMPILE_TEST
|
||||
|
||||
config QCOM_MDT_LOADER
|
||||
tristate
|
||||
select QCOM_SCM
|
||||
|
|
|
|||
|
|
@ -24,3 +24,4 @@ obj-$(CONFIG_QCOM_APR) += apr.o
|
|||
obj-$(CONFIG_QCOM_LLCC) += llcc-qcom.o
|
||||
obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o
|
||||
obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o
|
||||
obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o
|
||||
|
|
|
|||
|
|
@ -0,0 +1,57 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/barrier.h>
|
||||
#include <asm/sysreg.h>
|
||||
#include <soc/qcom/kryo-l2-accessors.h>
|
||||
|
||||
#define L2CPUSRSELR_EL1 sys_reg(3, 3, 15, 0, 6)
|
||||
#define L2CPUSRDR_EL1 sys_reg(3, 3, 15, 0, 7)
|
||||
|
||||
static DEFINE_RAW_SPINLOCK(l2_access_lock);
|
||||
|
||||
/**
|
||||
* kryo_l2_set_indirect_reg() - write value to an L2 register
|
||||
* @reg: Address of L2 register.
|
||||
* @value: Value to be written to register.
|
||||
*
|
||||
* Use architecturally required barriers for ordering between system register
|
||||
* accesses, and system registers with respect to device memory
|
||||
*/
|
||||
void kryo_l2_set_indirect_reg(u64 reg, u64 val)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&l2_access_lock, flags);
|
||||
write_sysreg_s(reg, L2CPUSRSELR_EL1);
|
||||
isb();
|
||||
write_sysreg_s(val, L2CPUSRDR_EL1);
|
||||
isb();
|
||||
raw_spin_unlock_irqrestore(&l2_access_lock, flags);
|
||||
}
|
||||
EXPORT_SYMBOL(kryo_l2_set_indirect_reg);
|
||||
|
||||
/**
|
||||
* kryo_l2_get_indirect_reg() - read an L2 register value
|
||||
* @reg: Address of L2 register.
|
||||
*
|
||||
* Use architecturally required barriers for ordering between system register
|
||||
* accesses, and system registers with respect to device memory
|
||||
*/
|
||||
u64 kryo_l2_get_indirect_reg(u64 reg)
|
||||
{
|
||||
u64 val;
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&l2_access_lock, flags);
|
||||
write_sysreg_s(reg, L2CPUSRSELR_EL1);
|
||||
isb();
|
||||
val = read_sysreg_s(L2CPUSRDR_EL1);
|
||||
raw_spin_unlock_irqrestore(&l2_access_lock, flags);
|
||||
|
||||
return val;
|
||||
}
|
||||
EXPORT_SYMBOL(kryo_l2_get_indirect_reg);
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __SOC_ARCH_QCOM_KRYO_L2_ACCESSORS_H
|
||||
#define __SOC_ARCH_QCOM_KRYO_L2_ACCESSORS_H
|
||||
|
||||
void kryo_l2_set_indirect_reg(u64 reg, u64 val);
|
||||
u64 kryo_l2_get_indirect_reg(u64 reg);
|
||||
|
||||
#endif
|
||||
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