serial: pl011: Use cached copy of IMSC register

Commit 075167ed71 ("drivers: PL011: replace UART_MIS reading with
_RIS & _IMSC") amended this driver's interrupt handler to read the
Raw Interrupt Status (RIS) and Interrupt Mask Set/Clear (IMSC) registers
instead of the Masked Interrupt Status (MIS) register.  The change was
made to attain compatibility with SBSA UARTs which lack the MIS register.

However the IMSC register is cached by the driver.  Using the cached
copy saves one register read per interrupt.

I've tested this change successfully on a BCM2837 (Raspberry Pi CM3).

Cc: Mathias Duckeck <m.duckeck@kunbus.de>
Cc: Phil Elwell <phil@raspberrypi.org>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Mark Langsdorf <mlangsdo@redhat.com>
Cc: Naresh Bhat <nbhat@cavium.com>
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

drivers/tty/serial/amba-pl011.c

@@ -1480,12 +1480,10 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
 	struct uart_amba_port *uap = dev_id;
 	unsigned long flags;
 	unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
-	u16 imsc;
 	int handled = 0;
 
 	spin_lock_irqsave(&uap->port.lock, flags);
-	imsc = pl011_read(uap, REG_IMSC);
-	status = pl011_read(uap, REG_RIS) & imsc;
+	status = pl011_read(uap, REG_RIS) & uap->im;
 	if (status) {
 		do {
 			check_apply_cts_event_workaround(uap);
@@ -1509,7 +1507,7 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
 			if (pass_counter-- == 0)
 				break;
 
-			status = pl011_read(uap, REG_RIS) & imsc;
+			status = pl011_read(uap, REG_RIS) & uap->im;
 		} while (status != 0);
 		handled = 1;
 	}