x86: unify paravirt parts of system.h
This patch moves the i386 control registers manipulation functions, wbinvd, and clts functions to system.h. They are essentially the same as in x86_64. With this, system.h paravirt comes for free in x86_64. [ mingo@elte.hu: reintroduced the cr8 bits - needed for resume images ] Signed-off-by: Glauber de Oliveira Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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d3ca901f94
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@ -3,6 +3,8 @@
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#include <asm/asm.h>
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#include <linux/kernel.h>
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#ifdef CONFIG_X86_32
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# include "system_32.h"
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#else
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@ -38,6 +40,8 @@ __asm__ __volatile__ ("movw %%dx,%1\n\t" \
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#define set_base(ldt, base) _set_base(((char *)&(ldt)) , (base))
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#define set_limit(ldt, limit) _set_limit(((char *)&(ldt)) , ((limit)-1))
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extern void load_gs_index(unsigned);
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/*
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* Load a segment. Fall back on loading the zero
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* segment if something goes wrong..
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@ -72,6 +76,112 @@ static inline unsigned long get_limit(unsigned long segment)
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:"=r" (__limit):"r" (segment));
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return __limit+1;
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}
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static inline void native_clts(void)
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{
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asm volatile ("clts");
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}
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/*
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* Volatile isn't enough to prevent the compiler from reordering the
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* read/write functions for the control registers and messing everything up.
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* A memory clobber would solve the problem, but would prevent reordering of
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* all loads stores around it, which can hurt performance. Solution is to
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* use a variable and mimic reads and writes to it to enforce serialization
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*/
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static unsigned long __force_order;
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static inline unsigned long native_read_cr0(void)
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{
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unsigned long val;
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asm volatile("mov %%cr0,%0\n\t" :"=r" (val), "=m" (__force_order));
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return val;
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}
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static inline void native_write_cr0(unsigned long val)
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{
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asm volatile("mov %0,%%cr0": :"r" (val), "m" (__force_order));
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}
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static inline unsigned long native_read_cr2(void)
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{
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unsigned long val;
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asm volatile("mov %%cr2,%0\n\t" :"=r" (val), "=m" (__force_order));
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return val;
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}
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static inline void native_write_cr2(unsigned long val)
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{
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asm volatile("mov %0,%%cr2": :"r" (val), "m" (__force_order));
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}
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static inline unsigned long native_read_cr3(void)
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{
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unsigned long val;
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asm volatile("mov %%cr3,%0\n\t" :"=r" (val), "=m" (__force_order));
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return val;
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}
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static inline void native_write_cr3(unsigned long val)
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{
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asm volatile("mov %0,%%cr3": :"r" (val), "m" (__force_order));
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}
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static inline unsigned long native_read_cr4(void)
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{
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unsigned long val;
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asm volatile("mov %%cr4,%0\n\t" :"=r" (val), "=m" (__force_order));
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return val;
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}
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static inline unsigned long native_read_cr4_safe(void)
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{
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unsigned long val;
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/* This could fault if %cr4 does not exist. In x86_64, a cr4 always
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* exists, so it will never fail. */
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#ifdef CONFIG_X86_32
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asm volatile("1: mov %%cr4, %0 \n"
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"2: \n"
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".section __ex_table,\"a\" \n"
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".long 1b,2b \n"
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".previous \n"
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: "=r" (val), "=m" (__force_order) : "0" (0));
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#else
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val = native_read_cr4();
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#endif
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return val;
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}
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static inline void native_write_cr4(unsigned long val)
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{
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asm volatile("mov %0,%%cr4": :"r" (val), "m" (__force_order));
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}
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static inline void native_wbinvd(void)
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{
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asm volatile("wbinvd": : :"memory");
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}
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define read_cr0() (native_read_cr0())
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#define write_cr0(x) (native_write_cr0(x))
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#define read_cr2() (native_read_cr2())
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#define write_cr2(x) (native_write_cr2(x))
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#define read_cr3() (native_read_cr3())
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#define write_cr3(x) (native_write_cr3(x))
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#define read_cr4() (native_read_cr4())
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#define read_cr4_safe() (native_read_cr4_safe())
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#define write_cr4(x) (native_write_cr4(x))
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#define wbinvd() (native_wbinvd())
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/* Clear the 'TS' bit */
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#define clts() (native_clts())
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#endif/* CONFIG_PARAVIRT */
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#define stts() write_cr0(8 | read_cr0())
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#endif /* __KERNEL__ */
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static inline void clflush(void *__p)
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@ -1,7 +1,6 @@
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#ifndef __ASM_SYSTEM_H
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#define __ASM_SYSTEM_H
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#include <linux/kernel.h>
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#include <asm/segment.h>
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#include <asm/cpufeature.h>
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#include <asm/cmpxchg.h>
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@ -34,99 +33,6 @@ extern struct task_struct * FASTCALL(__switch_to(struct task_struct *prev, struc
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"2" (prev), "d" (next)); \
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} while (0)
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static inline void native_clts(void)
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{
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asm volatile ("clts");
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}
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static inline unsigned long native_read_cr0(void)
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{
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unsigned long val;
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asm volatile("movl %%cr0,%0\n\t" :"=r" (val));
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return val;
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}
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static inline void native_write_cr0(unsigned long val)
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{
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asm volatile("movl %0,%%cr0": :"r" (val));
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}
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static inline unsigned long native_read_cr2(void)
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{
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unsigned long val;
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asm volatile("movl %%cr2,%0\n\t" :"=r" (val));
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return val;
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}
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static inline void native_write_cr2(unsigned long val)
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{
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asm volatile("movl %0,%%cr2": :"r" (val));
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}
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static inline unsigned long native_read_cr3(void)
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{
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unsigned long val;
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asm volatile("movl %%cr3,%0\n\t" :"=r" (val));
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return val;
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}
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static inline void native_write_cr3(unsigned long val)
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{
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asm volatile("movl %0,%%cr3": :"r" (val));
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}
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static inline unsigned long native_read_cr4(void)
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{
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unsigned long val;
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asm volatile("movl %%cr4,%0\n\t" :"=r" (val));
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return val;
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}
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static inline unsigned long native_read_cr4_safe(void)
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{
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unsigned long val;
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/* This could fault if %cr4 does not exist */
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asm volatile("1: movl %%cr4, %0 \n"
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"2: \n"
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".section __ex_table,\"a\" \n"
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".long 1b,2b \n"
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".previous \n"
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: "=r" (val): "0" (0));
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return val;
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}
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static inline void native_write_cr4(unsigned long val)
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{
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asm volatile("movl %0,%%cr4": :"r" (val));
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}
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static inline void native_wbinvd(void)
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{
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asm volatile("wbinvd": : :"memory");
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}
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define read_cr0() (native_read_cr0())
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#define write_cr0(x) (native_write_cr0(x))
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#define read_cr2() (native_read_cr2())
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#define write_cr2(x) (native_write_cr2(x))
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#define read_cr3() (native_read_cr3())
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#define write_cr3(x) (native_write_cr3(x))
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#define read_cr4() (native_read_cr4())
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#define read_cr4_safe() (native_read_cr4_safe())
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#define write_cr4(x) (native_write_cr4(x))
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#define wbinvd() (native_wbinvd())
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/* Clear the 'TS' bit */
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#define clts() (native_clts())
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#endif/* CONFIG_PARAVIRT */
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/* Set the 'TS' bit */
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#define stts() write_cr0(8 | read_cr0())
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#endif /* __KERNEL__ */
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@ -1,7 +1,6 @@
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#ifndef __ASM_SYSTEM_H
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#define __ASM_SYSTEM_H
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#include <linux/kernel.h>
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#include <asm/segment.h>
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#include <asm/cmpxchg.h>
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[pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent)) \
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: "memory", "cc" __EXTRA_CLOBBER)
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extern void load_gs_index(unsigned);
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/*
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* Clear and set 'TS' bit respectively
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*/
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#define clts() __asm__ __volatile__ ("clts")
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static inline unsigned long read_cr0(void)
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{
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unsigned long cr0;
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asm volatile("movq %%cr0,%0" : "=r" (cr0));
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return cr0;
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}
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static inline void write_cr0(unsigned long val)
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{
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asm volatile("movq %0,%%cr0" :: "r" (val));
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}
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static inline unsigned long read_cr2(void)
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{
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unsigned long cr2;
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asm volatile("movq %%cr2,%0" : "=r" (cr2));
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return cr2;
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}
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static inline void write_cr2(unsigned long val)
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{
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asm volatile("movq %0,%%cr2" :: "r" (val));
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}
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static inline unsigned long read_cr3(void)
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{
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unsigned long cr3;
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asm volatile("movq %%cr3,%0" : "=r" (cr3));
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return cr3;
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}
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static inline void write_cr3(unsigned long val)
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{
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asm volatile("movq %0,%%cr3" :: "r" (val) : "memory");
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}
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static inline unsigned long read_cr4(void)
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{
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unsigned long cr4;
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asm volatile("movq %%cr4,%0" : "=r" (cr4));
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return cr4;
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}
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static inline void write_cr4(unsigned long val)
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{
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asm volatile("movq %0,%%cr4" :: "r" (val) : "memory");
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}
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static inline unsigned long read_cr8(void)
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{
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unsigned long cr8;
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asm volatile("movq %%cr8,%0" : "=r" (cr8));
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return cr8;
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}
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static inline void write_cr8(unsigned long val)
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{
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asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
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}
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#define stts() write_cr0(8 | read_cr0())
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#define wbinvd() \
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__asm__ __volatile__ ("wbinvd": : :"memory")
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#endif /* __KERNEL__ */
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#ifdef CONFIG_SMP
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@ -148,6 +75,18 @@ static inline void write_cr8(unsigned long val)
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#define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
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static inline unsigned long read_cr8(void)
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{
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unsigned long cr8;
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asm volatile("movq %%cr8,%0" : "=r" (cr8));
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return cr8;
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}
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static inline void write_cr8(unsigned long val)
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{
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asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
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}
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#include <linux/irqflags.h>
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#endif
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