AT91 SoC #2 for 5.18:
- SAMA5D29 variant to the SAMA5D2 family in SoC driver. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ5TRCVIBiyi/S+BG4fOrpwrNPNDAUCYiIhEwAKCRAfOrpwrNPN DFAlAP9xZajlf01HHkHuIYUY1yLwpIC+T/BhRWDx4K52frstAQEAhvSz47V9/v/l QkQGxuQyMjmihjFKh7+qVL8RgHZaPAc= =7HCW -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmInewAACgkQmmx57+YA GNkRuhAApqEF39tytJ7UHAhnjs+VxvYLQTP+ZBO6Dw0h/vG/sFWthG6sEJxgL8xv /ZOmDeABGB4+jsc9BXuBPV96sA6DkY2FKV0oHyOEvs0XsMU7Z4dmpTy/Zi1ji57O eKpqv4N2dEsqpq+JUTLHdTnTW5Gse8QHJ8krpNXx1J9k3acsEOupr2GfKfgqgy8C 4m2Y+2LFsCrtO8fVXgVnxgIDdmvAoc8jbkPJ1V+pHPkh4c+Ar5B1FpsK8XIOKde/ hvYQTJoPzSf5JAHZ5qZKQUMdQrTV9cdJLvwbR137e2soCHlkw4L7wNrhjW0rpTa8 6NVhGbz6xX8Inars5+2XIsbaSWV/g7XVTNvwtM7FM9aV/S9T/AZajc1HjJ+Tk2Ad et4AicpiBh9/0l77VsxngukpsZ8JPBNEz5fPLK3awA/eCFWHtiiBApz9Hp4sO2qg 25GJ0K0WAJSM27AbUCNjwYI/EQKqaZYvLq+k7jIMKXq5uX9lXwlAiG50kP8ZtvZb txKlZOYuqEHI5R7l5lTDkq7PL239fdBTb0M8G+uw65PY6HgwFarR7lvFFzAqFvMi Rx9eYLQhtP1d5sBOIUTATfHC9Qu+YpC1Sx9MHLyaU98V3TItTiD9YX6HRTFEaiv3 CTYx/g1XvX37kxtVD3q8Ea4uolqpOR+Kt8tSWRz4faD4gIJxA0s= =bF4h -----END PGP SIGNATURE----- Merge tag 'at91-soc-5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/drivers AT91 SoC #2 for 5.18: - SAMA5D29 variant to the SAMA5D2 family in SoC driver. * tag 'at91-soc-5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: ARM: at91: add support in soc driver for new SAMA5D29 soc: add microchip polarfire soc system controller ARM: at91: Kconfig: select PM_OPP ARM: at91: PM: add cpu idle support for sama7g5 ARM: at91: ddr: fix typo to align with datasheet naming ARM: at91: ddr: align macro definitions ARM: at91: ddr: remove CONFIG_SOC_SAMA7 dependency Link: https://lore.kernel.org/r/20220304144216.23340-1-nicolas.ferre@microchip.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
Коммит
d3d009847a
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@ -63,6 +63,7 @@ config SOC_SAMA7G5
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select HAVE_AT91_GENERATED_CLK
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select HAVE_AT91_SAM9X60_PLL
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select HAVE_AT91_UTMI
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select PM_OPP
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select SOC_SAMA7
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help
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Select this if you are using one of Microchip's SAMA7G5 family SoC.
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@ -605,6 +605,30 @@ static void at91sam9_sdram_standby(void)
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at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
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}
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static void sama7g5_standby(void)
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{
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int pwrtmg, ratio;
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pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL);
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ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO);
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/*
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* Place RAM into self-refresh after a maximum idle clocks. The maximum
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* idle clocks is configured by bootloader in
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* UDDRC_PWRMGT.SELFREF_TO_X32.
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*/
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writel(pwrtmg | UDDRC_PWRCTL_SELFREF_EN,
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soc_pm.data.ramc[0] + UDDRC_PWRCTL);
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/* Divide CPU clock by 16. */
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writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO);
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cpu_do_idle();
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/* Restore previous configuration. */
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writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO);
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writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL);
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}
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struct ramc_info {
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void (*idle)(void);
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unsigned int memctrl;
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@ -615,6 +639,7 @@ static const struct ramc_info ramc_infos[] __initconst = {
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{ .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
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{ .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
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{ .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
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{ .idle = sama7g5_standby, },
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};
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static const struct of_device_id ramc_ids[] __initconst = {
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@ -622,7 +647,7 @@ static const struct of_device_id ramc_ids[] __initconst = {
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{ .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
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{ .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
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{ .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
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{ .compatible = "microchip,sama7g5-uddrc", },
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{ .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], },
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{ /*sentinel*/ }
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};
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@ -159,7 +159,7 @@ sr_ena_1:
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/* Switch to self-refresh. */
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ldr tmp1, [r2, #UDDRC_PWRCTL]
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orr tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
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orr tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW
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str tmp1, [r2, #UDDRC_PWRCTL]
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sr_ena_2:
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@ -276,7 +276,7 @@ sr_dis_5:
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/* Trigger self-refresh exit. */
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ldr tmp1, [r2, #UDDRC_PWRCTL]
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bic tmp1, tmp1, #UDDRC_PWRCTRL_SELFREF_SW
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bic tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW
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str tmp1, [r2, #UDDRC_PWRCTL]
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sr_dis_6:
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@ -13,6 +13,7 @@ source "drivers/soc/imx/Kconfig"
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source "drivers/soc/ixp4xx/Kconfig"
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source "drivers/soc/litex/Kconfig"
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source "drivers/soc/mediatek/Kconfig"
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source "drivers/soc/microchip/Kconfig"
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source "drivers/soc/qcom/Kconfig"
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source "drivers/soc/renesas/Kconfig"
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source "drivers/soc/rockchip/Kconfig"
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@ -18,6 +18,7 @@ obj-y += ixp4xx/
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obj-$(CONFIG_SOC_XWAY) += lantiq/
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obj-$(CONFIG_LITEX_SOC_CONTROLLER) += litex/
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obj-y += mediatek/
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obj-y += microchip/
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obj-y += amlogic/
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obj-y += qcom/
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obj-y += renesas/
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@ -156,6 +156,9 @@ static const struct at91_soc socs[] __initconst = {
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AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
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AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH,
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"sama5d28c 256MiB LPDDR2 SiP", "sama5d2"),
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AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
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AT91_CIDR_VERSION_MASK, SAMA5D29CN_EXID_MATCH,
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"sama5d29", "sama5d2"),
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AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
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AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH,
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"sama5d31", "sama5d3"),
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@ -95,6 +95,7 @@ at91_soc_init(const struct at91_soc *socs);
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#define SAMA5D28C_LD2G_EXID_MATCH 0x00000072
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#define SAMA5D28CU_EXID_MATCH 0x00000010
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#define SAMA5D28CN_EXID_MATCH 0x00000020
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#define SAMA5D29CN_EXID_MATCH 0x00000023
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#define SAMA5D3_CIDR_MATCH 0x0a5c07c0
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#define SAMA5D31_EXID_MATCH 0x00444300
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@ -0,0 +1,10 @@
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config POLARFIRE_SOC_SYS_CTRL
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tristate "POLARFIRE_SOC_SYS_CTRL"
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depends on POLARFIRE_SOC_MAILBOX
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help
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This driver adds support for the PolarFire SoC (MPFS) system controller.
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To compile this driver as a module, choose M here. the
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module will be called mpfs_system_controller.
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If unsure, say N.
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@ -0,0 +1 @@
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obj-$(CONFIG_POLARFIRE_SOC_SYS_CTRL) += mpfs-sys-controller.o
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@ -0,0 +1,194 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Microchip PolarFire SoC (MPFS) system controller driver
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*
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* Copyright (c) 2020-2021 Microchip Corporation. All rights reserved.
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*
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* Author: Conor Dooley <conor.dooley@microchip.com>
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*
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*/
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#include <linux/slab.h>
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#include <linux/kref.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/of_platform.h>
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#include <linux/mailbox_client.h>
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#include <linux/platform_device.h>
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#include <soc/microchip/mpfs.h>
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static DEFINE_MUTEX(transaction_lock);
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struct mpfs_sys_controller {
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struct mbox_client client;
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struct mbox_chan *chan;
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struct completion c;
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struct kref consumers;
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};
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int mpfs_blocking_transaction(struct mpfs_sys_controller *sys_controller, struct mpfs_mss_msg *msg)
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{
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int ret, err;
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err = mutex_lock_interruptible(&transaction_lock);
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if (err)
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return err;
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reinit_completion(&sys_controller->c);
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ret = mbox_send_message(sys_controller->chan, msg);
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if (ret >= 0) {
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if (wait_for_completion_timeout(&sys_controller->c, HZ)) {
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ret = 0;
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} else {
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ret = -ETIMEDOUT;
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dev_warn(sys_controller->client.dev,
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"MPFS sys controller transaction timeout\n");
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}
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} else {
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dev_err(sys_controller->client.dev,
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"mpfs sys controller transaction returned %d\n", ret);
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}
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mutex_unlock(&transaction_lock);
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return ret;
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}
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EXPORT_SYMBOL(mpfs_blocking_transaction);
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static void rx_callback(struct mbox_client *client, void *msg)
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{
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struct mpfs_sys_controller *sys_controller =
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container_of(client, struct mpfs_sys_controller, client);
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complete(&sys_controller->c);
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}
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static void mpfs_sys_controller_delete(struct kref *kref)
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{
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struct mpfs_sys_controller *sys_controller = container_of(kref, struct mpfs_sys_controller,
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consumers);
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mbox_free_channel(sys_controller->chan);
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kfree(sys_controller);
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}
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void mpfs_sys_controller_put(void *data)
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{
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struct mpfs_sys_controller *sys_controller = data;
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kref_put(&sys_controller->consumers, mpfs_sys_controller_delete);
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}
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EXPORT_SYMBOL(mpfs_sys_controller_put);
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static struct platform_device subdevs[] = {
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{
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.name = "mpfs-rng",
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.id = -1,
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},
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{
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.name = "mpfs-generic-service",
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.id = -1,
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}
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};
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static int mpfs_sys_controller_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mpfs_sys_controller *sys_controller;
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int i;
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sys_controller = devm_kzalloc(dev, sizeof(*sys_controller), GFP_KERNEL);
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if (!sys_controller)
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return -ENOMEM;
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sys_controller->client.dev = dev;
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sys_controller->client.rx_callback = rx_callback;
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sys_controller->client.tx_block = 1U;
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sys_controller->chan = mbox_request_channel(&sys_controller->client, 0);
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if (IS_ERR(sys_controller->chan))
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return dev_err_probe(dev, PTR_ERR(sys_controller->chan),
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"Failed to get mbox channel\n");
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init_completion(&sys_controller->c);
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kref_init(&sys_controller->consumers);
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platform_set_drvdata(pdev, sys_controller);
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dev_info(&pdev->dev, "Registered MPFS system controller\n");
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for (i = 0; i < ARRAY_SIZE(subdevs); i++) {
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subdevs[i].dev.parent = dev;
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if (platform_device_register(&subdevs[i]))
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dev_warn(dev, "Error registering sub device %s\n", subdevs[i].name);
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}
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return 0;
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}
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static int mpfs_sys_controller_remove(struct platform_device *pdev)
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{
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struct mpfs_sys_controller *sys_controller = platform_get_drvdata(pdev);
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mpfs_sys_controller_put(sys_controller);
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return 0;
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}
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static const struct of_device_id mpfs_sys_controller_of_match[] = {
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{.compatible = "microchip,mpfs-sys-controller", },
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{},
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};
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MODULE_DEVICE_TABLE(of, mpfs_sys_controller_of_match);
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struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev)
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{
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const struct of_device_id *match;
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struct mpfs_sys_controller *sys_controller;
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int ret;
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if (!dev->parent)
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goto err_no_device;
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match = of_match_node(mpfs_sys_controller_of_match, dev->parent->of_node);
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of_node_put(dev->parent->of_node);
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if (!match)
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goto err_no_device;
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sys_controller = dev_get_drvdata(dev->parent);
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if (!sys_controller)
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goto err_bad_device;
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if (!kref_get_unless_zero(&sys_controller->consumers))
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goto err_bad_device;
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ret = devm_add_action_or_reset(dev, mpfs_sys_controller_put, sys_controller);
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if (ret)
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return ERR_PTR(ret);
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return sys_controller;
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err_no_device:
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dev_dbg(dev, "Parent device was not an MPFS system controller\n");
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return ERR_PTR(-ENODEV);
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err_bad_device:
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dev_dbg(dev, "MPFS system controller found but could not register as a sub device\n");
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return ERR_PTR(-EPROBE_DEFER);
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}
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EXPORT_SYMBOL(mpfs_sys_controller_get);
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static struct platform_driver mpfs_sys_controller_driver = {
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.driver = {
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.name = "mpfs-sys-controller",
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.of_match_table = mpfs_sys_controller_of_match,
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},
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.probe = mpfs_sys_controller_probe,
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.remove = mpfs_sys_controller_remove,
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};
|
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module_platform_driver(mpfs_sys_controller_driver);
|
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|
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
|
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MODULE_DESCRIPTION("MPFS system controller driver");
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|
|
@ -78,6 +78,10 @@
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#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
|
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|
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#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
|
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|
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#define AT91_PMC_RATIO 0x2c /* Processor clock ratio register [SAMA7G5 only] */
|
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#define AT91_PMC_RATIO_RATIO (0xf) /* CPU clock ratio. */
|
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|
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#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
|
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#define AT91_PMC_DIV (0xff << 0) /* Divider */
|
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#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
|
||||
|
|
|
|||
|
|
@ -11,15 +11,13 @@
|
|||
#ifndef __SAMA7_DDR_H__
|
||||
#define __SAMA7_DDR_H__
|
||||
|
||||
#ifdef CONFIG_SOC_SAMA7
|
||||
|
||||
/* DDR3PHY */
|
||||
#define DDR3PHY_PIR (0x04) /* DDR3PHY PHY Initialization Register */
|
||||
#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */
|
||||
#define DDR3PHY_PIR_DLLBYP (1 << 17) /* DLL Bypass */
|
||||
#define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */
|
||||
#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */
|
||||
#define DDR3PHY_PIR_DLLLOCK (1 << 2) /* DLL Lock */
|
||||
#define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */
|
||||
#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */
|
||||
#define DDR3PHY_PIR_INIT (1 << 0) /* Initialization Trigger */
|
||||
|
||||
#define DDR3PHY_PGCR (0x08) /* DDR3PHY PHY General Configuration Register */
|
||||
#define DDR3PHY_PGCR_CKDV1 (1 << 13) /* CK# Disable Value */
|
||||
|
|
@ -55,7 +53,8 @@
|
|||
#define UDDRC_STAT_OPMODE_MSK (0x7 << 0) /* Operating mode mask */
|
||||
|
||||
#define UDDRC_PWRCTL (0x30) /* UDDRC Low Power Control Register */
|
||||
#define UDDRC_PWRCTRL_SELFREF_SW (1 << 5) /* Software self-refresh */
|
||||
#define UDDRC_PWRCTL_SELFREF_EN (1 << 0) /* Automatic self-refresh */
|
||||
#define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */
|
||||
|
||||
#define UDDRC_DFIMISC (0x1B0) /* UDDRC DFI Miscellaneous Control Register */
|
||||
#define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */
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@ -67,7 +66,7 @@
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#define UDDRC_SWSTAT_SW_DONE_ACK (1 << 0) /* Register programming done */
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#define UDDRC_PSTAT (0x3FC) /* UDDRC Port Status Register */
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#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */
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#define UDDRC_PSTAT_ALL_PORTS (0x1F001F) /* Read + writes outstanding transactions on all ports */
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#define UDDRC_PCTRL_0 (0x490) /* UDDRC Port 0 Control Register */
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#define UDDRC_PCTRL_1 (0x540) /* UDDRC Port 1 Control Register */
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@ -75,6 +74,4 @@
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#define UDDRC_PCTRL_3 (0x6A0) /* UDDRC Port 3 Control Register */
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#define UDDRC_PCTRL_4 (0x750) /* UDDRC Port 4 Control Register */
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#endif /* CONFIG_SOC_SAMA7 */
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#endif /* __SAMA7_DDR_H__ */
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@ -34,9 +34,9 @@ struct mpfs_mss_response {
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#if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL)
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int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg);
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int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, struct mpfs_mss_msg *msg);
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struct mpfs_sys_controller *mpfs_sys_controller_get(struct device_node *mailbox_node);
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struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev);
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||||
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#endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */
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||||
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||||
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|
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