Merge branches 'clk-ux500', 'clk-mtk', 'clk-tegra', 'clk-allwinner' and 'clk-imx' into clk-next
- Convert ux500 to clk_hw - Add the two missing CLKOUT clocks for U8500/DB8500 SoC - MediaTek MT8186 SoC clk support - Move MediaTek driver to clk_hw provider APIs * clk-ux500: clk: ux500: fix a possible off-by-one in u8500_prcc_reset_base() clk: ux500: Implement the missing CLKOUT clocks clk: ux500: Rewrite PRCMU clocks to use clk_hw_* clk: ux500: Drop .is_prepared state from PRCMU clocks clk: ux500: Drop .is_enabled state from PRCMU clocks dt-bindings: clock: u8500: Add clkout clock bindings * clk-mtk: (22 commits) clk: mediatek: mt8173: Switch to clk_hw provider APIs clk: mediatek: Switch to clk_hw provider APIs clk: mediatek: Replace 'struct clk' with 'struct clk_hw' clk: mediatek: apmixed: Drop error message from clk_register() failure clk: mediatek: Make mtk_clk_register_composite() static clk: mediatek: use en_mask as a pure div_en_mask clk: mediatek: update compatible string for MT7986 ethsys clk: mediatek: Add MT8186 ipesys clock support clk: mediatek: Add MT8186 mdpsys clock support clk: mediatek: Add MT8186 camsys clock support clk: mediatek: Add MT8186 vencsys clock support clk: mediatek: Add MT8186 vdecsys clock support clk: mediatek: Add MT8186 imgsys clock support clk: mediatek: Add MT8186 wpesys clock support clk: mediatek: Add MT8186 mmsys clock support clk: mediatek: Add MT8186 mfgsys clock support clk: mediatek: Add MT8186 imp i2c wrapper clock support clk: mediatek: Add MT8186 apmixedsys clock support clk: mediatek: Add MT8186 infrastructure clock support clk: mediatek: Add MT8186 topckgen clock support ... * clk-tegra: clk: tegra: Update kerneldoc to match prototypes clk: tegra: Replace .round_rate() with .determine_rate() clk: tegra: Register clocks from root to leaf clk: tegra: Add missing reset deassertion * clk-allwinner: clk: sunxi-ng: h616: Add PLL derived 32KHz clock clk: sunxi-ng: h6-r: Add RTC gate clock * clk-imx: clk: imx8mp: fix usb_root_clk parent clk: imx8mp: add clkout1/2 support clk: imx: scu: Use pm_runtime_resume_and_get to fix pm_runtime_get_sync() usage clk: imx8mp: Add DISP2 pixel clock clk: imx: scu: fix a potential memory leak in __imx_clk_gpr_scu() clk: imx: Add check for kcalloc clk: imx8mn: add GPT support dt-bindings: imx: add clock bindings for i.MX8MN GPT clk: imx: Remove the snvs clock clk: imx8m: check mcore_booted before register clk clk: imx: add mcore_booted module paratemter clk: imx8mq: add 27m phy pll ref clock
This commit is contained in:
Stephen Boyd
Коммит
d3d88716a6
|
|
@ -0,0 +1,56 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MediaTek Functional Clock Controller for MT8186
|
||||
|
||||
maintainers:
|
||||
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
description: |
|
||||
The clock architecture in MediaTek like below
|
||||
PLLs -->
|
||||
dividers -->
|
||||
muxes
|
||||
-->
|
||||
clock gate
|
||||
|
||||
The devices provide clock gate control in different IP blocks.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8186-imp_iic_wrap
|
||||
- mediatek,mt8186-mfgsys
|
||||
- mediatek,mt8186-wpesys
|
||||
- mediatek,mt8186-imgsys1
|
||||
- mediatek,mt8186-imgsys2
|
||||
- mediatek,mt8186-vdecsys
|
||||
- mediatek,mt8186-vencsys
|
||||
- mediatek,mt8186-camsys
|
||||
- mediatek,mt8186-camsys_rawa
|
||||
- mediatek,mt8186-camsys_rawb
|
||||
- mediatek,mt8186-mdpsys
|
||||
- mediatek,mt8186-ipesys
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
imp_iic_wrap: clock-controller@11017000 {
|
||||
compatible = "mediatek,mt8186-imp_iic_wrap";
|
||||
reg = <0x11017000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MediaTek System Clock Controller for MT8186
|
||||
|
||||
maintainers:
|
||||
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
description: |
|
||||
The clock architecture in MediaTek like below
|
||||
PLLs -->
|
||||
dividers -->
|
||||
muxes
|
||||
-->
|
||||
clock gate
|
||||
|
||||
The apmixedsys provides most of PLLs which generated from SoC 26m.
|
||||
The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
|
||||
The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
|
||||
The mcusys provides mux control to select the clock source in AP MCU.
|
||||
The device nodes also provide the system control capacity for configuration.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- mediatek,mt8186-mcusys
|
||||
- mediatek,mt8186-topckgen
|
||||
- mediatek,mt8186-infracfg_ao
|
||||
- mediatek,mt8186-apmixedsys
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
topckgen: syscon@10000000 {
|
||||
compatible = "mediatek,mt8186-topckgen", "syscon";
|
||||
reg = <0x10000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
|
@ -109,6 +109,25 @@ properties:
|
|||
|
||||
additionalProperties: false
|
||||
|
||||
clkout-clock:
|
||||
description: A subnode with three clock cells for externally routed clocks,
|
||||
output clocks. These are two PRCMU-internal clocks that can be divided and
|
||||
muxed out on the pads of the DB8500 SoC.
|
||||
type: object
|
||||
|
||||
properties:
|
||||
'#clock-cells':
|
||||
description:
|
||||
The first cell indicates which output clock we are using,
|
||||
possible values are 0 (CLKOUT1) and 1 (CLKOUT2).
|
||||
The second cell indicates which clock we want to use as source,
|
||||
possible values are 0 thru 7, see the defines for the different
|
||||
source clocks.
|
||||
The third cell is a divider, legal values are 1 thru 63.
|
||||
const: 3
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
@ -119,3 +138,41 @@ required:
|
|||
- smp-twd-clock
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/ste-db8500-clkout.h>
|
||||
clocks@8012 {
|
||||
compatible = "stericsson,u8500-clks";
|
||||
reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
|
||||
<0x8000f000 0x1000>, <0xa03ff000 0x1000>,
|
||||
<0xa03cf000 0x1000>;
|
||||
|
||||
prcmu_clk: prcmu-clock {
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
prcc_pclk: prcc-periph-clock {
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
prcc_kclk: prcc-kernel-clock {
|
||||
#clock-cells = <2>;
|
||||
};
|
||||
|
||||
prcc_reset: prcc-reset-controller {
|
||||
#reset-cells = <2>;
|
||||
};
|
||||
|
||||
rtc_clk: rtc32k-clock {
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
smp_twd_clk: smp-twd-clock {
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
clkout_clk: clkout-clock {
|
||||
#clock-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -178,7 +178,7 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
|
|||
unsigned long flags)
|
||||
{
|
||||
struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
|
||||
struct clk_hw *div_hw, *gate_hw;
|
||||
struct clk_hw *div_hw, *gate_hw = NULL;
|
||||
struct clk_divider *div = NULL;
|
||||
struct clk_gate *gate = NULL;
|
||||
struct clk_mux *mux = NULL;
|
||||
|
|
@ -223,14 +223,17 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name,
|
|||
div->lock = &imx_ccm_lock;
|
||||
div->flags = CLK_DIVIDER_ROUND_CLOSEST;
|
||||
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate)
|
||||
goto fail;
|
||||
/* skip registering the gate ops if M4 is enabled */
|
||||
if (!mcore_booted) {
|
||||
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
|
||||
if (!gate)
|
||||
goto fail;
|
||||
|
||||
gate_hw = &gate->hw;
|
||||
gate->reg = reg;
|
||||
gate->bit_idx = PCG_CGC_SHIFT;
|
||||
gate->lock = &imx_ccm_lock;
|
||||
gate_hw = &gate->hw;
|
||||
gate->reg = reg;
|
||||
gate->bit_idx = PCG_CGC_SHIFT;
|
||||
gate->lock = &imx_ccm_lock;
|
||||
}
|
||||
|
||||
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
|
||||
mux_hw, mux_ops, div_hw,
|
||||
|
|
|
|||
|
|
@ -782,7 +782,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
|
|||
hws[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
|
||||
hws[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
|
||||
hws[IMX7D_OCOTP_CLK] = imx_clk_hw_gate4("ocotp_clk", "ipg_root_clk", base + 0x4230, 0);
|
||||
hws[IMX7D_SNVS_CLK] = imx_clk_hw_gate4("snvs_clk", "ipg_root_clk", base + 0x4250, 0);
|
||||
hws[IMX7D_MU_ROOT_CLK] = imx_clk_hw_gate4("mu_root_clk", "ipg_root_clk", base + 0x4270, 0);
|
||||
hws[IMX7D_CAAM_CLK] = imx_clk_hw_gate4("caam_clk", "ipg_root_clk", base + 0x4240, 0);
|
||||
hws[IMX7D_USB_HSIC_ROOT_CLK] = imx_clk_hw_gate4("usb_hsic_root_clk", "usb_hsic_post_div", base + 0x4690, 0);
|
||||
|
|
|
|||
|
|
@ -560,7 +560,6 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MM_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
|
||||
hws[IMX8MM_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
|
||||
hws[IMX8MM_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
|
||||
hws[IMX8MM_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
|
||||
hws[IMX8MM_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
|
||||
hws[IMX8MM_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
|
||||
hws[IMX8MM_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
|
|
@ -639,6 +638,8 @@ static struct platform_driver imx8mm_clk_driver = {
|
|||
},
|
||||
};
|
||||
module_platform_driver(imx8mm_clk_driver);
|
||||
module_param(mcore_booted, bool, S_IRUGO);
|
||||
MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
|
||||
|
||||
MODULE_AUTHOR("Bai Ping <ping.bai@nxp.com>");
|
||||
MODULE_DESCRIPTION("NXP i.MX8MM clock driver");
|
||||
|
|
|
|||
|
|
@ -227,6 +227,30 @@ static const char * const imx8mn_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys
|
|||
"sys_pll1_40m", "sys_pll3_out", "clk_ext2",
|
||||
"sys_pll1_80m", "video_pll1_out", };
|
||||
|
||||
static const char * const imx8mn_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
|
||||
"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
|
||||
"audio_pll1_out", "clk_ext1", };
|
||||
|
||||
static const char * const imx8mn_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
|
||||
"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
|
||||
"audio_pll1_out", "clk_ext1", };
|
||||
|
||||
static const char * const imx8mn_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
|
||||
"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
|
||||
"audio_pll1_out", "clk_ext1", };
|
||||
|
||||
static const char * const imx8mn_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
|
||||
"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
|
||||
"audio_pll1_out", "clk_ext1", };
|
||||
|
||||
static const char * const imx8mn_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
|
||||
"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
|
||||
"audio_pll1_out", "clk_ext1", };
|
||||
|
||||
static const char * const imx8mn_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m",
|
||||
"sys_pll1_40m", "video_pll1_out", "sys_pll1_80m",
|
||||
"audio_pll1_out", "clk_ext1", };
|
||||
|
||||
static const char * const imx8mn_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m",
|
||||
"vpu_pll_out", "sys_pll2_125m", "sys_pll3_out",
|
||||
"sys_pll1_80m", "sys_pll2_166m", };
|
||||
|
|
@ -476,6 +500,12 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MN_CLK_PWM2] = imx8m_clk_hw_composite("pwm2", imx8mn_pwm2_sels, base + 0xb400);
|
||||
hws[IMX8MN_CLK_PWM3] = imx8m_clk_hw_composite("pwm3", imx8mn_pwm3_sels, base + 0xb480);
|
||||
hws[IMX8MN_CLK_PWM4] = imx8m_clk_hw_composite("pwm4", imx8mn_pwm4_sels, base + 0xb500);
|
||||
hws[IMX8MN_CLK_GPT1] = imx8m_clk_hw_composite("gpt1", imx8mn_gpt1_sels, base + 0xb580);
|
||||
hws[IMX8MN_CLK_GPT2] = imx8m_clk_hw_composite("gpt2", imx8mn_gpt2_sels, base + 0xb600);
|
||||
hws[IMX8MN_CLK_GPT3] = imx8m_clk_hw_composite("gpt3", imx8mn_gpt3_sels, base + 0xb680);
|
||||
hws[IMX8MN_CLK_GPT4] = imx8m_clk_hw_composite("gpt4", imx8mn_gpt4_sels, base + 0xb700);
|
||||
hws[IMX8MN_CLK_GPT5] = imx8m_clk_hw_composite("gpt5", imx8mn_gpt5_sels, base + 0xb780);
|
||||
hws[IMX8MN_CLK_GPT6] = imx8m_clk_hw_composite("gpt6", imx8mn_gpt6_sels, base + 0xb800);
|
||||
hws[IMX8MN_CLK_WDOG] = imx8m_clk_hw_composite("wdog", imx8mn_wdog_sels, base + 0xb900);
|
||||
hws[IMX8MN_CLK_WRCLK] = imx8m_clk_hw_composite("wrclk", imx8mn_wrclk_sels, base + 0xb980);
|
||||
hws[IMX8MN_CLK_CLKO1] = imx8m_clk_hw_composite("clko1", imx8mn_clko1_sels, base + 0xba00);
|
||||
|
|
@ -501,6 +531,12 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MN_CLK_GPIO3_ROOT] = imx_clk_hw_gate4("gpio3_root_clk", "ipg_root", base + 0x40d0, 0);
|
||||
hws[IMX8MN_CLK_GPIO4_ROOT] = imx_clk_hw_gate4("gpio4_root_clk", "ipg_root", base + 0x40e0, 0);
|
||||
hws[IMX8MN_CLK_GPIO5_ROOT] = imx_clk_hw_gate4("gpio5_root_clk", "ipg_root", base + 0x40f0, 0);
|
||||
hws[IMX8MN_CLK_GPT1_ROOT] = imx_clk_hw_gate4("gpt1_root_clk", "gpt1", base + 0x4100, 0);
|
||||
hws[IMX8MN_CLK_GPT2_ROOT] = imx_clk_hw_gate4("gpt2_root_clk", "gpt2", base + 0x4110, 0);
|
||||
hws[IMX8MN_CLK_GPT3_ROOT] = imx_clk_hw_gate4("gpt3_root_clk", "gpt3", base + 0x4120, 0);
|
||||
hws[IMX8MN_CLK_GPT4_ROOT] = imx_clk_hw_gate4("gpt4_root_clk", "gpt4", base + 0x4130, 0);
|
||||
hws[IMX8MN_CLK_GPT5_ROOT] = imx_clk_hw_gate4("gpt5_root_clk", "gpt5", base + 0x4140, 0);
|
||||
hws[IMX8MN_CLK_GPT6_ROOT] = imx_clk_hw_gate4("gpt6_root_clk", "gpt6", base + 0x4150, 0);
|
||||
hws[IMX8MN_CLK_I2C1_ROOT] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0);
|
||||
hws[IMX8MN_CLK_I2C2_ROOT] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0);
|
||||
hws[IMX8MN_CLK_I2C3_ROOT] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0);
|
||||
|
|
@ -522,7 +558,6 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MN_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
|
||||
hws[IMX8MN_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
|
||||
hws[IMX8MN_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
|
||||
hws[IMX8MN_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
|
||||
hws[IMX8MN_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
|
||||
hws[IMX8MN_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
|
||||
hws[IMX8MN_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
|
|
@ -549,6 +584,8 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MN_CLK_SDMA3_ROOT] = imx_clk_hw_gate4("sdma3_clk", "ipg_audio_root", base + 0x45f0, 0);
|
||||
hws[IMX8MN_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root_clk", "sai7", base + 0x4650, 0, &share_count_sai7);
|
||||
|
||||
hws[IMX8MN_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc_24m", 1, 8);
|
||||
|
||||
hws[IMX8MN_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
|
||||
|
||||
hws[IMX8MN_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
|
||||
|
|
@ -594,6 +631,8 @@ static struct platform_driver imx8mn_clk_driver = {
|
|||
},
|
||||
};
|
||||
module_platform_driver(imx8mn_clk_driver);
|
||||
module_param(mcore_booted, bool, S_IRUGO);
|
||||
MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
|
||||
|
||||
MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
|
||||
MODULE_DESCRIPTION("NXP i.MX8MN clock driver");
|
||||
|
|
|
|||
|
|
@ -358,7 +358,7 @@ static const char * const imx8mp_media_mipi_phy1_ref_sels[] = {"osc_24m", "sys_p
|
|||
"clk_ext2", "audio_pll2_out",
|
||||
"video_pll1_out", };
|
||||
|
||||
static const char * const imx8mp_media_disp1_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
|
||||
static const char * const imx8mp_media_disp_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out",
|
||||
"audio_pll1_out", "sys_pll1_800m",
|
||||
"sys_pll2_1000m", "sys_pll3_out", "clk_ext4", };
|
||||
|
||||
|
|
@ -399,6 +399,11 @@ static const char * const imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "au
|
|||
|
||||
static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", };
|
||||
|
||||
static const char * const imx8mp_clkout_sels[] = {"audio_pll1_out", "audio_pll2_out", "video_pll1_out",
|
||||
"dummy", "dummy", "gpu_pll_out", "vpu_pll_out",
|
||||
"arm_pll_out", "sys_pll1", "sys_pll2", "sys_pll3",
|
||||
"dummy", "dummy", "osc_24m", "dummy", "osc_32k"};
|
||||
|
||||
static struct clk_hw **hws;
|
||||
static struct clk_hw_onecell_data *clk_hw_data;
|
||||
|
||||
|
|
@ -504,6 +509,15 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_SYS_PLL2_500M] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2);
|
||||
hws[IMX8MP_SYS_PLL2_1000M] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1);
|
||||
|
||||
hws[IMX8MP_CLK_CLKOUT1_SEL] = imx_clk_hw_mux2("clkout1_sel", anatop_base + 0x128, 4, 4,
|
||||
imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels));
|
||||
hws[IMX8MP_CLK_CLKOUT1_DIV] = imx_clk_hw_divider("clkout1_div", "clkout1_sel", anatop_base + 0x128, 0, 4);
|
||||
hws[IMX8MP_CLK_CLKOUT1] = imx_clk_hw_gate("clkout1", "clkout1_div", anatop_base + 0x128, 8);
|
||||
hws[IMX8MP_CLK_CLKOUT2_SEL] = imx_clk_hw_mux2("clkout2_sel", anatop_base + 0x128, 20, 4,
|
||||
imx8mp_clkout_sels, ARRAY_SIZE(imx8mp_clkout_sels));
|
||||
hws[IMX8MP_CLK_CLKOUT2_DIV] = imx_clk_hw_divider("clkout2_div", "clkout2_sel", anatop_base + 0x128, 16, 4);
|
||||
hws[IMX8MP_CLK_CLKOUT2] = imx_clk_hw_gate("clkout2", "clkout2_div", anatop_base + 0x128, 24);
|
||||
|
||||
hws[IMX8MP_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mp_a53_sels, ccm_base + 0x8000);
|
||||
hws[IMX8MP_CLK_A53_SRC] = hws[IMX8MP_CLK_A53_DIV];
|
||||
hws[IMX8MP_CLK_A53_CG] = hws[IMX8MP_CLK_A53_DIV];
|
||||
|
|
@ -538,6 +552,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_AHB] = imx8m_clk_hw_composite_bus_critical("ahb_root", imx8mp_ahb_sels, ccm_base + 0x9000);
|
||||
hws[IMX8MP_CLK_AUDIO_AHB] = imx8m_clk_hw_composite_bus("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100);
|
||||
hws[IMX8MP_CLK_MIPI_DSI_ESC_RX] = imx8m_clk_hw_composite_bus("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200);
|
||||
hws[IMX8MP_CLK_MEDIA_DISP2_PIX] = imx8m_clk_hw_composite("media_disp2_pix", imx8mp_media_disp_pix_sels, ccm_base + 0x9300);
|
||||
|
||||
hws[IMX8MP_CLK_IPG_ROOT] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1);
|
||||
|
||||
|
|
@ -600,7 +615,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_USDHC3] = imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3_sels, ccm_base + 0xbc80);
|
||||
hws[IMX8MP_CLK_MEDIA_CAM1_PIX] = imx8m_clk_hw_composite("media_cam1_pix", imx8mp_media_cam1_pix_sels, ccm_base + 0xbd00);
|
||||
hws[IMX8MP_CLK_MEDIA_MIPI_PHY1_REF] = imx8m_clk_hw_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80);
|
||||
hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite("media_disp1_pix", imx8mp_media_disp1_pix_sels, ccm_base + 0xbe00);
|
||||
hws[IMX8MP_CLK_MEDIA_DISP1_PIX] = imx8m_clk_hw_composite("media_disp1_pix", imx8mp_media_disp_pix_sels, ccm_base + 0xbe00);
|
||||
hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80);
|
||||
hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", imx8mp_media_ldb_sels, ccm_base + 0xbf00);
|
||||
hws[IMX8MP_CLK_MEMREPAIR] = imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base + 0xbf80);
|
||||
|
|
@ -654,12 +669,11 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
|
||||
hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_core", ccm_base + 0x4450, 0);
|
||||
hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core", ccm_base + 0x4460, 0);
|
||||
hws[IMX8MP_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", ccm_base + 0x4470, 0);
|
||||
hws[IMX8MP_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", ccm_base + 0x4490, 0);
|
||||
hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0);
|
||||
hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", ccm_base + 0x44b0, 0);
|
||||
hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", ccm_base + 0x44c0, 0);
|
||||
hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk", "osc_32k", ccm_base + 0x44d0, 0);
|
||||
hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk", "hsio_axi", ccm_base + 0x44d0, 0);
|
||||
hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk", "usb_phy_ref", ccm_base + 0x44f0, 0);
|
||||
hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", ccm_base + 0x4510, 0);
|
||||
hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", ccm_base + 0x4520, 0);
|
||||
|
|
@ -721,6 +735,8 @@ static struct platform_driver imx8mp_clk_driver = {
|
|||
},
|
||||
};
|
||||
module_platform_driver(imx8mp_clk_driver);
|
||||
module_param(mcore_booted, bool, S_IRUGO);
|
||||
MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
|
||||
|
||||
MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
|
||||
MODULE_DESCRIPTION("NXP i.MX8MP clock driver");
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ static u32 share_count_sai6;
|
|||
static u32 share_count_dcss;
|
||||
static u32 share_count_nand;
|
||||
|
||||
static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "dummy", "dummy", };
|
||||
static const char * const pll_ref_sels[] = { "osc_25m", "osc_27m", "hdmi_phy_27m", "dummy", };
|
||||
static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
|
||||
static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", };
|
||||
static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", };
|
||||
|
|
@ -557,7 +557,6 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||
hws[IMX8MQ_CLK_SAI5_IPG] = imx_clk_hw_gate2_shared2("sai5_ipg_clk", "ipg_audio_root", base + 0x4370, 0, &share_count_sai5);
|
||||
hws[IMX8MQ_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root_clk", "sai6", base + 0x4380, 0, &share_count_sai6);
|
||||
hws[IMX8MQ_CLK_SAI6_IPG] = imx_clk_hw_gate2_shared2("sai6_ipg_clk", "ipg_audio_root", base + 0x4380, 0, &share_count_sai6);
|
||||
hws[IMX8MQ_CLK_SNVS_ROOT] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", base + 0x4470, 0);
|
||||
hws[IMX8MQ_CLK_UART1_ROOT] = imx_clk_hw_gate4("uart1_root_clk", "uart1", base + 0x4490, 0);
|
||||
hws[IMX8MQ_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", base + 0x44a0, 0);
|
||||
hws[IMX8MQ_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", base + 0x44b0, 0);
|
||||
|
|
@ -632,6 +631,8 @@ static struct platform_driver imx8mq_clk_driver = {
|
|||
},
|
||||
};
|
||||
module_platform_driver(imx8mq_clk_driver);
|
||||
module_param(mcore_booted, bool, S_IRUGO);
|
||||
MODULE_PARM_DESC(mcore_booted, "See Cortex-M core is booted or not");
|
||||
|
||||
MODULE_AUTHOR("Abel Vesa <abel.vesa@nxp.com>");
|
||||
MODULE_DESCRIPTION("NXP i.MX8MQ clock driver");
|
||||
|
|
|
|||
|
|
@ -528,7 +528,7 @@ static int imx_clk_scu_probe(struct platform_device *pdev)
|
|||
pm_runtime_use_autosuspend(&pdev->dev);
|
||||
pm_runtime_enable(dev);
|
||||
|
||||
ret = pm_runtime_get_sync(dev);
|
||||
ret = pm_runtime_resume_and_get(dev);
|
||||
if (ret) {
|
||||
pm_genpd_remove_device(dev);
|
||||
pm_runtime_disable(dev);
|
||||
|
|
@ -837,8 +837,10 @@ struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_na
|
|||
if (!clk_node)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
if (!imx_scu_clk_is_valid(rsrc_id))
|
||||
if (!imx_scu_clk_is_valid(rsrc_id)) {
|
||||
kfree(clk_node);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
clk = kzalloc(sizeof(*clk), GFP_KERNEL);
|
||||
if (!clk) {
|
||||
|
|
|
|||
|
|
@ -17,6 +17,9 @@
|
|||
DEFINE_SPINLOCK(imx_ccm_lock);
|
||||
EXPORT_SYMBOL_GPL(imx_ccm_lock);
|
||||
|
||||
bool mcore_booted;
|
||||
EXPORT_SYMBOL_GPL(mcore_booted);
|
||||
|
||||
void imx_unregister_clocks(struct clk *clks[], unsigned int count)
|
||||
{
|
||||
unsigned int i;
|
||||
|
|
@ -173,6 +176,8 @@ void imx_register_uart_clocks(unsigned int clk_count)
|
|||
int i;
|
||||
|
||||
imx_uart_clocks = kcalloc(clk_count, sizeof(struct clk *), GFP_KERNEL);
|
||||
if (!imx_uart_clocks)
|
||||
return;
|
||||
|
||||
if (!of_stdout)
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@
|
|||
#include <linux/clk-provider.h>
|
||||
|
||||
extern spinlock_t imx_ccm_lock;
|
||||
extern bool mcore_booted;
|
||||
|
||||
void imx_check_clocks(struct clk *clks[], unsigned int count);
|
||||
void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
|
||||
|
|
|
|||
|
|
@ -512,6 +512,14 @@ config COMMON_CLK_MT8183_VENCSYS
|
|||
help
|
||||
This driver supports MediaTek MT8183 vencsys clocks.
|
||||
|
||||
config COMMON_CLK_MT8186
|
||||
bool "Clock driver for MediaTek MT8186"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
select COMMON_CLK_MEDIATEK
|
||||
default ARCH_MEDIATEK
|
||||
help
|
||||
This driver supports MediaTek MT8186 clocks.
|
||||
|
||||
config COMMON_CLK_MT8192
|
||||
bool "Clock driver for MediaTek MT8192"
|
||||
depends on ARM64 || COMPILE_TEST
|
||||
|
|
|
|||
|
|
@ -71,6 +71,11 @@ obj-$(CONFIG_COMMON_CLK_MT8183_MFGCFG) += clk-mt8183-mfgcfg.o
|
|||
obj-$(CONFIG_COMMON_CLK_MT8183_MMSYS) += clk-mt8183-mm.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \
|
||||
clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \
|
||||
clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
|
||||
clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \
|
||||
clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
|
||||
|
|
|
|||
|
|
@ -70,12 +70,12 @@ static const struct clk_ops mtk_ref2usb_tx_ops = {
|
|||
.unprepare = mtk_ref2usb_tx_unprepare,
|
||||
};
|
||||
|
||||
struct clk * __init mtk_clk_register_ref2usb_tx(const char *name,
|
||||
struct clk_hw * __init mtk_clk_register_ref2usb_tx(const char *name,
|
||||
const char *parent_name, void __iomem *reg)
|
||||
{
|
||||
struct mtk_ref2usb_tx *tx;
|
||||
struct clk_init_data init = {};
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
tx = kzalloc(sizeof(*tx), GFP_KERNEL);
|
||||
if (!tx)
|
||||
|
|
@ -89,14 +89,14 @@ struct clk * __init mtk_clk_register_ref2usb_tx(const char *name,
|
|||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
clk = clk_register(NULL, &tx->hw);
|
||||
ret = clk_hw_register(NULL, &tx->hw);
|
||||
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("Failed to register clk %s: %pe\n", name, clk);
|
||||
if (ret) {
|
||||
kfree(tx);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
return clk;
|
||||
return &tx->hw;
|
||||
}
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
|
|||
|
|
@ -57,12 +57,12 @@ static const struct clk_ops clk_cpumux_ops = {
|
|||
.set_parent = clk_cpumux_set_parent,
|
||||
};
|
||||
|
||||
static struct clk *
|
||||
static struct clk_hw *
|
||||
mtk_clk_register_cpumux(const struct mtk_composite *mux,
|
||||
struct regmap *regmap)
|
||||
{
|
||||
struct mtk_clk_cpumux *cpumux;
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
struct clk_init_data init;
|
||||
|
||||
cpumux = kzalloc(sizeof(*cpumux), GFP_KERNEL);
|
||||
|
|
@ -81,34 +81,33 @@ mtk_clk_register_cpumux(const struct mtk_composite *mux,
|
|||
cpumux->regmap = regmap;
|
||||
cpumux->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &cpumux->hw);
|
||||
if (IS_ERR(clk))
|
||||
ret = clk_hw_register(NULL, &cpumux->hw);
|
||||
if (ret) {
|
||||
kfree(cpumux);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
return clk;
|
||||
return &cpumux->hw;
|
||||
}
|
||||
|
||||
static void mtk_clk_unregister_cpumux(struct clk *clk)
|
||||
static void mtk_clk_unregister_cpumux(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_cpumux *cpumux;
|
||||
struct clk_hw *hw;
|
||||
|
||||
hw = __clk_get_hw(clk);
|
||||
if (!hw)
|
||||
return;
|
||||
|
||||
cpumux = to_mtk_clk_cpumux(hw);
|
||||
|
||||
clk_unregister(clk);
|
||||
clk_hw_unregister(hw);
|
||||
kfree(cpumux);
|
||||
}
|
||||
|
||||
int mtk_clk_register_cpumuxes(struct device_node *node,
|
||||
const struct mtk_composite *clks, int num,
|
||||
struct clk_onecell_data *clk_data)
|
||||
struct clk_hw_onecell_data *clk_data)
|
||||
{
|
||||
int i;
|
||||
struct clk *clk;
|
||||
struct clk_hw *hw;
|
||||
struct regmap *regmap;
|
||||
|
||||
regmap = device_node_to_regmap(node);
|
||||
|
|
@ -120,19 +119,20 @@ int mtk_clk_register_cpumuxes(struct device_node *node,
|
|||
for (i = 0; i < num; i++) {
|
||||
const struct mtk_composite *mux = &clks[i];
|
||||
|
||||
if (!IS_ERR_OR_NULL(clk_data->clks[mux->id])) {
|
||||
if (!IS_ERR_OR_NULL(clk_data->hws[mux->id])) {
|
||||
pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
|
||||
node, mux->id);
|
||||
continue;
|
||||
}
|
||||
|
||||
clk = mtk_clk_register_cpumux(mux, regmap);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("Failed to register clk %s: %pe\n", mux->name, clk);
|
||||
hw = mtk_clk_register_cpumux(mux, regmap);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("Failed to register clk %s: %pe\n", mux->name,
|
||||
hw);
|
||||
goto err;
|
||||
}
|
||||
|
||||
clk_data->clks[mux->id] = clk;
|
||||
clk_data->hws[mux->id] = hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -141,29 +141,29 @@ err:
|
|||
while (--i >= 0) {
|
||||
const struct mtk_composite *mux = &clks[i];
|
||||
|
||||
if (IS_ERR_OR_NULL(clk_data->clks[mux->id]))
|
||||
if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
|
||||
continue;
|
||||
|
||||
mtk_clk_unregister_cpumux(clk_data->clks[mux->id]);
|
||||
clk_data->clks[mux->id] = ERR_PTR(-ENOENT);
|
||||
mtk_clk_unregister_cpumux(clk_data->hws[mux->id]);
|
||||
clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
|
||||
}
|
||||
|
||||
return PTR_ERR(clk);
|
||||
return PTR_ERR(hw);
|
||||
}
|
||||
|
||||
void mtk_clk_unregister_cpumuxes(const struct mtk_composite *clks, int num,
|
||||
struct clk_onecell_data *clk_data)
|
||||
struct clk_hw_onecell_data *clk_data)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = num; i > 0; i--) {
|
||||
const struct mtk_composite *mux = &clks[i - 1];
|
||||
|
||||
if (IS_ERR_OR_NULL(clk_data->clks[mux->id]))
|
||||
if (IS_ERR_OR_NULL(clk_data->hws[mux->id]))
|
||||
continue;
|
||||
|
||||
mtk_clk_unregister_cpumux(clk_data->clks[mux->id]);
|
||||
clk_data->clks[mux->id] = ERR_PTR(-ENOENT);
|
||||
mtk_clk_unregister_cpumux(clk_data->hws[mux->id]);
|
||||
clk_data->hws[mux->id] = ERR_PTR(-ENOENT);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -7,15 +7,15 @@
|
|||
#ifndef __DRV_CLK_CPUMUX_H
|
||||
#define __DRV_CLK_CPUMUX_H
|
||||
|
||||
struct clk_onecell_data;
|
||||
struct clk_hw_onecell_data;
|
||||
struct device_node;
|
||||
struct mtk_composite;
|
||||
|
||||
int mtk_clk_register_cpumuxes(struct device_node *node,
|
||||
const struct mtk_composite *clks, int num,
|
||||
struct clk_onecell_data *clk_data);
|
||||
struct clk_hw_onecell_data *clk_data);
|
||||
|
||||
void mtk_clk_unregister_cpumuxes(const struct mtk_composite *clks, int num,
|
||||
struct clk_onecell_data *clk_data);
|
||||
struct clk_hw_onecell_data *clk_data);
|
||||
|
||||
#endif /* __DRV_CLK_CPUMUX_H */
|
||||
|
|
|
|||
|
|
@ -152,7 +152,7 @@ const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
|
|||
};
|
||||
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
|
||||
|
||||
static struct clk *mtk_clk_register_gate(const char *name,
|
||||
static struct clk_hw *mtk_clk_register_gate(const char *name,
|
||||
const char *parent_name,
|
||||
struct regmap *regmap, int set_ofs,
|
||||
int clr_ofs, int sta_ofs, u8 bit,
|
||||
|
|
@ -160,7 +160,7 @@ static struct clk *mtk_clk_register_gate(const char *name,
|
|||
unsigned long flags, struct device *dev)
|
||||
{
|
||||
struct mtk_clk_gate *cg;
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
struct clk_init_data init = {};
|
||||
|
||||
cg = kzalloc(sizeof(*cg), GFP_KERNEL);
|
||||
|
|
@ -181,35 +181,34 @@ static struct clk *mtk_clk_register_gate(const char *name,
|
|||
|
||||
cg->hw.init = &init;
|
||||
|
||||
clk = clk_register(dev, &cg->hw);
|
||||
if (IS_ERR(clk))
|
||||
ret = clk_hw_register(dev, &cg->hw);
|
||||
if (ret) {
|
||||
kfree(cg);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
return clk;
|
||||
return &cg->hw;
|
||||
}
|
||||
|
||||
static void mtk_clk_unregister_gate(struct clk *clk)
|
||||
static void mtk_clk_unregister_gate(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_gate *cg;
|
||||
struct clk_hw *hw;
|
||||
|
||||
hw = __clk_get_hw(clk);
|
||||
if (!hw)
|
||||
return;
|
||||
|
||||
cg = to_mtk_clk_gate(hw);
|
||||
|
||||
clk_unregister(clk);
|
||||
clk_hw_unregister(hw);
|
||||
kfree(cg);
|
||||
}
|
||||
|
||||
int mtk_clk_register_gates_with_dev(struct device_node *node,
|
||||
const struct mtk_gate *clks, int num,
|
||||
struct clk_onecell_data *clk_data,
|
||||
struct clk_hw_onecell_data *clk_data,
|
||||
struct device *dev)
|
||||
{
|
||||
int i;
|
||||
struct clk *clk;
|
||||
struct clk_hw *hw;
|
||||
struct regmap *regmap;
|
||||
|
||||
if (!clk_data)
|
||||
|
|
@ -224,13 +223,13 @@ int mtk_clk_register_gates_with_dev(struct device_node *node,
|
|||
for (i = 0; i < num; i++) {
|
||||
const struct mtk_gate *gate = &clks[i];
|
||||
|
||||
if (!IS_ERR_OR_NULL(clk_data->clks[gate->id])) {
|
||||
if (!IS_ERR_OR_NULL(clk_data->hws[gate->id])) {
|
||||
pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
|
||||
node, gate->id);
|
||||
continue;
|
||||
}
|
||||
|
||||
clk = mtk_clk_register_gate(gate->name, gate->parent_name,
|
||||
hw = mtk_clk_register_gate(gate->name, gate->parent_name,
|
||||
regmap,
|
||||
gate->regs->set_ofs,
|
||||
gate->regs->clr_ofs,
|
||||
|
|
@ -238,12 +237,13 @@ int mtk_clk_register_gates_with_dev(struct device_node *node,
|
|||
gate->shift, gate->ops,
|
||||
gate->flags, dev);
|
||||
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("Failed to register clk %s: %pe\n", gate->name, clk);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("Failed to register clk %s: %pe\n", gate->name,
|
||||
hw);
|
||||
goto err;
|
||||
}
|
||||
|
||||
clk_data->clks[gate->id] = clk;
|
||||
clk_data->hws[gate->id] = hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -252,26 +252,26 @@ err:
|
|||
while (--i >= 0) {
|
||||
const struct mtk_gate *gate = &clks[i];
|
||||
|
||||
if (IS_ERR_OR_NULL(clk_data->clks[gate->id]))
|
||||
if (IS_ERR_OR_NULL(clk_data->hws[gate->id]))
|
||||
continue;
|
||||
|
||||
mtk_clk_unregister_gate(clk_data->clks[gate->id]);
|
||||
clk_data->clks[gate->id] = ERR_PTR(-ENOENT);
|
||||
mtk_clk_unregister_gate(clk_data->hws[gate->id]);
|
||||
clk_data->hws[gate->id] = ERR_PTR(-ENOENT);
|
||||
}
|
||||
|
||||
return PTR_ERR(clk);
|
||||
return PTR_ERR(hw);
|
||||
}
|
||||
|
||||
int mtk_clk_register_gates(struct device_node *node,
|
||||
const struct mtk_gate *clks, int num,
|
||||
struct clk_onecell_data *clk_data)
|
||||
struct clk_hw_onecell_data *clk_data)
|
||||
{
|
||||
return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
|
||||
|
||||
void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
|
||||
struct clk_onecell_data *clk_data)
|
||||
struct clk_hw_onecell_data *clk_data)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
@ -281,11 +281,11 @@ void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
|
|||
for (i = num; i > 0; i--) {
|
||||
const struct mtk_gate *gate = &clks[i - 1];
|
||||
|
||||
if (IS_ERR_OR_NULL(clk_data->clks[gate->id]))
|
||||
if (IS_ERR_OR_NULL(clk_data->hws[gate->id]))
|
||||
continue;
|
||||
|
||||
mtk_clk_unregister_gate(clk_data->clks[gate->id]);
|
||||
clk_data->clks[gate->id] = ERR_PTR(-ENOENT);
|
||||
mtk_clk_unregister_gate(clk_data->hws[gate->id]);
|
||||
clk_data->hws[gate->id] = ERR_PTR(-ENOENT);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(mtk_clk_unregister_gates);
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
#include <linux/types.h>
|
||||
|
||||
struct clk;
|
||||
struct clk_onecell_data;
|
||||
struct clk_hw_onecell_data;
|
||||
struct clk_ops;
|
||||
struct device;
|
||||
struct device_node;
|
||||
|
|
@ -52,14 +52,14 @@ struct mtk_gate {
|
|||
|
||||
int mtk_clk_register_gates(struct device_node *node,
|
||||
const struct mtk_gate *clks, int num,
|
||||
struct clk_onecell_data *clk_data);
|
||||
struct clk_hw_onecell_data *clk_data);
|
||||
|
||||
int mtk_clk_register_gates_with_dev(struct device_node *node,
|
||||
const struct mtk_gate *clks, int num,
|
||||
struct clk_onecell_data *clk_data,
|
||||
struct clk_hw_onecell_data *clk_data,
|
||||
struct device *dev);
|
||||
|
||||
void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
|
||||
struct clk_onecell_data *clk_data);
|
||||
struct clk_hw_onecell_data *clk_data);
|
||||
|
||||
#endif /* __DRV_CLK_GATE_H */
|
||||
|
|
|
|||
|
|
@ -145,7 +145,7 @@ static const struct of_device_id of_match_clk_mt2701_aud[] = {
|
|||
|
||||
static int clk_mt2701_aud_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
|
|
@ -154,7 +154,7 @@ static int clk_mt2701_aud_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r) {
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@ static const struct of_device_id of_match_clk_mt2701_bdp[] = {
|
|||
|
||||
static int clk_mt2701_bdp_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -110,7 +110,7 @@ static int clk_mt2701_bdp_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ static const struct of_device_id of_match_clk_mt2701_eth[] = {
|
|||
|
||||
static int clk_mt2701_eth_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -52,7 +52,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ static const struct mtk_gate g3d_clks[] = {
|
|||
|
||||
static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
|
|
@ -46,7 +46,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ static const struct of_device_id of_match_clk_mt2701_hif[] = {
|
|||
|
||||
static int clk_mt2701_hif_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -49,7 +49,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r) {
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ static const struct of_device_id of_match_clk_mt2701_img[] = {
|
|||
|
||||
static int clk_mt2701_img_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -52,7 +52,7 @@ static int clk_mt2701_img_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -83,7 +83,7 @@ static int clk_mt2701_mm_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->parent->of_node;
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MM_NR);
|
||||
|
|
@ -91,7 +91,7 @@ static int clk_mt2701_mm_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ static const struct of_device_id of_match_clk_mt2701_vdec[] = {
|
|||
|
||||
static int clk_mt2701_vdec_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -63,7 +63,7 @@ static int clk_mt2701_vdec_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -666,7 +666,7 @@ static const struct mtk_gate top_clks[] = {
|
|||
|
||||
static int mtk_topckgen_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
void __iomem *base;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
|
@ -692,7 +692,7 @@ static int mtk_topckgen_init(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct mtk_gate_regs infra_cg_regs = {
|
||||
|
|
@ -735,7 +735,7 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
|
|||
FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
|
||||
};
|
||||
|
||||
static struct clk_onecell_data *infra_clk_data;
|
||||
static struct clk_hw_onecell_data *infra_clk_data;
|
||||
|
||||
static void __init mtk_infrasys_init_early(struct device_node *node)
|
||||
{
|
||||
|
|
@ -745,7 +745,7 @@ static void __init mtk_infrasys_init_early(struct device_node *node)
|
|||
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
|
||||
|
||||
for (i = 0; i < CLK_INFRA_NR; i++)
|
||||
infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
|
||||
infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
|
||||
}
|
||||
|
||||
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
|
||||
|
|
@ -754,7 +754,8 @@ static void __init mtk_infrasys_init_early(struct device_node *node)
|
|||
mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
|
||||
infra_clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
|
||||
infra_clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -771,8 +772,8 @@ static int mtk_infrasys_init(struct platform_device *pdev)
|
|||
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
|
||||
} else {
|
||||
for (i = 0; i < CLK_INFRA_NR; i++) {
|
||||
if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
|
||||
infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
|
||||
if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
|
||||
infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -781,7 +782,8 @@ static int mtk_infrasys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
|
||||
infra_clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
|
||||
infra_clk_data);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -886,7 +888,7 @@ static const struct mtk_composite peri_muxs[] = {
|
|||
|
||||
static int mtk_pericfg_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
void __iomem *base;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
|
@ -904,7 +906,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
|
|||
mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
|
||||
&mt2701_clk_lock, clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -935,13 +937,13 @@ static int mtk_pericfg_init(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
static const struct mtk_pll_data apmixed_plls[] = {
|
||||
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001,
|
||||
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,
|
||||
PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001,
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000,
|
||||
HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
|
||||
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001,
|
||||
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,
|
||||
HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0,
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0, 0,
|
||||
21, 0x230, 4, 0x0, 0x234, 0),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
|
||||
21, 0x240, 4, 0x0, 0x244, 0),
|
||||
|
|
@ -969,7 +971,7 @@ static const struct mtk_fixed_factor apmixed_fixed_divs[] = {
|
|||
|
||||
static int mtk_apmixedsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
|
||||
|
|
@ -981,7 +983,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2701[] = {
|
||||
|
|
|
|||
|
|
@ -60,7 +60,7 @@ static const struct mtk_gate bdp_clks[] = {
|
|||
|
||||
static int clk_mt2712_bdp_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -69,7 +69,7 @@ static int clk_mt2712_bdp_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ static const struct mtk_gate img_clks[] = {
|
|||
|
||||
static int clk_mt2712_img_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -47,7 +47,7 @@ static int clk_mt2712_img_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ static const struct mtk_gate jpgdec_clks[] = {
|
|||
|
||||
static int clk_mt2712_jpgdec_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -43,7 +43,7 @@ static int clk_mt2712_jpgdec_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, jpgdec_clks, ARRAY_SIZE(jpgdec_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ static const struct mtk_gate mfg_clks[] = {
|
|||
|
||||
static int clk_mt2712_mfg_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -42,7 +42,7 @@ static int clk_mt2712_mfg_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -130,7 +130,7 @@ static int clk_mt2712_mm_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->parent->of_node;
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
|
||||
|
|
@ -138,7 +138,7 @@ static int clk_mt2712_mm_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -52,7 +52,7 @@ static const struct mtk_gate vdec_clks[] = {
|
|||
|
||||
static int clk_mt2712_vdec_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -61,7 +61,7 @@ static int clk_mt2712_vdec_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ static const struct mtk_gate venc_clks[] = {
|
|||
|
||||
static int clk_mt2712_venc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -44,7 +44,7 @@ static int clk_mt2712_venc_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -1223,44 +1223,44 @@ static const struct mtk_pll_div_table mmpll_div_table[] = {
|
|||
};
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
|
||||
HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
|
||||
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,
|
||||
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
|
||||
HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
|
||||
PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,
|
||||
PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,
|
||||
0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
|
||||
PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,
|
||||
PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
|
||||
0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000100,
|
||||
0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000100,
|
||||
0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
|
||||
PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,
|
||||
PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000100,
|
||||
0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
|
||||
PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,
|
||||
PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000100,
|
||||
0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000100,
|
||||
0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
|
||||
PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,
|
||||
PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000100,
|
||||
0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000100,
|
||||
0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
|
||||
PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,
|
||||
PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000100,
|
||||
0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
|
||||
mmpll_div_table),
|
||||
PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,
|
||||
PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000100,
|
||||
HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
|
||||
armca35pll_div_table),
|
||||
PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,
|
||||
PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000100,
|
||||
0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
|
||||
armca72pll_div_table),
|
||||
PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,
|
||||
PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000100,
|
||||
0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
|
||||
};
|
||||
|
||||
static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -1268,7 +1268,7 @@ static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
|
|||
|
||||
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
@ -1277,7 +1277,7 @@ static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
|
|||
return r;
|
||||
}
|
||||
|
||||
static struct clk_onecell_data *top_clk_data;
|
||||
static struct clk_hw_onecell_data *top_clk_data;
|
||||
|
||||
static void clk_mt2712_top_init_early(struct device_node *node)
|
||||
{
|
||||
|
|
@ -1287,13 +1287,13 @@ static void clk_mt2712_top_init_early(struct device_node *node)
|
|||
top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
|
||||
|
||||
for (i = 0; i < CLK_TOP_NR_CLK; i++)
|
||||
top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
|
||||
top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
|
||||
}
|
||||
|
||||
mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
|
||||
top_clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -1318,8 +1318,8 @@ static int clk_mt2712_top_probe(struct platform_device *pdev)
|
|||
top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
|
||||
} else {
|
||||
for (i = 0; i < CLK_TOP_NR_CLK; i++) {
|
||||
if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
|
||||
top_clk_data->clks[i] = ERR_PTR(-ENOENT);
|
||||
if (top_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
|
||||
top_clk_data->hws[i] = ERR_PTR(-ENOENT);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1335,7 +1335,7 @@ static int clk_mt2712_top_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
|
||||
top_clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
@ -1346,7 +1346,7 @@ static int clk_mt2712_top_probe(struct platform_device *pdev)
|
|||
|
||||
static int clk_mt2712_infra_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -1355,7 +1355,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
@ -1368,7 +1368,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
|
|||
|
||||
static int clk_mt2712_peri_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -1377,7 +1377,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
@ -1390,7 +1390,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
|
|||
|
||||
static int clk_mt2712_mcu_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
void __iomem *base;
|
||||
|
|
@ -1406,7 +1406,7 @@ static int clk_mt2712_mcu_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
|
||||
&mt2712_clk_lock, clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@ static const struct mtk_gate audio_clks[] = {
|
|||
|
||||
static int clk_mt6765_audio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -75,7 +75,7 @@ static int clk_mt6765_audio_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, audio_clks,
|
||||
ARRAY_SIZE(audio_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ static const struct mtk_gate cam_clks[] = {
|
|||
|
||||
static int clk_mt6765_cam_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -49,7 +49,7 @@ static int clk_mt6765_cam_probe(struct platform_device *pdev)
|
|||
|
||||
mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ static const struct mtk_gate img_clks[] = {
|
|||
|
||||
static int clk_mt6765_img_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -45,7 +45,7 @@ static int clk_mt6765_img_probe(struct platform_device *pdev)
|
|||
|
||||
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ static const struct mtk_gate mipi0a_clks[] = {
|
|||
|
||||
static int clk_mt6765_mipi0a_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -43,7 +43,7 @@ static int clk_mt6765_mipi0a_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, mipi0a_clks,
|
||||
ARRAY_SIZE(mipi0a_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ static const struct mtk_gate mm_clks[] = {
|
|||
|
||||
static int clk_mt6765_mm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -71,7 +71,7 @@ static int clk_mt6765_mm_probe(struct platform_device *pdev)
|
|||
|
||||
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ static const struct mtk_gate venc_clks[] = {
|
|||
|
||||
static int clk_mt6765_vcodec_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -45,7 +45,7 @@ static int clk_mt6765_vcodec_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, venc_clks,
|
||||
ARRAY_SIZE(venc_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -748,32 +748,32 @@ static const struct mtk_gate apmixed_clks[] = {
|
|||
_pcw_reg, _pcw_shift, NULL) \
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, BIT(0),
|
||||
PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, 0,
|
||||
PLL_AO, 22, 8, 0x0220, 24, 0, 0, 0, 0x0220, 0),
|
||||
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, BIT(0),
|
||||
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, 0,
|
||||
PLL_AO, 22, 8, 0x0210, 24, 0, 0, 0, 0x0210, 0),
|
||||
PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, BIT(0),
|
||||
PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, 0,
|
||||
PLL_AO, 22, 8, 0x0230, 24, 0, 0, 0, 0x0230, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, BIT(0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, 0,
|
||||
(HAVE_RST_BAR | PLL_AO), 22, 8, 0x0240, 24, 0, 0, 0, 0x0240,
|
||||
0),
|
||||
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, BIT(0),
|
||||
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, 0,
|
||||
0, 22, 8, 0x0250, 24, 0, 0, 0, 0x0250, 0),
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, BIT(0),
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, 0,
|
||||
0, 22, 8, 0x0260, 24, 0, 0, 0, 0x0260, 0),
|
||||
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, BIT(0),
|
||||
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, 0,
|
||||
HAVE_RST_BAR, 22, 8, 0x0270, 24, 0, 0, 0, 0x0270, 0),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, BIT(0),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, 0,
|
||||
0, 22, 8, 0x0280, 24, 0, 0, 0, 0x0280, 0),
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, BIT(0),
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, 0,
|
||||
0, 32, 8, 0x0290, 24, 0x0040, 0x000C, 0, 0x0294, 0),
|
||||
PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, BIT(0),
|
||||
PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, 0,
|
||||
PLL_AO, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0),
|
||||
};
|
||||
|
||||
static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
void __iomem *base;
|
||||
|
|
@ -791,7 +791,7 @@ static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
|
|||
|
||||
mtk_clk_register_gates(node, apmixed_clks,
|
||||
ARRAY_SIZE(apmixed_clks), clk_data);
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
@ -811,7 +811,7 @@ static int clk_mt6765_top_probe(struct platform_device *pdev)
|
|||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
void __iomem *base;
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
|
|
@ -831,7 +831,7 @@ static int clk_mt6765_top_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
@ -848,7 +848,7 @@ static int clk_mt6765_top_probe(struct platform_device *pdev)
|
|||
|
||||
static int clk_mt6765_ifr_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
void __iomem *base;
|
||||
|
|
@ -864,7 +864,7 @@ static int clk_mt6765_ifr_probe(struct platform_device *pdev)
|
|||
|
||||
mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks),
|
||||
clk_data);
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -96,7 +96,7 @@ static const struct of_device_id of_match_clk_mt6779_aud[] = {
|
|||
|
||||
static int clk_mt6779_aud_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
|
||||
|
|
@ -104,7 +104,7 @@ static int clk_mt6779_aud_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt6779_aud_drv = {
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ static const struct of_device_id of_match_clk_mt6779_cam[] = {
|
|||
|
||||
static int clk_mt6779_cam_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
|
||||
|
|
@ -53,7 +53,7 @@ static int clk_mt6779_cam_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt6779_cam_drv = {
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ static const struct of_device_id of_match_clk_mt6779_img[] = {
|
|||
|
||||
static int clk_mt6779_img_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
|
||||
|
|
@ -45,7 +45,7 @@ static int clk_mt6779_img_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt6779_img_drv = {
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ static const struct of_device_id of_match_clk_mt6779_ipe[] = {
|
|||
|
||||
static int clk_mt6779_ipe_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_IPE_NR_CLK);
|
||||
|
|
@ -47,7 +47,7 @@ static int clk_mt6779_ipe_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, ipe_clks, ARRAY_SIZE(ipe_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt6779_ipe_drv = {
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ static const struct mtk_gate mfg_clks[] = {
|
|||
|
||||
static int clk_mt6779_mfg_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MFGCFG_NR_CLK);
|
||||
|
|
@ -37,7 +37,7 @@ static int clk_mt6779_mfg_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt6779_mfg[] = {
|
||||
|
|
|
|||
|
|
@ -89,14 +89,14 @@ static int clk_mt6779_mm_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->parent->of_node;
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt6779_mm_drv = {
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ static const struct of_device_id of_match_clk_mt6779_vdec[] = {
|
|||
|
||||
static int clk_mt6779_vdec_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VDEC_GCON_NR_CLK);
|
||||
|
|
@ -54,7 +54,7 @@ static int clk_mt6779_vdec_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt6779_vdec_drv = {
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ static const struct of_device_id of_match_clk_mt6779_venc[] = {
|
|||
|
||||
static int clk_mt6779_venc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VENC_GCON_NR_CLK);
|
||||
|
|
@ -45,7 +45,7 @@ static int clk_mt6779_venc_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt6779_venc_drv = {
|
||||
|
|
|
|||
|
|
@ -1182,39 +1182,39 @@ static const struct mtk_gate apmixed_clks[] = {
|
|||
_pcw_chg_reg, NULL)
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, BIT(0),
|
||||
PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
|
||||
PLL_AO, 0, 22, 8, 0x0204, 24, 0, 0, 0, 0x0204, 0, 0),
|
||||
PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, BIT(0),
|
||||
PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0210, 0x021C, 0,
|
||||
PLL_AO, 0, 22, 8, 0x0214, 24, 0, 0, 0, 0x0214, 0, 0),
|
||||
PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, BIT(0),
|
||||
PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x02A0, 0x02AC, 0,
|
||||
PLL_AO, 0, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, BIT(0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0,
|
||||
(HAVE_RST_BAR), BIT(24), 22, 8, 0x0234, 24, 0, 0, 0,
|
||||
0x0234, 0, 0),
|
||||
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, BIT(0),
|
||||
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0240, 0x024C, 0,
|
||||
(HAVE_RST_BAR), BIT(24), 22, 8, 0x0244, 24,
|
||||
0, 0, 0, 0x0244, 0, 0),
|
||||
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, BIT(0),
|
||||
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0250, 0x025C, 0,
|
||||
0, 0, 22, 8, 0x0254, 24, 0, 0, 0, 0x0254, 0, 0),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, BIT(0),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0260, 0x026C, 0,
|
||||
0, 0, 22, 8, 0x0264, 24, 0, 0, 0, 0x0264, 0, 0),
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, BIT(0),
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0,
|
||||
0, 0, 22, 8, 0x0274, 24, 0, 0, 0, 0x0274, 0, 0),
|
||||
PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, BIT(0),
|
||||
PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x02b0, 0x02bC, 0,
|
||||
(HAVE_RST_BAR), BIT(23), 22, 8, 0x02b4, 24,
|
||||
0, 0, 0, 0x02b4, 0, 0),
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, BIT(0),
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0280, 0x028C, 0,
|
||||
(HAVE_RST_BAR), BIT(23), 22, 8, 0x0284, 24,
|
||||
0, 0, 0, 0x0284, 0, 0),
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, BIT(0),
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x02C0, 0x02D0, 0,
|
||||
0, 0, 32, 8, 0x02C0, 1, 0, 0x14, 0, 0x02C4, 0, 0x2C0),
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, BIT(0),
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x02D4, 0x02E4, 0,
|
||||
0, 0, 32, 8, 0x02D4, 1, 0, 0x14, 1, 0x02D8, 0, 0x02D4),
|
||||
};
|
||||
|
||||
static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
|
||||
|
|
@ -1224,13 +1224,13 @@ static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, apmixed_clks,
|
||||
ARRAY_SIZE(apmixed_clks), clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static int clk_mt6779_top_probe(struct platform_device *pdev)
|
||||
{
|
||||
void __iomem *base;
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
|
|
@ -1253,12 +1253,12 @@ static int clk_mt6779_top_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs),
|
||||
base, &mt6779_clk_lock, clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static int clk_mt6779_infra_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
|
||||
|
|
@ -1266,7 +1266,7 @@ static int clk_mt6779_infra_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt6779[] = {
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@ static const struct of_device_id of_match_clk_mt6797_img[] = {
|
|||
|
||||
static int clk_mt6797_img_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -48,7 +48,7 @@ static int clk_mt6797_img_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -96,7 +96,7 @@ static int clk_mt6797_mm_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->parent->of_node;
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MM_NR);
|
||||
|
|
@ -104,7 +104,7 @@ static int clk_mt6797_mm_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ static const struct of_device_id of_match_clk_mt6797_vdec[] = {
|
|||
|
||||
static int clk_mt6797_vdec_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -65,7 +65,7 @@ static int clk_mt6797_vdec_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ static const struct of_device_id of_match_clk_mt6797_venc[] = {
|
|||
|
||||
static int clk_mt6797_venc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -50,7 +50,7 @@ static int clk_mt6797_venc_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -383,7 +383,7 @@ static const struct mtk_composite top_muxes[] = {
|
|||
|
||||
static int mtk_topckgen_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
void __iomem *base;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -399,7 +399,7 @@ static int mtk_topckgen_init(struct platform_device *pdev)
|
|||
mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
|
||||
&mt6797_clk_lock, clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct mtk_gate_regs infra0_cg_regs = {
|
||||
|
|
@ -556,7 +556,7 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
|
|||
FACTOR(CLK_INFRA_13M, "clk13m", "clk26m", 1, 2),
|
||||
};
|
||||
|
||||
static struct clk_onecell_data *infra_clk_data;
|
||||
static struct clk_hw_onecell_data *infra_clk_data;
|
||||
|
||||
static void mtk_infrasys_init_early(struct device_node *node)
|
||||
{
|
||||
|
|
@ -566,13 +566,14 @@ static void mtk_infrasys_init_early(struct device_node *node)
|
|||
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
|
||||
|
||||
for (i = 0; i < CLK_INFRA_NR; i++)
|
||||
infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
|
||||
infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
|
||||
}
|
||||
|
||||
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
|
||||
infra_clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
|
||||
infra_clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -590,8 +591,8 @@ static int mtk_infrasys_init(struct platform_device *pdev)
|
|||
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
|
||||
} else {
|
||||
for (i = 0; i < CLK_INFRA_NR; i++) {
|
||||
if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
|
||||
infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
|
||||
if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
|
||||
infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -600,7 +601,8 @@ static int mtk_infrasys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
|
||||
infra_clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
|
||||
infra_clk_data);
|
||||
}
|
||||
|
||||
#define MT6797_PLL_FMAX (3000UL * MHZ)
|
||||
|
|
@ -635,31 +637,31 @@ static int mtk_infrasys_init(struct platform_device *pdev)
|
|||
NULL)
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000101, PLL_AO,
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0xF0000100, PLL_AO,
|
||||
21, 0x220, 4, 0x0, 0x224, 0),
|
||||
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000011, 0, 7,
|
||||
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0230, 0x023C, 0xFE000010, 0, 7,
|
||||
0x230, 4, 0x0, 0x234, 14),
|
||||
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000101, 0, 21,
|
||||
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000100, 0, 21,
|
||||
0x244, 24, 0x0, 0x244, 0),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000121, 0, 21,
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000120, 0, 21,
|
||||
0x250, 4, 0x0, 0x254, 0),
|
||||
PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000121, 0, 21,
|
||||
PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0260, 0x026C, 0x00000120, 0, 21,
|
||||
0x260, 4, 0x0, 0x264, 0),
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000121, 0, 21,
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0270, 0x027C, 0xC0000120, 0, 21,
|
||||
0x270, 4, 0x0, 0x274, 0),
|
||||
PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000121, 0, 21,
|
||||
PLL(CLK_APMIXED_CODECPLL, "codecpll", 0x0290, 0x029C, 0x00000120, 0, 21,
|
||||
0x290, 4, 0x0, 0x294, 0),
|
||||
PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000121, 0, 21,
|
||||
PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x02E4, 0x02F0, 0x00000120, 0, 21,
|
||||
0x2E4, 4, 0x0, 0x2E8, 0),
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000131, 0, 31,
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000130, 0, 31,
|
||||
0x2A0, 4, 0x2A8, 0x2A4, 0),
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000131, 0, 31,
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x02B4, 0x02C4, 0x00000130, 0, 31,
|
||||
0x2B4, 4, 0x2BC, 0x2B8, 0),
|
||||
};
|
||||
|
||||
static int mtk_apmixedsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
|
||||
|
|
@ -668,7 +670,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
|
|||
|
||||
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt6797[] = {
|
||||
|
|
|
|||
|
|
@ -132,7 +132,7 @@ static const struct mtk_gate audio_clks[] = {
|
|||
|
||||
static int clk_mt7622_audiosys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
|
|
@ -141,7 +141,7 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r) {
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -67,7 +67,7 @@ static const struct mtk_gate sgmii_clks[] = {
|
|||
|
||||
static int clk_mt7622_ethsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
|
|
@ -76,7 +76,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
@ -89,7 +89,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
|
|||
|
||||
static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
|
|
@ -98,7 +98,7 @@ static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@ static const struct mtk_gate pcie_clks[] = {
|
|||
|
||||
static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
|
|
@ -87,7 +87,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
@ -100,7 +100,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
|
|||
|
||||
static int clk_mt7622_pciesys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
|
|
@ -109,7 +109,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -329,23 +329,23 @@ static const struct mtk_gate_regs peri1_cg_regs = {
|
|||
};
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
|
||||
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
|
||||
PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
|
||||
HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
|
||||
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
|
||||
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
|
||||
HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
|
||||
PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
|
||||
PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
|
||||
0, 21, 0x0300, 1, 0, 0x0304, 0),
|
||||
PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
|
||||
PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
|
||||
0, 21, 0x0314, 1, 0, 0x0318, 0),
|
||||
PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001,
|
||||
PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0,
|
||||
0, 31, 0x0324, 1, 0, 0x0328, 0),
|
||||
PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001,
|
||||
PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0,
|
||||
0, 31, 0x0334, 1, 0, 0x0338, 0),
|
||||
PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001,
|
||||
PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0,
|
||||
0, 21, 0x0344, 1, 0, 0x0348, 0),
|
||||
PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
|
||||
PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
|
||||
0, 21, 0x0358, 1, 0, 0x035C, 0),
|
||||
};
|
||||
|
||||
|
|
@ -612,7 +612,7 @@ static struct mtk_composite peri_muxes[] = {
|
|||
|
||||
static int mtk_topckgen_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
void __iomem *base;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -637,17 +637,17 @@ static int mtk_topckgen_init(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
|
||||
clk_data);
|
||||
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
|
||||
clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
|
||||
clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
|
||||
clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static int mtk_infrasys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
|
||||
|
|
@ -658,8 +658,8 @@ static int mtk_infrasys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get,
|
||||
clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
|
||||
clk_data);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
@ -670,7 +670,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
|
|||
|
||||
static int mtk_apmixedsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
|
||||
|
|
@ -683,15 +683,15 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, apmixed_clks,
|
||||
ARRAY_SIZE(apmixed_clks), clk_data);
|
||||
|
||||
clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
|
||||
clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
|
||||
clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
|
||||
clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static int mtk_pericfg_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
void __iomem *base;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
|
@ -708,11 +708,11 @@ static int mtk_pericfg_init(struct platform_device *pdev)
|
|||
mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
|
||||
&mt7622_clk_lock, clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
|
||||
clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
|
||||
|
||||
mtk_register_reset_controller(node, 2, 0x0);
|
||||
|
||||
|
|
|
|||
|
|
@ -78,7 +78,7 @@ static const struct mtk_gate sgmii_clks[2][4] = {
|
|||
|
||||
static int clk_mt7629_ethsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
|
|
@ -86,7 +86,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
|
|||
|
||||
mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
@ -99,7 +99,7 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
|
|||
|
||||
static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
static int id;
|
||||
int r;
|
||||
|
|
@ -109,7 +109,7 @@ static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -73,7 +73,7 @@ static const struct mtk_gate pcie_clks[] = {
|
|||
|
||||
static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
|
|
@ -82,7 +82,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
@ -95,7 +95,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
|
|||
|
||||
static int clk_mt7629_pciesys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
|
|
@ -104,7 +104,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
|
|
|
|||
|
|
@ -336,17 +336,17 @@ static const struct mtk_gate_regs peri1_cg_regs = {
|
|||
};
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
|
||||
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0,
|
||||
0, 21, 0x0204, 24, 0, 0x0204, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0,
|
||||
HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
|
||||
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
|
||||
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0,
|
||||
HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
|
||||
PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
|
||||
PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0,
|
||||
0, 21, 0x0300, 1, 0, 0x0304, 0),
|
||||
PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
|
||||
PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0,
|
||||
0, 21, 0x0314, 1, 0, 0x0318, 0),
|
||||
PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
|
||||
PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0,
|
||||
0, 21, 0x0358, 1, 0, 0x035C, 0),
|
||||
};
|
||||
|
||||
|
|
@ -572,7 +572,7 @@ static struct mtk_composite peri_muxes[] = {
|
|||
|
||||
static int mtk_topckgen_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
void __iomem *base;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -591,17 +591,17 @@ static int mtk_topckgen_init(struct platform_device *pdev)
|
|||
mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
|
||||
base, &mt7629_clk_lock, clk_data);
|
||||
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
|
||||
clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk);
|
||||
clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk);
|
||||
clk_prepare_enable(clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static int mtk_infrasys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
|
||||
|
||||
|
|
@ -611,13 +611,13 @@ static int mtk_infrasys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get,
|
||||
clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
|
||||
clk_data);
|
||||
}
|
||||
|
||||
static int mtk_pericfg_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
void __iomem *base;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
|
@ -634,18 +634,18 @@ static int mtk_pericfg_init(struct platform_device *pdev)
|
|||
mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
|
||||
&mt7629_clk_lock, clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
|
||||
clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_apmixedsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
|
||||
|
|
@ -658,10 +658,10 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, apmixed_clks,
|
||||
ARRAY_SIZE(apmixed_clks), clk_data);
|
||||
|
||||
clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
|
||||
clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
|
||||
clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
|
||||
clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -42,21 +42,21 @@
|
|||
"clkxtal")
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32,
|
||||
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, 0, 32,
|
||||
0x0200, 4, 0, 0x0204, 0),
|
||||
PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
|
||||
PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
|
||||
0x0210, 4, 0, 0x0214, 0),
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x0, 0, 32,
|
||||
0x0220, 4, 0, 0x0224, 0),
|
||||
PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x00000001, 0, 32,
|
||||
PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x0, 0, 32,
|
||||
0x0230, 4, 0, 0x0234, 0),
|
||||
PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x00000001, 0,
|
||||
PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x0, 0,
|
||||
32, 0x0240, 4, 0, 0x0244, 0),
|
||||
PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x00000001, 0, 32,
|
||||
PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x0, 0, 32,
|
||||
0x0250, 4, 0, 0x0254, 0),
|
||||
PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 0x0260,
|
||||
PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x0, 0, 32, 0x0260,
|
||||
4, 0, 0x0264, 0),
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x0, 0, 32,
|
||||
0x0278, 4, 0, 0x027c, 0),
|
||||
};
|
||||
|
||||
|
|
@ -67,7 +67,7 @@ static const struct of_device_id of_match_clk_mt7986_apmixed[] = {
|
|||
|
||||
static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
|
|
@ -77,9 +77,9 @@ static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
|
|||
|
||||
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
|
||||
|
||||
clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
|
||||
clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r) {
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ static const struct mtk_gate eth_clks[] __initconst = {
|
|||
|
||||
static void __init mtk_sgmiisys_0_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
|
||||
|
|
@ -87,7 +87,7 @@ static void __init mtk_sgmiisys_0_init(struct device_node *node)
|
|||
mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -97,7 +97,7 @@ CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0",
|
|||
|
||||
static void __init mtk_sgmiisys_1_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
|
||||
|
|
@ -105,7 +105,7 @@ static void __init mtk_sgmiisys_1_init(struct device_node *node)
|
|||
mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
@ -116,17 +116,17 @@ CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1",
|
|||
|
||||
static void __init mtk_ethsys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
|
||||
|
||||
mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
}
|
||||
CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys_ck", mtk_ethsys_init);
|
||||
CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys", mtk_ethsys_init);
|
||||
|
|
|
|||
|
|
@ -171,7 +171,7 @@ static const struct mtk_gate infra_clks[] = {
|
|||
|
||||
static int clk_mt7986_infracfg_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
void __iomem *base;
|
||||
|
|
@ -195,7 +195,7 @@ static int clk_mt7986_infracfg_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r) {
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
|
|||
|
|
@ -283,7 +283,7 @@ static const struct mtk_mux top_muxes[] = {
|
|||
|
||||
static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
void __iomem *base;
|
||||
|
|
@ -306,14 +306,14 @@ static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
|
||||
&mt7986_clk_lock, clk_data);
|
||||
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]);
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]);
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]);
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]);
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]);
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]);
|
||||
clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
|
||||
clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk);
|
||||
clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk);
|
||||
clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk);
|
||||
clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk);
|
||||
clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r) {
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -516,7 +516,7 @@ static const struct mtk_composite peri_clks[] __initconst = {
|
|||
|
||||
static void __init mtk_topckgen_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
void __iomem *base;
|
||||
int r;
|
||||
|
||||
|
|
@ -533,9 +533,9 @@ static void __init mtk_topckgen_init(struct device_node *node)
|
|||
mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
|
||||
&mt8135_clk_lock, clk_data);
|
||||
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_CCI_SEL]);
|
||||
clk_prepare_enable(clk_data->hws[CLK_TOP_CCI_SEL]->clk);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -544,7 +544,7 @@ CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init);
|
|||
|
||||
static void __init mtk_infrasys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
|
||||
|
|
@ -552,9 +552,9 @@ static void __init mtk_infrasys_init(struct device_node *node)
|
|||
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
|
||||
clk_data);
|
||||
|
||||
clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]);
|
||||
clk_prepare_enable(clk_data->hws[CLK_INFRA_M4U]->clk);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -565,7 +565,7 @@ CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
|
|||
|
||||
static void __init mtk_pericfg_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
void __iomem *base;
|
||||
|
||||
|
|
@ -582,7 +582,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
|
|||
mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
|
||||
&mt8135_clk_lock, clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -612,21 +612,21 @@ CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
|
|||
}
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
|
||||
PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000001, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000001, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
|
||||
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000001, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000001, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000001, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
|
||||
PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
|
||||
PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000001, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
|
||||
PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
|
||||
PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000000, 0, 21, 0x204, 24, 0x0, 0x204, 0),
|
||||
PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000000, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000000, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
|
||||
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000000, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000000, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000000, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000000, 0, 31, 0x294, 6, 0x0, 0x298, 0),
|
||||
PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
|
||||
PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000000, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
|
||||
PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c, 0x80000000, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
|
||||
};
|
||||
|
||||
static void __init mtk_apmixedsys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
|
||||
if (!clk_data)
|
||||
|
|
|
|||
|
|
@ -50,14 +50,14 @@ static const struct mtk_gate aud_clks[] __initconst = {
|
|||
|
||||
static void __init mtk_audsys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
|
|||
|
|
@ -43,14 +43,14 @@ static const struct mtk_gate img_clks[] __initconst = {
|
|||
|
||||
static void __init mtk_imgsys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -41,14 +41,14 @@ static const struct mtk_gate mfg_clks[] __initconst = {
|
|||
|
||||
static void __init mtk_mfgcfg_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@ static int clk_mt8167_mm_probe(struct platform_device *pdev)
|
|||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->parent->of_node;
|
||||
const struct clk_mt8167_mm_driver_data *data;
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int ret;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
|
||||
|
|
@ -115,7 +115,7 @@ static int clk_mt8167_mm_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -56,14 +56,14 @@ static const struct mtk_gate vdec_clks[] __initconst = {
|
|||
|
||||
static void __init mtk_vdecsys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
|
|||
|
|
@ -923,7 +923,7 @@ static const struct mtk_gate top_clks[] __initconst = {
|
|||
|
||||
static void __init mtk_topckgen_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
void __iomem *base;
|
||||
|
||||
|
|
@ -945,7 +945,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
|
|||
mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
|
||||
base, &mt8167_clk_lock, clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -954,7 +954,7 @@ CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8167-topckgen", mtk_topckgen_init);
|
|||
|
||||
static void __init mtk_infracfg_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
void __iomem *base;
|
||||
|
||||
|
|
@ -969,7 +969,7 @@ static void __init mtk_infracfg_init(struct device_node *node)
|
|||
mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base,
|
||||
&mt8167_clk_lock, clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -1017,27 +1017,27 @@ static const struct mtk_pll_div_table mmpll_div_table[] = {
|
|||
};
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0x00000001, 0,
|
||||
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0, 0,
|
||||
21, 0x0104, 24, 0, 0x0104, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0x00000001,
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0,
|
||||
HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
|
||||
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000001,
|
||||
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000000,
|
||||
HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
|
||||
PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0x00000001, 0,
|
||||
PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0, 0,
|
||||
21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0x00000001, 0,
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0, 0,
|
||||
31, 0x0180, 1, 0x0194, 0x0184, 0),
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0x00000001, 0,
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0, 0,
|
||||
31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0x00000001, 0,
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x01C0, 0x01D0, 0, 0,
|
||||
21, 0x01C4, 24, 0, 0x01C4, 0),
|
||||
PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0x00000001, 0,
|
||||
PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x01E0, 0x01F0, 0, 0,
|
||||
21, 0x01E4, 24, 0, 0x01E4, 0),
|
||||
};
|
||||
|
||||
static void __init mtk_apmixedsys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
void __iomem *base;
|
||||
int r;
|
||||
|
||||
|
|
@ -1053,7 +1053,7 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
|
|||
mtk_clk_register_dividers(apmixed_adj_divs, ARRAY_SIZE(apmixed_adj_divs),
|
||||
base, &mt8167_clk_lock, clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
|
|||
|
|
@ -115,7 +115,7 @@ static int clk_mt8173_mm_probe(struct platform_device *pdev)
|
|||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->parent->of_node;
|
||||
const struct clk_mt8173_mm_driver_data *data;
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int ret;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
|
||||
|
|
@ -129,7 +129,7 @@ static int clk_mt8173_mm_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
|
|
|||
|
|
@ -819,25 +819,25 @@ static const struct mtk_gate venclt_clks[] __initconst = {
|
|||
GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
|
||||
};
|
||||
|
||||
static struct clk_onecell_data *mt8173_top_clk_data __initdata;
|
||||
static struct clk_onecell_data *mt8173_pll_clk_data __initdata;
|
||||
static struct clk_hw_onecell_data *mt8173_top_clk_data __initdata;
|
||||
static struct clk_hw_onecell_data *mt8173_pll_clk_data __initdata;
|
||||
|
||||
static void __init mtk_clk_enable_critical(void)
|
||||
{
|
||||
if (!mt8173_top_clk_data || !mt8173_pll_clk_data)
|
||||
return;
|
||||
|
||||
clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA15PLL]);
|
||||
clk_prepare_enable(mt8173_pll_clk_data->clks[CLK_APMIXED_ARMCA7PLL]);
|
||||
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_MEM_SEL]);
|
||||
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
|
||||
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_CCI400_SEL]);
|
||||
clk_prepare_enable(mt8173_top_clk_data->clks[CLK_TOP_RTC_SEL]);
|
||||
clk_prepare_enable(mt8173_pll_clk_data->hws[CLK_APMIXED_ARMCA15PLL]->clk);
|
||||
clk_prepare_enable(mt8173_pll_clk_data->hws[CLK_APMIXED_ARMCA7PLL]->clk);
|
||||
clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_MEM_SEL]->clk);
|
||||
clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);
|
||||
clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_CCI400_SEL]->clk);
|
||||
clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_RTC_SEL]->clk);
|
||||
}
|
||||
|
||||
static void __init mtk_topckgen_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
void __iomem *base;
|
||||
int r;
|
||||
|
||||
|
|
@ -854,7 +854,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
|
|||
mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
|
||||
&mt8173_clk_lock, clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -865,7 +865,7 @@ CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
|
|||
|
||||
static void __init mtk_infrasys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
|
||||
|
|
@ -877,7 +877,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
|
|||
mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -888,7 +888,7 @@ CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
|
|||
|
||||
static void __init mtk_pericfg_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
void __iomem *base;
|
||||
|
||||
|
|
@ -905,7 +905,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
|
|||
mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
|
||||
&mt8173_clk_lock, clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -973,27 +973,27 @@ static const struct mtk_pll_div_table mmpll_div_table[] = {
|
|||
};
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
|
||||
PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
|
||||
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
|
||||
PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0x00000001, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0),
|
||||
PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0),
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
|
||||
PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0),
|
||||
PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000001, 0, 21, 0x290, 4, 0x0, 0x294, 0),
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0x00000001, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0x00000001, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
|
||||
PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0x00000001, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
|
||||
PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0x00000001, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
|
||||
PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0, 0, 21, 0x204, 24, 0x0, 0x204, 0),
|
||||
PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0, 0, 21, 0x214, 24, 0x0, 0x214, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000100, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x224, 0),
|
||||
PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000000, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x234, 14),
|
||||
PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x240, 0x24c, 0, 0, 21, 0x244, 24, 0x0, 0x244, 0, mmpll_div_table),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0, 0, 21, 0x250, 4, 0x0, 0x254, 0),
|
||||
PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0, 0, 21, 0x260, 4, 0x0, 0x264, 0),
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0, 0, 21, 0x270, 4, 0x0, 0x274, 0),
|
||||
PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0, 0, 21, 0x280, 4, 0x0, 0x284, 0),
|
||||
PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0, 0, 21, 0x290, 4, 0x0, 0x294, 0),
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x2a0, 0x2b0, 0, 0, 31, 0x2a0, 4, 0x2a4, 0x2a4, 0),
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x2b4, 0x2c4, 0, 0, 31, 0x2b4, 4, 0x2b8, 0x2b8, 0),
|
||||
PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2d0, 0x2dc, 0, 0, 21, 0x2d0, 4, 0x0, 0x2d4, 0),
|
||||
PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0),
|
||||
};
|
||||
|
||||
static void __init mtk_apmixedsys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
void __iomem *base;
|
||||
struct clk *clk;
|
||||
struct clk_hw *hw;
|
||||
int r, i;
|
||||
|
||||
base = of_iomap(node, 0);
|
||||
|
|
@ -1013,24 +1013,21 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
|
|||
for (i = 0; i < ARRAY_SIZE(apmixed_usb); i++) {
|
||||
const struct mtk_clk_usb *cku = &apmixed_usb[i];
|
||||
|
||||
clk = mtk_clk_register_ref2usb_tx(cku->name, cku->parent,
|
||||
base + cku->reg_ofs);
|
||||
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("Failed to register clk %s: %ld\n", cku->name,
|
||||
PTR_ERR(clk));
|
||||
hw = mtk_clk_register_ref2usb_tx(cku->name, cku->parent, base + cku->reg_ofs);
|
||||
if (IS_ERR(hw)) {
|
||||
pr_err("Failed to register clk %s: %ld\n", cku->name, PTR_ERR(hw));
|
||||
continue;
|
||||
}
|
||||
|
||||
clk_data->clks[cku->id] = clk;
|
||||
clk_data->hws[cku->id] = hw;
|
||||
}
|
||||
|
||||
clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
|
||||
base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
|
||||
NULL);
|
||||
clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;
|
||||
hw = clk_hw_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,
|
||||
base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,
|
||||
NULL);
|
||||
clk_data->hws[CLK_APMIXED_HDMI_REF] = hw;
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -1042,7 +1039,7 @@ CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
|
|||
|
||||
static void __init mtk_imgsys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
|
||||
|
|
@ -1050,7 +1047,7 @@ static void __init mtk_imgsys_init(struct device_node *node)
|
|||
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
|
|
@ -1060,7 +1057,7 @@ CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init);
|
|||
|
||||
static void __init mtk_vdecsys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
|
||||
|
|
@ -1068,7 +1065,7 @@ static void __init mtk_vdecsys_init(struct device_node *node)
|
|||
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -1077,7 +1074,7 @@ CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8173-vdecsys", mtk_vdecsys_init);
|
|||
|
||||
static void __init mtk_vencsys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
|
||||
|
|
@ -1085,7 +1082,7 @@ static void __init mtk_vencsys_init(struct device_node *node)
|
|||
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
@ -1094,7 +1091,7 @@ CLK_OF_DECLARE(mtk_vencsys, "mediatek,mt8173-vencsys", mtk_vencsys_init);
|
|||
|
||||
static void __init mtk_vencltsys_init(struct device_node *node)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VENCLT_NR_CLK);
|
||||
|
|
@ -1102,7 +1099,7 @@ static void __init mtk_vencltsys_init(struct device_node *node)
|
|||
mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ static const struct mtk_gate audio_clks[] = {
|
|||
|
||||
static int clk_mt8183_audio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
|
|
@ -78,7 +78,7 @@ static int clk_mt8183_audio_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ static const struct mtk_gate cam_clks[] = {
|
|||
|
||||
static int clk_mt8183_cam_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
|
||||
|
|
@ -44,7 +44,7 @@ static int clk_mt8183_cam_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8183_cam[] = {
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ static const struct mtk_gate img_clks[] = {
|
|||
|
||||
static int clk_mt8183_img_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
|
||||
|
|
@ -44,7 +44,7 @@ static int clk_mt8183_img_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8183_img[] = {
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ static const struct mtk_gate ipu_core0_clks[] = {
|
|||
|
||||
static int clk_mt8183_ipu_core0_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_IPU_CORE0_NR_CLK);
|
||||
|
|
@ -37,7 +37,7 @@ static int clk_mt8183_ipu_core0_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, ipu_core0_clks, ARRAY_SIZE(ipu_core0_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8183_ipu_core0[] = {
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ static const struct mtk_gate ipu_core1_clks[] = {
|
|||
|
||||
static int clk_mt8183_ipu_core1_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_IPU_CORE1_NR_CLK);
|
||||
|
|
@ -37,7 +37,7 @@ static int clk_mt8183_ipu_core1_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, ipu_core1_clks, ARRAY_SIZE(ipu_core1_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8183_ipu_core1[] = {
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@ static const struct mtk_gate ipu_adl_clks[] = {
|
|||
|
||||
static int clk_mt8183_ipu_adl_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_IPU_ADL_NR_CLK);
|
||||
|
|
@ -35,7 +35,7 @@ static int clk_mt8183_ipu_adl_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, ipu_adl_clks, ARRAY_SIZE(ipu_adl_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8183_ipu_adl[] = {
|
||||
|
|
|
|||
|
|
@ -96,7 +96,7 @@ static const struct mtk_gate ipu_conn_clks[] = {
|
|||
|
||||
static int clk_mt8183_ipu_conn_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_IPU_CONN_NR_CLK);
|
||||
|
|
@ -104,7 +104,7 @@ static int clk_mt8183_ipu_conn_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, ipu_conn_clks, ARRAY_SIZE(ipu_conn_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8183_ipu_conn[] = {
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@ static const struct mtk_gate mfg_clks[] = {
|
|||
|
||||
static int clk_mt8183_mfg_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
|
@ -38,7 +38,7 @@ static int clk_mt8183_mfg_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates_with_dev(node, mfg_clks, ARRAY_SIZE(mfg_clks),
|
||||
clk_data, &pdev->dev);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8183_mfg[] = {
|
||||
|
|
|
|||
|
|
@ -86,14 +86,14 @@ static int clk_mt8183_mm_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->parent->of_node;
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt8183_mm_drv = {
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ static const struct mtk_gate vdec_clks[] = {
|
|||
|
||||
static int clk_mt8183_vdec_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
|
||||
|
|
@ -48,7 +48,7 @@ static int clk_mt8183_vdec_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8183_vdec[] = {
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ static const struct mtk_gate venc_clks[] = {
|
|||
|
||||
static int clk_mt8183_venc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
|
||||
|
|
@ -40,7 +40,7 @@ static int clk_mt8183_venc_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8183_venc[] = {
|
||||
|
|
|
|||
|
|
@ -1122,40 +1122,40 @@ static const struct mtk_pll_div_table mfgpll_div_table[] = {
|
|||
};
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0x00000001,
|
||||
PLL_B(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0200, 0x020C, 0,
|
||||
HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0204, 24, 0x0, 0x0, 0,
|
||||
0x0204, 0, 0, armpll_div_table),
|
||||
PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0x00000001,
|
||||
PLL_B(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x0210, 0x021C, 0,
|
||||
HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0214, 24, 0x0, 0x0, 0,
|
||||
0x0214, 0, 0, armpll_div_table),
|
||||
PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0x00000001,
|
||||
PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0290, 0x029C, 0,
|
||||
HAVE_RST_BAR | PLL_AO, BIT(24), 22, 8, 0x0294, 24, 0x0, 0x0, 0,
|
||||
0x0294, 0, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0x00000001,
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0220, 0x022C, 0,
|
||||
HAVE_RST_BAR, BIT(24), 22, 8, 0x0224, 24, 0x0, 0x0, 0,
|
||||
0x0224, 0, 0),
|
||||
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0x00000001,
|
||||
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0230, 0x023C, 0,
|
||||
HAVE_RST_BAR, BIT(24), 22, 8, 0x0234, 24, 0x0, 0x0, 0,
|
||||
0x0234, 0, 0),
|
||||
PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0x00000001,
|
||||
PLL_B(CLK_APMIXED_MFGPLL, "mfgpll", 0x0240, 0x024C, 0,
|
||||
0, 0, 22, 8, 0x0244, 24, 0x0, 0x0, 0, 0x0244, 0, 0,
|
||||
mfgpll_div_table),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0x00000001,
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0250, 0x025C, 0,
|
||||
0, 0, 22, 8, 0x0254, 24, 0x0, 0x0, 0, 0x0254, 0, 0),
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0x00000001,
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0260, 0x026C, 0,
|
||||
0, 0, 22, 8, 0x0264, 24, 0x0, 0x0, 0, 0x0264, 0, 0),
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0x00000001,
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0270, 0x027C, 0,
|
||||
HAVE_RST_BAR, BIT(23), 22, 8, 0x0274, 24, 0x0, 0x0, 0,
|
||||
0x0274, 0, 0),
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0x00000001,
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x02A0, 0x02B0, 0,
|
||||
0, 0, 32, 8, 0x02A0, 1, 0x02A8, 0x0014, 0, 0x02A4, 0, 0x02A0),
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0x00000001,
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x02b4, 0x02c4, 0,
|
||||
0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
|
||||
};
|
||||
|
||||
static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
|
||||
|
|
@ -1165,10 +1165,10 @@ static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static struct clk_onecell_data *top_clk_data;
|
||||
static struct clk_hw_onecell_data *top_clk_data;
|
||||
|
||||
static void clk_mt8183_top_init_early(struct device_node *node)
|
||||
{
|
||||
|
|
@ -1177,12 +1177,12 @@ static void clk_mt8183_top_init_early(struct device_node *node)
|
|||
top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
|
||||
|
||||
for (i = 0; i < CLK_TOP_NR_CLK; i++)
|
||||
top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
|
||||
top_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
|
||||
|
||||
mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
|
||||
top_clk_data);
|
||||
|
||||
of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
|
||||
of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data);
|
||||
}
|
||||
|
||||
CLK_OF_DECLARE_DRIVER(mt8183_topckgen, "mediatek,mt8183-topckgen",
|
||||
|
|
@ -1217,12 +1217,13 @@ static int clk_mt8183_top_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
|
||||
top_clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
|
||||
top_clk_data);
|
||||
}
|
||||
|
||||
static int clk_mt8183_infra_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
|
|
@ -1231,7 +1232,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r) {
|
||||
dev_err(&pdev->dev,
|
||||
"%s(): could not register clock provider: %d\n",
|
||||
|
|
@ -1246,7 +1247,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
|
|||
|
||||
static int clk_mt8183_peri_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
|
||||
|
|
@ -1254,12 +1255,12 @@ static int clk_mt8183_peri_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
|
||||
clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static int clk_mt8183_mcu_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
void __iomem *base;
|
||||
|
||||
|
|
@ -1272,7 +1273,7 @@ static int clk_mt8183_mcu_probe(struct platform_device *pdev)
|
|||
mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
|
||||
&mt8183_clk_lock, clk_data);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8183[] = {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,133 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// Copyright (c) 2022 MediaTek Inc.
|
||||
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/clock/mt8186-clk.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-pll.h"
|
||||
|
||||
#define MT8186_PLL_FMAX (3800UL * MHZ)
|
||||
#define MT8186_PLL_FMIN (1500UL * MHZ)
|
||||
#define MT8186_INTEGER_BITS (8)
|
||||
|
||||
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
|
||||
_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
|
||||
_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
|
||||
_pcw_reg) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.reg = _reg, \
|
||||
.pwr_reg = _pwr_reg, \
|
||||
.en_mask = _en_mask, \
|
||||
.flags = _flags, \
|
||||
.rst_bar_mask = _rst_bar_mask, \
|
||||
.fmax = MT8186_PLL_FMAX, \
|
||||
.fmin = MT8186_PLL_FMIN, \
|
||||
.pcwbits = _pcwbits, \
|
||||
.pcwibits = MT8186_INTEGER_BITS, \
|
||||
.pd_reg = _pd_reg, \
|
||||
.pd_shift = _pd_shift, \
|
||||
.tuner_reg = _tuner_reg, \
|
||||
.tuner_en_reg = _tuner_en_reg, \
|
||||
.tuner_en_bit = _tuner_en_bit, \
|
||||
.pcw_reg = _pcw_reg, \
|
||||
.pcw_shift = 0, \
|
||||
.pcw_chg_reg = 0, \
|
||||
.en_reg = 0, \
|
||||
.pll_en_bit = 0, \
|
||||
}
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
/*
|
||||
* armpll_ll/armpll_bl/ccipll are main clock source of AP MCU,
|
||||
* should not be closed in Linux world.
|
||||
*/
|
||||
PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0204, 0x0210, 0,
|
||||
PLL_AO, 0, 22, 0x0208, 24, 0, 0, 0, 0x0208),
|
||||
PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0214, 0x0220, 0,
|
||||
PLL_AO, 0, 22, 0x0218, 24, 0, 0, 0, 0x0218),
|
||||
PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0224, 0x0230, 0,
|
||||
PLL_AO, 0, 22, 0x0228, 24, 0, 0, 0, 0x0228),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0244, 0x0250, 0xff000000,
|
||||
HAVE_RST_BAR, BIT(23), 22, 0x0248, 24, 0, 0, 0, 0x0248),
|
||||
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0324, 0x0330, 0xff000000,
|
||||
HAVE_RST_BAR, BIT(23), 22, 0x0328, 24, 0, 0, 0, 0x0328),
|
||||
PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x038C, 0x0398, 0,
|
||||
0, 0, 22, 0x0390, 24, 0, 0, 0, 0x0390),
|
||||
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0254, 0x0260, 0,
|
||||
0, 0, 22, 0x0258, 24, 0, 0, 0, 0x0258),
|
||||
PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x035C, 0x0368, 0,
|
||||
0, 0, 22, 0x0360, 24, 0, 0, 0, 0x0360),
|
||||
PLL(CLK_APMIXED_NNA2PLL, "nna2pll", 0x036C, 0x0378, 0,
|
||||
0, 0, 22, 0x0370, 24, 0, 0, 0, 0x0370),
|
||||
PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x0304, 0x0310, 0,
|
||||
0, 0, 22, 0x0308, 24, 0, 0, 0, 0x0308),
|
||||
PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0314, 0x0320, 0,
|
||||
0, 0, 22, 0x0318, 24, 0, 0, 0, 0x0318),
|
||||
PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0264, 0x0270, 0,
|
||||
0, 0, 22, 0x0268, 24, 0, 0, 0, 0x0268),
|
||||
PLL(CLK_APMIXED_APLL1, "apll1", 0x0334, 0x0344, 0,
|
||||
0, 0, 32, 0x0338, 24, 0x0040, 0x000C, 0, 0x033C),
|
||||
PLL(CLK_APMIXED_APLL2, "apll2", 0x0348, 0x0358, 0,
|
||||
0, 0, 32, 0x034C, 24, 0x0044, 0x000C, 5, 0x0350),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8186_apmixed[] = {
|
||||
{ .compatible = "mediatek,mt8186-apmixedsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
|
||||
if (r)
|
||||
goto free_apmixed_data;
|
||||
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
goto unregister_plls;
|
||||
|
||||
platform_set_drvdata(pdev, clk_data);
|
||||
|
||||
return r;
|
||||
|
||||
unregister_plls:
|
||||
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
|
||||
free_apmixed_data:
|
||||
mtk_free_clk_data(clk_data);
|
||||
return r;
|
||||
}
|
||||
|
||||
static int clk_mt8186_apmixed_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
|
||||
|
||||
of_clk_del_provider(node);
|
||||
mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
|
||||
mtk_free_clk_data(clk_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt8186_apmixed_drv = {
|
||||
.probe = clk_mt8186_apmixed_probe,
|
||||
.remove = clk_mt8186_apmixed_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt8186-apmixed",
|
||||
.of_match_table = of_match_clk_mt8186_apmixed,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(clk_mt8186_apmixed_drv);
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// Copyright (c) 2022 MediaTek Inc.
|
||||
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/clock/mt8186-clk.h>
|
||||
|
||||
#include "clk-gate.h"
|
||||
#include "clk-mtk.h"
|
||||
|
||||
static const struct mtk_gate_regs cam_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_CAM(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
static const struct mtk_gate cam_clks[] = {
|
||||
GATE_CAM(CLK_CAM_LARB13, "cam_larb13", "top_cam", 0),
|
||||
GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "top_cam", 1),
|
||||
GATE_CAM(CLK_CAM_LARB14, "cam_larb14", "top_cam", 2),
|
||||
GATE_CAM(CLK_CAM, "cam", "top_cam", 6),
|
||||
GATE_CAM(CLK_CAMTG, "camtg", "top_cam", 7),
|
||||
GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "top_cam", 8),
|
||||
GATE_CAM(CLK_CAMSV1, "camsv1", "top_cam", 10),
|
||||
GATE_CAM(CLK_CAMSV2, "camsv2", "top_cam", 11),
|
||||
GATE_CAM(CLK_CAMSV3, "camsv3", "top_cam", 12),
|
||||
GATE_CAM(CLK_CAM_CCU0, "cam_ccu0", "top_cam", 13),
|
||||
GATE_CAM(CLK_CAM_CCU1, "cam_ccu1", "top_cam", 14),
|
||||
GATE_CAM(CLK_CAM_MRAW0, "cam_mraw0", "top_cam", 15),
|
||||
GATE_CAM(CLK_CAM_FAKE_ENG, "cam_fake_eng", "top_cam", 17),
|
||||
GATE_CAM(CLK_CAM_CCU_GALS, "cam_ccu_gals", "top_cam", 18),
|
||||
GATE_CAM(CLK_CAM2MM_GALS, "cam2mm_gals", "top_cam", 19),
|
||||
};
|
||||
|
||||
static const struct mtk_gate cam_rawa_clks[] = {
|
||||
GATE_CAM(CLK_CAM_RAWA_LARBX_RAWA, "cam_rawa_larbx_rawa", "top_cam", 0),
|
||||
GATE_CAM(CLK_CAM_RAWA, "cam_rawa", "top_cam", 1),
|
||||
GATE_CAM(CLK_CAM_RAWA_CAMTG_RAWA, "cam_rawa_camtg_rawa", "top_cam", 2),
|
||||
};
|
||||
|
||||
static const struct mtk_gate cam_rawb_clks[] = {
|
||||
GATE_CAM(CLK_CAM_RAWB_LARBX_RAWB, "cam_rawb_larbx_rawb", "top_cam", 0),
|
||||
GATE_CAM(CLK_CAM_RAWB, "cam_rawb", "top_cam", 1),
|
||||
GATE_CAM(CLK_CAM_RAWB_CAMTG_RAWB, "cam_rawb_camtg_rawb", "top_cam", 2),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc cam_desc = {
|
||||
.clks = cam_clks,
|
||||
.num_clks = ARRAY_SIZE(cam_clks),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc cam_rawa_desc = {
|
||||
.clks = cam_rawa_clks,
|
||||
.num_clks = ARRAY_SIZE(cam_rawa_clks),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc cam_rawb_desc = {
|
||||
.clks = cam_rawb_clks,
|
||||
.num_clks = ARRAY_SIZE(cam_rawb_clks),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8186_cam[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8186-camsys",
|
||||
.data = &cam_desc,
|
||||
}, {
|
||||
.compatible = "mediatek,mt8186-camsys_rawa",
|
||||
.data = &cam_rawa_desc,
|
||||
}, {
|
||||
.compatible = "mediatek,mt8186-camsys_rawb",
|
||||
.data = &cam_rawb_desc,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt8186_cam_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt8186-cam",
|
||||
.of_match_table = of_match_clk_mt8186_cam,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(clk_mt8186_cam_drv);
|
||||
|
|
@ -0,0 +1,68 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// Copyright (c) 2022 MediaTek Inc.
|
||||
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/clock/mt8186-clk.h>
|
||||
|
||||
#include "clk-gate.h"
|
||||
#include "clk-mtk.h"
|
||||
|
||||
static const struct mtk_gate_regs img_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_IMG(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &img_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
static const struct mtk_gate img1_clks[] = {
|
||||
GATE_IMG(CLK_IMG1_LARB9_IMG1, "img1_larb9_img1", "top_img1", 0),
|
||||
GATE_IMG(CLK_IMG1_LARB10_IMG1, "img1_larb10_img1", "top_img1", 1),
|
||||
GATE_IMG(CLK_IMG1_DIP, "img1_dip", "top_img1", 2),
|
||||
GATE_IMG(CLK_IMG1_GALS_IMG1, "img1_gals_img1", "top_img1", 12),
|
||||
};
|
||||
|
||||
static const struct mtk_gate img2_clks[] = {
|
||||
GATE_IMG(CLK_IMG2_LARB9_IMG2, "img2_larb9_img2", "top_img1", 0),
|
||||
GATE_IMG(CLK_IMG2_LARB10_IMG2, "img2_larb10_img2", "top_img1", 1),
|
||||
GATE_IMG(CLK_IMG2_MFB, "img2_mfb", "top_img1", 6),
|
||||
GATE_IMG(CLK_IMG2_WPE, "img2_wpe", "top_img1", 7),
|
||||
GATE_IMG(CLK_IMG2_MSS, "img2_mss", "top_img1", 8),
|
||||
GATE_IMG(CLK_IMG2_GALS_IMG2, "img2_gals_img2", "top_img1", 12),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc img1_desc = {
|
||||
.clks = img1_clks,
|
||||
.num_clks = ARRAY_SIZE(img1_clks),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc img2_desc = {
|
||||
.clks = img2_clks,
|
||||
.num_clks = ARRAY_SIZE(img2_clks),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8186_img[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8186-imgsys1",
|
||||
.data = &img1_desc,
|
||||
}, {
|
||||
.compatible = "mediatek,mt8186-imgsys2",
|
||||
.data = &img2_desc,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt8186_img_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt8186-img",
|
||||
.of_match_table = of_match_clk_mt8186_img,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(clk_mt8186_img_drv);
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// Copyright (c) 2022 MediaTek Inc.
|
||||
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/clock/mt8186-clk.h>
|
||||
|
||||
#include "clk-gate.h"
|
||||
#include "clk-mtk.h"
|
||||
|
||||
static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
|
||||
.set_ofs = 0xe08,
|
||||
.clr_ofs = 0xe04,
|
||||
.sta_ofs = 0xe00,
|
||||
};
|
||||
|
||||
#define GATE_IMP_IIC_WRAP(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &imp_iic_wrap_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
static const struct mtk_gate imp_iic_wrap_clks[] = {
|
||||
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0,
|
||||
"imp_iic_wrap_ap_clock_i2c0", "infra_ao_i2c_ap", 0),
|
||||
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1,
|
||||
"imp_iic_wrap_ap_clock_i2c1", "infra_ao_i2c_ap", 1),
|
||||
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2,
|
||||
"imp_iic_wrap_ap_clock_i2c2", "infra_ao_i2c_ap", 2),
|
||||
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3,
|
||||
"imp_iic_wrap_ap_clock_i2c3", "infra_ao_i2c_ap", 3),
|
||||
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4,
|
||||
"imp_iic_wrap_ap_clock_i2c4", "infra_ao_i2c_ap", 4),
|
||||
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5,
|
||||
"imp_iic_wrap_ap_clock_i2c5", "infra_ao_i2c_ap", 5),
|
||||
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6,
|
||||
"imp_iic_wrap_ap_clock_i2c6", "infra_ao_i2c_ap", 6),
|
||||
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7,
|
||||
"imp_iic_wrap_ap_clock_i2c7", "infra_ao_i2c_ap", 7),
|
||||
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8,
|
||||
"imp_iic_wrap_ap_clock_i2c8", "infra_ao_i2c_ap", 8),
|
||||
GATE_IMP_IIC_WRAP(CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9,
|
||||
"imp_iic_wrap_ap_clock_i2c9", "infra_ao_i2c_ap", 9),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc imp_iic_wrap_desc = {
|
||||
.clks = imp_iic_wrap_clks,
|
||||
.num_clks = ARRAY_SIZE(imp_iic_wrap_clks),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8186_imp_iic_wrap[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8186-imp_iic_wrap",
|
||||
.data = &imp_iic_wrap_desc,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt8186_imp_iic_wrap_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt8186-imp_iic_wrap",
|
||||
.of_match_table = of_match_clk_mt8186_imp_iic_wrap,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(clk_mt8186_imp_iic_wrap_drv);
|
||||
|
|
@ -0,0 +1,216 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// Copyright (c) 2022 MediaTek Inc.
|
||||
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/clock/mt8186-clk.h>
|
||||
|
||||
#include "clk-gate.h"
|
||||
#include "clk-mtk.h"
|
||||
|
||||
static const struct mtk_gate_regs infra_ao0_cg_regs = {
|
||||
.set_ofs = 0x80,
|
||||
.clr_ofs = 0x84,
|
||||
.sta_ofs = 0x90,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs infra_ao1_cg_regs = {
|
||||
.set_ofs = 0x88,
|
||||
.clr_ofs = 0x8c,
|
||||
.sta_ofs = 0x94,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs infra_ao2_cg_regs = {
|
||||
.set_ofs = 0xa4,
|
||||
.clr_ofs = 0xa8,
|
||||
.sta_ofs = 0xac,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs infra_ao3_cg_regs = {
|
||||
.set_ofs = 0xc0,
|
||||
.clr_ofs = 0xc4,
|
||||
.sta_ofs = 0xc8,
|
||||
};
|
||||
|
||||
#define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \
|
||||
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
|
||||
&mtk_clk_gate_ops_setclr, _flag)
|
||||
|
||||
#define GATE_INFRA_AO0(_id, _name, _parent, _shift) \
|
||||
GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
|
||||
|
||||
#define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \
|
||||
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
|
||||
&mtk_clk_gate_ops_setclr, _flag)
|
||||
|
||||
#define GATE_INFRA_AO1(_id, _name, _parent, _shift) \
|
||||
GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
|
||||
|
||||
#define GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, _flag) \
|
||||
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao2_cg_regs, _shift, \
|
||||
&mtk_clk_gate_ops_setclr, _flag)
|
||||
|
||||
#define GATE_INFRA_AO2(_id, _name, _parent, _shift) \
|
||||
GATE_INFRA_AO2_FLAGS(_id, _name, _parent, _shift, 0)
|
||||
|
||||
#define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \
|
||||
GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao3_cg_regs, _shift, \
|
||||
&mtk_clk_gate_ops_setclr, _flag)
|
||||
|
||||
#define GATE_INFRA_AO3(_id, _name, _parent, _shift) \
|
||||
GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
|
||||
|
||||
static const struct mtk_gate infra_ao_clks[] = {
|
||||
/* INFRA_AO0 */
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_TMR, "infra_ao_pmic_tmr", "top_pwrap_ulposc", 0),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_AP, "infra_ao_pmic_ap", "top_pwrap_ulposc", 1),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_MD, "infra_ao_pmic_md", "top_pwrap_ulposc", 2),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_PMIC_CONN, "infra_ao_pmic_conn", "top_pwrap_ulposc", 3),
|
||||
/* infra_ao_scp_core are main clock in always-on co-processor. */
|
||||
GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SCP_CORE,
|
||||
"infra_ao_scp_core", "top_scp", 4, CLK_IS_CRITICAL),
|
||||
/* infra_ao_sej is main clock for secure engine with JTAG support */
|
||||
GATE_INFRA_AO0_FLAGS(CLK_INFRA_AO_SEJ,
|
||||
"infra_ao_sej", "top_axi", 5, CLK_IS_CRITICAL),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_APXGPT, "infra_ao_apxgpt", "top_axi", 6),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_ICUSB, "infra_ao_icusb", "top_axi", 8),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_GCE, "infra_ao_gce", "top_axi", 9),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_THERM, "infra_ao_therm", "top_axi", 10),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_I2C_AP, "infra_ao_i2c_ap", "top_i2c", 11),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_I2C_CCU, "infra_ao_i2c_ccu", "top_i2c", 12),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_I2C_SSPM, "infra_ao_i2c_sspm", "top_i2c", 13),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_I2C_RSV, "infra_ao_i2c_rsv", "top_i2c", 14),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_PWM_HCLK, "infra_ao_pwm_hclk", "top_axi", 15),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_PWM1, "infra_ao_pwm1", "top_pwm", 16),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_PWM2, "infra_ao_pwm2", "top_pwm", 17),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_PWM3, "infra_ao_pwm3", "top_pwm", 18),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_PWM4, "infra_ao_pwm4", "top_pwm", 19),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_PWM5, "infra_ao_pwm5", "top_pwm", 20),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_PWM, "infra_ao_pwm", "top_pwm", 21),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_UART0, "infra_ao_uart0", "top_uart", 22),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_UART1, "infra_ao_uart1", "top_uart", 23),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_UART2, "infra_ao_uart2", "top_uart", 24),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_GCE_26M, "infra_ao_gce_26m", "clk26m", 27),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_CQ_DMA_FPC, "infra_ao_dma", "top_axi", 28),
|
||||
GATE_INFRA_AO0(CLK_INFRA_AO_BTIF, "infra_ao_btif", "top_axi", 31),
|
||||
/* INFRA_AO1 */
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "top_spi", 1),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC0, "infra_ao_msdc0", "top_msdc5hclk", 2),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_MSDCFDE, "infra_ao_msdcfde", "top_aes_msdcfde", 3),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_MSDC1, "infra_ao_msdc1", "top_axi", 4),
|
||||
/* infra_ao_dvfsrc is for internal DVFS usage, should not be handled by Linux */
|
||||
GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DVFSRC,
|
||||
"infra_ao_dvfsrc", "top_dvfsrc", 7, CLK_IS_CRITICAL),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_GCPU, "infra_ao_gcpu", "top_axi", 8),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_TRNG, "infra_ao_trng", "top_axi", 9),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC, "infra_ao_auxadc", "clk26m", 10),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_CPUM, "infra_ao_cpum", "top_axi", 11),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_CCIF1_AP, "infra_ao_ccif1_ap", "top_axi", 12),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_CCIF1_MD, "infra_ao_ccif1_md", "top_axi", 13),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_AUXADC_MD, "infra_ao_auxadc_md", "clk26m", 14),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_AP_DMA, "infra_ao_ap_dma", "top_axi", 18),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_XIU, "infra_ao_xiu", "top_axi", 19),
|
||||
/* infra_ao_device_apc is for device access permission control module */
|
||||
GATE_INFRA_AO1_FLAGS(CLK_INFRA_AO_DEVICE_APC,
|
||||
"infra_ao_dapc", "top_axi", 20, CLK_IS_CRITICAL),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_CCIF_AP, "infra_ao_ccif_ap", "top_axi", 23),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_DEBUGTOP, "infra_ao_debugtop", "top_axi", 24),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_AUDIO, "infra_ao_audio", "top_axi", 25),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_CCIF_MD, "infra_ao_ccif_md", "top_axi", 26),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_DXCC_SEC_CORE, "infra_ao_secore", "top_dxcc", 27),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_DXCC_AO, "infra_ao_dxcc_ao", "top_dxcc", 28),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_IMP_IIC, "infra_ao_imp_iic", "top_axi", 29),
|
||||
GATE_INFRA_AO1(CLK_INFRA_AO_DRAMC_F26M, "infra_ao_dramc26", "clk26m", 31),
|
||||
/* INFRA_AO2 */
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_RG_PWM_FBCLK6, "infra_ao_pwm_fbclk6", "clk26m", 0),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_HCLK, "infra_ao_ssusb_hclk", "top_axi", 1),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_DISP_PWM, "infra_ao_disp_pwm", "top_disp_pwm", 2),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_CLDMA_BCLK, "infra_ao_cldmabclk", "top_axi", 3),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_AUDIO_26M_BCLK, "infra_ao_audio26m", "clk26m", 4),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_HCLK, "infra_ao_ssusb_p1_hclk", "top_axi", 5),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "top_spi", 6),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_I2C4, "infra_ao_i2c4", "top_i2c", 7),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_MODEM_TEMP_SHARE, "infra_ao_mdtemp", "clk26m", 8),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_SPI2, "infra_ao_spi2", "top_spi", 9),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_SPI3, "infra_ao_spi3", "top_spi", 10),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_REF, "infra_ao_ssusb_ref", "clk26m", 11),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_XHCI, "infra_ao_ssusb_xhci", "top_ssusb_xhci", 12),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_REF, "infra_ao_ssusb_p1_ref", "clk26m", 13),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_XHCI,
|
||||
"infra_ao_ssusb_p1_xhci", "top_ssusb_xhci_1p", 14),
|
||||
/* infra_ao_sspm is main clock in co-processor, should not be closed in Linux. */
|
||||
GATE_INFRA_AO2_FLAGS(CLK_INFRA_AO_SSPM, "infra_ao_sspm", "top_sspm", 15, CLK_IS_CRITICAL),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_SSUSB_TOP_P1_SYS,
|
||||
"infra_ao_ssusb_p1_sys", "top_ssusb_1p", 16),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_I2C5, "infra_ao_i2c5", "top_i2c", 18),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_I2C5_ARBITER, "infra_ao_i2c5a", "top_i2c", 19),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_I2C5_IMM, "infra_ao_i2c5_imm", "top_i2c", 20),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_I2C1_ARBITER, "infra_ao_i2c1a", "top_i2c", 21),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_I2C1_IMM, "infra_ao_i2c1_imm", "top_i2c", 22),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_I2C2_ARBITER, "infra_ao_i2c2a", "top_i2c", 23),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_I2C2_IMM, "infra_ao_i2c2_imm", "top_i2c", 24),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_SPI4, "infra_ao_spi4", "top_spi", 25),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_SPI5, "infra_ao_spi5", "top_spi", 26),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_CQ_DMA, "infra_ao_cq_dma", "top_axi", 27),
|
||||
GATE_INFRA_AO2(CLK_INFRA_AO_BIST2FPC, "infra_ao_bist2fpc", "f_bist2fpc_ck", 28),
|
||||
/* INFRA_AO3 */
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SELF, "infra_ao_msdc0sf", "top_msdc50_0", 0),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_SPINOR, "infra_ao_spinor", "top_spinor", 1),
|
||||
/*
|
||||
* infra_ao_sspm_26m/infra_ao_sspm_32k are main clocks in co-processor,
|
||||
* should not be closed in Linux.
|
||||
*/
|
||||
GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_SSPM_26M_SELF, "infra_ao_sspm_26m", "clk26m", 3,
|
||||
CLK_IS_CRITICAL),
|
||||
GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_SSPM_32K_SELF, "infra_ao_sspm_32k", "clk32k", 4,
|
||||
CLK_IS_CRITICAL),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_I2C6, "infra_ao_i2c6", "top_i2c", 6),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_AP_MSDC0, "infra_ao_ap_msdc0", "top_axi", 7),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_MD_MSDC0, "infra_ao_md_msdc0", "top_axi", 8),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC0_SRC, "infra_ao_msdc0_clk", "top_msdc50_0", 9),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_MSDC1_SRC, "infra_ao_msdc1_clk", "top_msdc30_1", 10),
|
||||
/* infra_ao_sej_f13m is main clock for secure engine with JTAG support */
|
||||
GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_SEJ_F13M,
|
||||
"infra_ao_sej_f13m", "clk26m", 15, CLK_IS_CRITICAL),
|
||||
/* infra_ao_aes_top0_bclk is for secure encryption */
|
||||
GATE_INFRA_AO3_FLAGS(CLK_INFRA_AO_AES_TOP0_BCLK,
|
||||
"infra_ao_aes_top0_bclk", "top_axi", 16, CLK_IS_CRITICAL),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_MCU_PM_BCLK, "infra_ao_mcu_pm_bclk", "top_axi", 17),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_CCIF2_AP, "infra_ao_ccif2_ap", "top_axi", 18),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_CCIF2_MD, "infra_ao_ccif2_md", "top_axi", 19),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_CCIF3_AP, "infra_ao_ccif3_ap", "top_axi", 20),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_CCIF3_MD, "infra_ao_ccif3_md", "top_axi", 21),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_FADSP_26M, "infra_ao_fadsp_26m", "clk26m", 22),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_FADSP_32K, "infra_ao_fadsp_32k", "clk32k", 23),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_CCIF4_AP, "infra_ao_ccif4_ap", "top_axi", 24),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_CCIF4_MD, "infra_ao_ccif4_md", "top_axi", 25),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_FADSP, "infra_ao_fadsp", "top_audiodsp", 27),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_FLASHIF_133M, "infra_ao_flashif_133m", "top_axi", 28),
|
||||
GATE_INFRA_AO3(CLK_INFRA_AO_FLASHIF_66M, "infra_ao_flashif_66m", "top_axi", 29),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc infra_ao_desc = {
|
||||
.clks = infra_ao_clks,
|
||||
.num_clks = ARRAY_SIZE(infra_ao_clks),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8186_infra_ao[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8186-infracfg_ao",
|
||||
.data = &infra_ao_desc,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt8186_infra_ao_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt8186-infra-ao",
|
||||
.of_match_table = of_match_clk_mt8186_infra_ao,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(clk_mt8186_infra_ao_drv);
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// Copyright (c) 2022 MediaTek Inc.
|
||||
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/clock/mt8186-clk.h>
|
||||
|
||||
#include "clk-gate.h"
|
||||
#include "clk-mtk.h"
|
||||
|
||||
static const struct mtk_gate_regs ipe_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_IPE(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &ipe_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
static const struct mtk_gate ipe_clks[] = {
|
||||
GATE_IPE(CLK_IPE_LARB19, "ipe_larb19", "top_ipe", 0),
|
||||
GATE_IPE(CLK_IPE_LARB20, "ipe_larb20", "top_ipe", 1),
|
||||
GATE_IPE(CLK_IPE_SMI_SUBCOM, "ipe_smi_subcom", "top_ipe", 2),
|
||||
GATE_IPE(CLK_IPE_FD, "ipe_fd", "top_ipe", 3),
|
||||
GATE_IPE(CLK_IPE_FE, "ipe_fe", "top_ipe", 4),
|
||||
GATE_IPE(CLK_IPE_RSC, "ipe_rsc", "top_ipe", 5),
|
||||
GATE_IPE(CLK_IPE_DPE, "ipe_dpe", "top_ipe", 6),
|
||||
GATE_IPE(CLK_IPE_GALS_IPE, "ipe_gals_ipe", "top_img1", 8),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc ipe_desc = {
|
||||
.clks = ipe_clks,
|
||||
.num_clks = ARRAY_SIZE(ipe_clks),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8186_ipe[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8186-ipesys",
|
||||
.data = &ipe_desc,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt8186_ipe_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt8186-ipe",
|
||||
.of_match_table = of_match_clk_mt8186_ipe,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(clk_mt8186_ipe_drv);
|
||||
|
|
@ -0,0 +1,108 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// Copyright (c) 2022 MediaTek Inc.
|
||||
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/clock/mt8186-clk.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
|
||||
static const char * const mcu_armpll_ll_parents[] = {
|
||||
"clk26m",
|
||||
"armpll_ll",
|
||||
"mainpll",
|
||||
"univpll_d2"
|
||||
};
|
||||
|
||||
static const char * const mcu_armpll_bl_parents[] = {
|
||||
"clk26m",
|
||||
"armpll_bl",
|
||||
"mainpll",
|
||||
"univpll_d2"
|
||||
};
|
||||
|
||||
static const char * const mcu_armpll_bus_parents[] = {
|
||||
"clk26m",
|
||||
"ccipll",
|
||||
"mainpll",
|
||||
"univpll_d2"
|
||||
};
|
||||
|
||||
/*
|
||||
* We only configure the CPU muxes when adjust CPU frequency in MediaTek CPUFreq Driver.
|
||||
* Other fields like divider always keep the same value. (set once in bootloader)
|
||||
*/
|
||||
static struct mtk_composite mcu_muxes[] = {
|
||||
/* CPU_PLLDIV_CFG0 */
|
||||
MUX(CLK_MCU_ARMPLL_LL_SEL, "mcu_armpll_ll_sel", mcu_armpll_ll_parents, 0x2A0, 9, 2),
|
||||
/* CPU_PLLDIV_CFG1 */
|
||||
MUX(CLK_MCU_ARMPLL_BL_SEL, "mcu_armpll_bl_sel", mcu_armpll_bl_parents, 0x2A4, 9, 2),
|
||||
/* BUS_PLLDIV_CFG */
|
||||
MUX(CLK_MCU_ARMPLL_BUS_SEL, "mcu_armpll_bus_sel", mcu_armpll_bus_parents, 0x2E0, 9, 2),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8186_mcu[] = {
|
||||
{ .compatible = "mediatek,mt8186-mcusys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static int clk_mt8186_mcu_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
void __iomem *base;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base)) {
|
||||
r = PTR_ERR(base);
|
||||
goto free_mcu_data;
|
||||
}
|
||||
|
||||
r = mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
|
||||
NULL, clk_data);
|
||||
if (r)
|
||||
goto free_mcu_data;
|
||||
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
goto unregister_composite_muxes;
|
||||
|
||||
platform_set_drvdata(pdev, clk_data);
|
||||
|
||||
return r;
|
||||
|
||||
unregister_composite_muxes:
|
||||
mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), clk_data);
|
||||
free_mcu_data:
|
||||
mtk_free_clk_data(clk_data);
|
||||
return r;
|
||||
}
|
||||
|
||||
static int clk_mt8186_mcu_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
of_clk_del_provider(node);
|
||||
mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), clk_data);
|
||||
mtk_free_clk_data(clk_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt8186_mcu_drv = {
|
||||
.probe = clk_mt8186_mcu_probe,
|
||||
.remove = clk_mt8186_mcu_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt8186-mcu",
|
||||
.of_match_table = of_match_clk_mt8186_mcu,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(clk_mt8186_mcu_drv);
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// Copyright (c) 2022 MediaTek Inc.
|
||||
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/clock/mt8186-clk.h>
|
||||
|
||||
#include "clk-gate.h"
|
||||
#include "clk-mtk.h"
|
||||
|
||||
static const struct mtk_gate_regs mdp0_cg_regs = {
|
||||
.set_ofs = 0x104,
|
||||
.clr_ofs = 0x108,
|
||||
.sta_ofs = 0x100,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs mdp2_cg_regs = {
|
||||
.set_ofs = 0x124,
|
||||
.clr_ofs = 0x128,
|
||||
.sta_ofs = 0x120,
|
||||
};
|
||||
|
||||
#define GATE_MDP0(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &mdp0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
#define GATE_MDP2(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &mdp2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
static const struct mtk_gate mdp_clks[] = {
|
||||
/* MDP0 */
|
||||
GATE_MDP0(CLK_MDP_RDMA0, "mdp_rdma0", "top_mdp", 0),
|
||||
GATE_MDP0(CLK_MDP_TDSHP0, "mdp_tdshp0", "top_mdp", 1),
|
||||
GATE_MDP0(CLK_MDP_IMG_DL_ASYNC0, "mdp_img_dl_async0", "top_mdp", 2),
|
||||
GATE_MDP0(CLK_MDP_IMG_DL_ASYNC1, "mdp_img_dl_async1", "top_mdp", 3),
|
||||
GATE_MDP0(CLK_MDP_DISP_RDMA, "mdp_disp_rdma", "top_mdp", 4),
|
||||
GATE_MDP0(CLK_MDP_HMS, "mdp_hms", "top_mdp", 5),
|
||||
GATE_MDP0(CLK_MDP_SMI0, "mdp_smi0", "top_mdp", 6),
|
||||
GATE_MDP0(CLK_MDP_APB_BUS, "mdp_apb_bus", "top_mdp", 7),
|
||||
GATE_MDP0(CLK_MDP_WROT0, "mdp_wrot0", "top_mdp", 8),
|
||||
GATE_MDP0(CLK_MDP_RSZ0, "mdp_rsz0", "top_mdp", 9),
|
||||
GATE_MDP0(CLK_MDP_HDR0, "mdp_hdr0", "top_mdp", 10),
|
||||
GATE_MDP0(CLK_MDP_MUTEX0, "mdp_mutex0", "top_mdp", 11),
|
||||
GATE_MDP0(CLK_MDP_WROT1, "mdp_wrot1", "top_mdp", 12),
|
||||
GATE_MDP0(CLK_MDP_RSZ1, "mdp_rsz1", "top_mdp", 13),
|
||||
GATE_MDP0(CLK_MDP_FAKE_ENG0, "mdp_fake_eng0", "top_mdp", 14),
|
||||
GATE_MDP0(CLK_MDP_AAL0, "mdp_aal0", "top_mdp", 15),
|
||||
GATE_MDP0(CLK_MDP_DISP_WDMA, "mdp_disp_wdma", "top_mdp", 16),
|
||||
GATE_MDP0(CLK_MDP_COLOR, "mdp_color", "top_mdp", 17),
|
||||
GATE_MDP0(CLK_MDP_IMG_DL_ASYNC2, "mdp_img_dl_async2", "top_mdp", 18),
|
||||
/* MDP2 */
|
||||
GATE_MDP2(CLK_MDP_IMG_DL_RELAY0_ASYNC0, "mdp_img_dl_rel0_as0", "top_mdp", 0),
|
||||
GATE_MDP2(CLK_MDP_IMG_DL_RELAY1_ASYNC1, "mdp_img_dl_rel1_as1", "top_mdp", 8),
|
||||
GATE_MDP2(CLK_MDP_IMG_DL_RELAY2_ASYNC2, "mdp_img_dl_rel2_as2", "top_mdp", 24),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc mdp_desc = {
|
||||
.clks = mdp_clks,
|
||||
.num_clks = ARRAY_SIZE(mdp_clks),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8186_mdp[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8186-mdpsys",
|
||||
.data = &mdp_desc,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt8186_mdp_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt8186-mdp",
|
||||
.of_match_table = of_match_clk_mt8186_mdp,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(clk_mt8186_mdp_drv);
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// Copyright (c) 2022 MediaTek Inc.
|
||||
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/clock/mt8186-clk.h>
|
||||
|
||||
#include "clk-gate.h"
|
||||
#include "clk-mtk.h"
|
||||
|
||||
static const struct mtk_gate_regs mfg_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_MFG(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
static const struct mtk_gate mfg_clks[] = {
|
||||
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "top_mfg", 0),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_desc mfg_desc = {
|
||||
.clks = mfg_clks,
|
||||
.num_clks = ARRAY_SIZE(mfg_clks),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8186_mfg[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt8186-mfgsys",
|
||||
.data = &mfg_desc,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt8186_mfg_drv = {
|
||||
.probe = mtk_clk_simple_probe,
|
||||
.remove = mtk_clk_simple_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt8186-mfg",
|
||||
.of_match_table = of_match_clk_mt8186_mfg,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(clk_mt8186_mfg_drv);
|
||||
|
|
@ -0,0 +1,111 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// Copyright (c) 2022 MediaTek Inc.
|
||||
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/clock/mt8186-clk.h>
|
||||
|
||||
#include "clk-gate.h"
|
||||
#include "clk-mtk.h"
|
||||
|
||||
static const struct mtk_gate_regs mm0_cg_regs = {
|
||||
.set_ofs = 0x104,
|
||||
.clr_ofs = 0x108,
|
||||
.sta_ofs = 0x100,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs mm1_cg_regs = {
|
||||
.set_ofs = 0x1a4,
|
||||
.clr_ofs = 0x1a8,
|
||||
.sta_ofs = 0x1a0,
|
||||
};
|
||||
|
||||
#define GATE_MM0(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
#define GATE_MM1(_id, _name, _parent, _shift) \
|
||||
GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
|
||||
|
||||
static const struct mtk_gate mm_clks[] = {
|
||||
/* MM0 */
|
||||
GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "top_disp", 0),
|
||||
GATE_MM0(CLK_MM_APB_MM_BUS, "mm_apb_mm_bus", "top_disp", 1),
|
||||
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "top_disp", 2),
|
||||
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "top_disp", 3),
|
||||
GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "top_disp", 4),
|
||||
GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "top_disp", 5),
|
||||
GATE_MM0(CLK_MM_DISP_RSZ0, "mm_disp_rsz0", "top_disp", 7),
|
||||
GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "top_disp", 8),
|
||||
GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "top_disp", 9),
|
||||
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "top_disp", 10),
|
||||
GATE_MM0(CLK_MM_SMI_INFRA, "mm_smi_infra", "top_disp", 11),
|
||||
GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "top_disp", 12),
|
||||
GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "top_disp", 13),
|
||||
GATE_MM0(CLK_MM_DISP_POSTMASK0, "mm_disp_postmask0", "top_disp", 14),
|
||||
GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "top_disp", 16),
|
||||
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "top_disp", 17),
|
||||
GATE_MM0(CLK_MM_DSI0, "mm_dsi0", "top_disp", 19),
|
||||
GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "top_disp", 20),
|
||||
GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "top_disp", 21),
|
||||
GATE_MM0(CLK_MM_SMI_GALS, "mm_smi_gals", "top_disp", 22),
|
||||
GATE_MM0(CLK_MM_SMI_IOMMU, "mm_smi_iommu", "top_disp", 24),
|
||||
GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "top_disp", 25),
|
||||
GATE_MM0(CLK_MM_DISP_DPI, "mm_disp_dpi", "top_disp", 26),
|
||||
/* MM1 */
|
||||
GATE_MM1(CLK_MM_DSI0_DSI_CK_DOMAIN, "mm_dsi0_dsi_domain", "top_disp", 0),
|
||||
GATE_MM1(CLK_MM_DISP_26M, "mm_disp_26m_ck", "top_disp", 10),
|
||||
};
|
||||
|
||||
static int clk_mt8186_mm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->parent->of_node;
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
r = mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data);
|
||||
if (r)
|
||||
goto free_mm_data;
|
||||
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
goto unregister_gates;
|
||||
|
||||
platform_set_drvdata(pdev, clk_data);
|
||||
|
||||
return r;
|
||||
|
||||
unregister_gates:
|
||||
mtk_clk_unregister_gates(mm_clks, ARRAY_SIZE(mm_clks), clk_data);
|
||||
free_mm_data:
|
||||
mtk_free_clk_data(clk_data);
|
||||
return r;
|
||||
}
|
||||
|
||||
static int clk_mt8186_mm_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *node = dev->parent->of_node;
|
||||
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
|
||||
|
||||
of_clk_del_provider(node);
|
||||
mtk_clk_unregister_gates(mm_clks, ARRAY_SIZE(mm_clks), clk_data);
|
||||
mtk_free_clk_data(clk_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt8186_mm_drv = {
|
||||
.probe = clk_mt8186_mm_probe,
|
||||
.remove = clk_mt8186_mm_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt8186-mm",
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(clk_mt8186_mm_drv);
|
||||
|
|
@ -0,0 +1,780 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
//
|
||||
// Copyright (c) 2022 MediaTek Inc.
|
||||
// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <dt-bindings/clock/mt8186-clk.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-mux.h"
|
||||
|
||||
static DEFINE_SPINLOCK(mt8186_clk_lock);
|
||||
|
||||
static const struct mtk_fixed_clk top_fixed_clks[] = {
|
||||
FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc1", NULL, 250000000),
|
||||
FIXED_CLK(CLK_TOP_466M_FMEM, "hd_466m_fmem_ck", NULL, 466000000),
|
||||
FIXED_CLK(CLK_TOP_MPLL, "mpll", NULL, 208000000),
|
||||
};
|
||||
|
||||
static const struct mtk_fixed_factor top_divs[] = {
|
||||
FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16),
|
||||
FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
|
||||
FACTOR(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
|
||||
FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4),
|
||||
FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
|
||||
FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll_d7", 1, 2),
|
||||
FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll_d7", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2_D2, "univpll_d2_d2", "univpll_d2", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2_D4, "univpll_d2_d4", "univpll_d2", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D2, "univpll_d3_d2", "univpll_d3", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D4, "univpll_d3_d4", "univpll_d3", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D8, "univpll_d3_d8", "univpll_d3", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D3_D32, "univpll_d3_d32", "univpll_d3", 1, 32),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll_d5", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll_d5", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univ2pll", 1, 13),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll_192m", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll_192m", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll_192m", 1, 16),
|
||||
FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll_192m", 1, 32),
|
||||
FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
|
||||
FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
|
||||
FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
|
||||
FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
|
||||
FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
|
||||
FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
|
||||
FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
|
||||
FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
|
||||
FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
|
||||
FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll", 1, 8),
|
||||
FACTOR(CLK_TOP_TVDPLL_D16, "tvdpll_d16", "tvdpll", 1, 16),
|
||||
FACTOR(CLK_TOP_TVDPLL_D32, "tvdpll_d32", "tvdpll", 1, 32),
|
||||
FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
|
||||
FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1", 1, 2),
|
||||
FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1", 1, 4),
|
||||
FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1", 1, 8),
|
||||
FACTOR(CLK_TOP_ULPOSC1_D10, "ulposc1_d10", "ulposc1", 1, 10),
|
||||
FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1", 1, 16),
|
||||
FACTOR(CLK_TOP_ULPOSC1_D32, "ulposc1_d32", "ulposc1", 1, 32),
|
||||
FACTOR(CLK_TOP_ADSPPLL_D2, "adsppll_d2", "adsppll", 1, 2),
|
||||
FACTOR(CLK_TOP_ADSPPLL_D4, "adsppll_d4", "adsppll", 1, 4),
|
||||
FACTOR(CLK_TOP_ADSPPLL_D8, "adsppll_d8", "adsppll", 1, 8),
|
||||
FACTOR(CLK_TOP_NNAPLL_D2, "nnapll_d2", "nnapll", 1, 2),
|
||||
FACTOR(CLK_TOP_NNAPLL_D4, "nnapll_d4", "nnapll", 1, 4),
|
||||
FACTOR(CLK_TOP_NNAPLL_D8, "nnapll_d8", "nnapll", 1, 8),
|
||||
FACTOR(CLK_TOP_NNA2PLL_D2, "nna2pll_d2", "nna2pll", 1, 2),
|
||||
FACTOR(CLK_TOP_NNA2PLL_D4, "nna2pll_d4", "nna2pll", 1, 4),
|
||||
FACTOR(CLK_TOP_NNA2PLL_D8, "nna2pll_d8", "nna2pll", 1, 8),
|
||||
FACTOR(CLK_TOP_F_BIST2FPC, "f_bist2fpc_ck", "univpll_d3_d2", 1, 1),
|
||||
};
|
||||
|
||||
static const char * const axi_parents[] = {
|
||||
"clk26m",
|
||||
"mainpll_d7",
|
||||
"mainpll_d2_d4",
|
||||
"univpll_d7"
|
||||
};
|
||||
|
||||
static const char * const scp_parents[] = {
|
||||
"clk26m",
|
||||
"mainpll_d2_d4",
|
||||
"mainpll_d5",
|
||||
"mainpll_d2_d2",
|
||||
"mainpll_d3",
|
||||
"univpll_d3"
|
||||
};
|
||||
|
||||
static const char * const mfg_parents[] = {
|
||||
"clk26m",
|
||||
"mfgpll",
|
||||
"mainpll_d3",
|
||||
"mainpll_d5"
|
||||
};
|
||||
|
||||
static const char * const camtg_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_192m_d8",
|
||||
"univpll_d3_d8",
|
||||
"univpll_192m_d4",
|
||||
"univpll_d3_d32",
|
||||
"univpll_192m_d16",
|
||||
"univpll_192m_d32"
|
||||
};
|
||||
|
||||
static const char * const uart_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d3_d8"
|
||||
};
|
||||
|
||||
static const char * const spi_parents[] = {
|
||||
"clk26m",
|
||||
"mainpll_d5_d4",
|
||||
"mainpll_d3_d4",
|
||||
"mainpll_d5_d2",
|
||||
"mainpll_d2_d4",
|
||||
"mainpll_d7",
|
||||
"mainpll_d3_d2",
|
||||
"mainpll_d5"
|
||||
};
|
||||
|
||||
static const char * const msdc5hclk_parents[] = {
|
||||
"clk26m",
|
||||
"mainpll_d2_d2",
|
||||
"mainpll_d7",
|
||||
"mainpll_d3_d2"
|
||||
};
|
||||
|
||||
static const char * const msdc50_0_parents[] = {
|
||||
"clk26m",
|
||||
"msdcpll",
|
||||
"univpll_d3",
|
||||
"msdcpll_d2",
|
||||
"mainpll_d7",
|
||||
"mainpll_d3_d2",
|
||||
"univpll_d2_d2"
|
||||
};
|
||||
|
||||
static const char * const msdc30_1_parents[] = {
|
||||
"clk26m",
|
||||
"msdcpll_d2",
|
||||
"univpll_d3_d2",
|
||||
"mainpll_d3_d2",
|
||||
"mainpll_d7"
|
||||
};
|
||||
|
||||
static const char * const audio_parents[] = {
|
||||
"clk26m",
|
||||
"mainpll_d5_d4",
|
||||
"mainpll_d7_d4",
|
||||
"mainpll_d2_d16"
|
||||
};
|
||||
|
||||
static const char * const aud_intbus_parents[] = {
|
||||
"clk26m",
|
||||
"mainpll_d2_d4",
|
||||
"mainpll_d7_d2"
|
||||
};
|
||||
|
||||
static const char * const aud_1_parents[] = {
|
||||
"clk26m",
|
||||
"apll1"
|
||||
};
|
||||
|
||||
static const char * const aud_2_parents[] = {
|
||||
"clk26m",
|
||||
"apll2"
|
||||
};
|
||||
|
||||
static const char * const aud_engen1_parents[] = {
|
||||
"clk26m",
|
||||
"apll1_d2",
|
||||
"apll1_d4",
|
||||
"apll1_d8"
|
||||
};
|
||||
|
||||
static const char * const aud_engen2_parents[] = {
|
||||
"clk26m",
|
||||
"apll2_d2",
|
||||
"apll2_d4",
|
||||
"apll2_d8"
|
||||
};
|
||||
|
||||
static const char * const disp_pwm_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d5_d2",
|
||||
"univpll_d3_d4",
|
||||
"ulposc1_d2",
|
||||
"ulposc1_d8"
|
||||
};
|
||||
|
||||
static const char * const sspm_parents[] = {
|
||||
"clk26m",
|
||||
"mainpll_d2_d2",
|
||||
"mainpll_d3_d2",
|
||||
"mainpll_d5",
|
||||
"mainpll_d3"
|
||||
};
|
||||
|
||||
static const char * const dxcc_parents[] = {
|
||||
"clk26m",
|
||||
"mainpll_d2_d2",
|
||||
"mainpll_d2_d4"
|
||||
};
|
||||
|
||||
static const char * const usb_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d5_d4",
|
||||
"univpll_d5_d2"
|
||||
};
|
||||
|
||||
static const char * const srck_parents[] = {
|
||||
"clk32k",
|
||||
"clk26m",
|
||||
"ulposc1_d10"
|
||||
};
|
||||
|
||||
static const char * const spm_parents[] = {
|
||||
"clk32k",
|
||||
"ulposc1_d10",
|
||||
"clk26m",
|
||||
"mainpll_d7_d2"
|
||||
};
|
||||
|
||||
static const char * const i2c_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d5_d4",
|
||||
"univpll_d3_d4",
|
||||
"univpll_d5_d2"
|
||||
};
|
||||
|
||||
static const char * const pwm_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d3_d8",
|
||||
"univpll_d3_d4",
|
||||
"univpll_d2_d4"
|
||||
};
|
||||
|
||||
static const char * const seninf_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d2_d4",
|
||||
"univpll_d2_d2",
|
||||
"univpll_d3_d2"
|
||||
};
|
||||
|
||||
static const char * const aes_msdcfde_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d3",
|
||||
"mainpll_d3",
|
||||
"univpll_d2_d2",
|
||||
"mainpll_d2_d2",
|
||||
"mainpll_d2_d4"
|
||||
};
|
||||
|
||||
static const char * const pwrap_ulposc_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d5_d4",
|
||||
"ulposc1_d4",
|
||||
"ulposc1_d8",
|
||||
"ulposc1_d10",
|
||||
"ulposc1_d16",
|
||||
"ulposc1_d32"
|
||||
};
|
||||
|
||||
static const char * const camtm_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d2_d4",
|
||||
"univpll_d3_d2"
|
||||
};
|
||||
|
||||
static const char * const venc_parents[] = {
|
||||
"clk26m",
|
||||
"mmpll",
|
||||
"mainpll_d2_d2",
|
||||
"mainpll_d2",
|
||||
"univpll_d3",
|
||||
"univpll_d2_d2",
|
||||
"mainpll_d3",
|
||||
"mmpll"
|
||||
};
|
||||
|
||||
static const char * const isp_parents[] = {
|
||||
"clk26m",
|
||||
"mainpll_d2",
|
||||
"mainpll_d2_d2",
|
||||
"univpll_d3",
|
||||
"mainpll_d3",
|
||||
"mmpll",
|
||||
"univpll_d5",
|
||||
"univpll_d2_d2",
|
||||
"mmpll_d2"
|
||||
};
|
||||
|
||||
static const char * const dpmaif_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d2_d2",
|
||||
"mainpll_d3",
|
||||
"mainpll_d2_d2",
|
||||
"univpll_d3_d2"
|
||||
};
|
||||
|
||||
static const char * const vdec_parents[] = {
|
||||
"clk26m",
|
||||
"mainpll_d3",
|
||||
"mainpll_d2_d2",
|
||||
"univpll_d5",
|
||||
"mainpll_d2",
|
||||
"univpll_d3",
|
||||
"univpll_d2_d2"
|
||||
};
|
||||
|
||||
static const char * const disp_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d3_d2",
|
||||
"mainpll_d5",
|
||||
"univpll_d5",
|
||||
"univpll_d2_d2",
|
||||
"mainpll_d3",
|
||||
"univpll_d3",
|
||||
"mainpll_d2",
|
||||
"mmpll"
|
||||
};
|
||||
|
||||
static const char * const mdp_parents[] = {
|
||||
"clk26m",
|
||||
"mainpll_d5",
|
||||
"univpll_d5",
|
||||
"mainpll_d2_d2",
|
||||
"univpll_d2_d2",
|
||||
"mainpll_d3",
|
||||
"univpll_d3",
|
||||
"mainpll_d2",
|
||||
"mmpll"
|
||||
};
|
||||
|
||||
static const char * const audio_h_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d7",
|
||||
"apll1",
|
||||
"apll2"
|
||||
};
|
||||
|
||||
static const char * const ufs_parents[] = {
|
||||
"clk26m",
|
||||
"mainpll_d7",
|
||||
"univpll_d2_d4",
|
||||
"mainpll_d2_d4"
|
||||
};
|
||||
|
||||
static const char * const aes_fde_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d3",
|
||||
"mainpll_d2_d2",
|
||||
"univpll_d5"
|
||||
};
|
||||
|
||||
static const char * const audiodsp_parents[] = {
|
||||
"clk26m",
|
||||
"ulposc1_d10",
|
||||
"adsppll",
|
||||
"adsppll_d2",
|
||||
"adsppll_d4",
|
||||
"adsppll_d8"
|
||||
};
|
||||
|
||||
static const char * const dvfsrc_parents[] = {
|
||||
"clk26m",
|
||||
"ulposc1_d10",
|
||||
};
|
||||
|
||||
static const char * const dsi_occ_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d3_d2",
|
||||
"mpll",
|
||||
"mainpll_d5"
|
||||
};
|
||||
|
||||
static const char * const spmi_mst_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d5_d4",
|
||||
"ulposc1_d4",
|
||||
"ulposc1_d8",
|
||||
"ulposc1_d10",
|
||||
"ulposc1_d16",
|
||||
"ulposc1_d32"
|
||||
};
|
||||
|
||||
static const char * const spinor_parents[] = {
|
||||
"clk26m",
|
||||
"clk13m",
|
||||
"mainpll_d7_d4",
|
||||
"univpll_d3_d8",
|
||||
"univpll_d5_d4",
|
||||
"mainpll_d7_d2"
|
||||
};
|
||||
|
||||
static const char * const nna_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d3_d8",
|
||||
"mainpll_d2_d4",
|
||||
"univpll_d3_d2",
|
||||
"mainpll_d2_d2",
|
||||
"univpll_d2_d2",
|
||||
"mainpll_d3",
|
||||
"univpll_d3",
|
||||
"mmpll",
|
||||
"mainpll_d2",
|
||||
"univpll_d2",
|
||||
"nnapll_d2",
|
||||
"nnapll_d4",
|
||||
"nnapll_d8",
|
||||
"nnapll",
|
||||
"nna2pll"
|
||||
};
|
||||
|
||||
static const char * const nna2_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d3_d8",
|
||||
"mainpll_d2_d4",
|
||||
"univpll_d3_d2",
|
||||
"mainpll_d2_d2",
|
||||
"univpll_d2_d2",
|
||||
"mainpll_d3",
|
||||
"univpll_d3",
|
||||
"mmpll",
|
||||
"mainpll_d2",
|
||||
"univpll_d2",
|
||||
"nna2pll_d2",
|
||||
"nna2pll_d4",
|
||||
"nna2pll_d8",
|
||||
"nnapll",
|
||||
"nna2pll"
|
||||
};
|
||||
|
||||
static const char * const ssusb_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d5_d4",
|
||||
"univpll_d5_d2"
|
||||
};
|
||||
|
||||
static const char * const wpe_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d3_d2",
|
||||
"mainpll_d5",
|
||||
"univpll_d5",
|
||||
"univpll_d2_d2",
|
||||
"mainpll_d3",
|
||||
"univpll_d3",
|
||||
"mainpll_d2",
|
||||
"mmpll"
|
||||
};
|
||||
|
||||
static const char * const dpi_parents[] = {
|
||||
"clk26m",
|
||||
"tvdpll",
|
||||
"tvdpll_d2",
|
||||
"tvdpll_d4",
|
||||
"tvdpll_d8",
|
||||
"tvdpll_d16",
|
||||
"tvdpll_d32"
|
||||
};
|
||||
|
||||
static const char * const u3_occ_250m_parents[] = {
|
||||
"clk26m",
|
||||
"univpll_d5"
|
||||
};
|
||||
|
||||
static const char * const u3_occ_500m_parents[] = {
|
||||
"clk26m",
|
||||
"nna2pll_d2"
|
||||
};
|
||||
|
||||
static const char * const adsp_bus_parents[] = {
|
||||
"clk26m",
|
||||
"ulposc1_d2",
|
||||
"mainpll_d5",
|
||||
"mainpll_d2_d2",
|
||||
"mainpll_d3",
|
||||
"mainpll_d2",
|
||||
"univpll_d3"
|
||||
};
|
||||
|
||||
static const char * const apll_mck_parents[] = {
|
||||
"top_aud_1",
|
||||
"top_aud_2"
|
||||
};
|
||||
|
||||
static const struct mtk_mux top_mtk_muxes[] = {
|
||||
/*
|
||||
* CLK_CFG_0
|
||||
* top_axi is bus clock, should not be closed by Linux.
|
||||
* top_scp is main clock in always-on co-processor.
|
||||
*/
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI, "top_axi", axi_parents,
|
||||
0x0040, 0x0044, 0x0048, 0, 2, 7, 0x0004, 0,
|
||||
CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SCP, "top_scp", scp_parents,
|
||||
0x0040, 0x0044, 0x0048, 8, 3, 15, 0x0004, 1,
|
||||
CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG, "top_mfg",
|
||||
mfg_parents, 0x0040, 0x0044, 0x0048, 16, 2, 23, 0x0004, 2),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG, "top_camtg",
|
||||
camtg_parents, 0x0040, 0x0044, 0x0048, 24, 3, 31, 0x0004, 3),
|
||||
/* CLK_CFG_1 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1, "top_camtg1",
|
||||
camtg_parents, 0x0050, 0x0054, 0x0058, 0, 3, 7, 0x0004, 4),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2, "top_camtg2",
|
||||
camtg_parents, 0x0050, 0x0054, 0x0058, 8, 3, 15, 0x0004, 5),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3, "top_camtg3",
|
||||
camtg_parents, 0x0050, 0x0054, 0x0058, 16, 3, 23, 0x0004, 6),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG4, "top_camtg4",
|
||||
camtg_parents, 0x0050, 0x0054, 0x0058, 24, 3, 31, 0x0004, 7),
|
||||
/* CLK_CFG_2 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG5, "top_camtg5",
|
||||
camtg_parents, 0x0060, 0x0064, 0x0068, 0, 3, 7, 0x0004, 8),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG6, "top_camtg6",
|
||||
camtg_parents, 0x0060, 0x0064, 0x0068, 8, 3, 15, 0x0004, 9),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART, "top_uart",
|
||||
uart_parents, 0x0060, 0x0064, 0x0068, 16, 1, 23, 0x0004, 10),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI, "top_spi",
|
||||
spi_parents, 0x0060, 0x0064, 0x0068, 24, 3, 31, 0x0004, 11),
|
||||
/* CLK_CFG_3 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK, "top_msdc5hclk",
|
||||
msdc5hclk_parents, 0x0070, 0x0074, 0x0078, 0, 2, 7, 0x0004, 12),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0, "top_msdc50_0",
|
||||
msdc50_0_parents, 0x0070, 0x0074, 0x0078, 8, 3, 15, 0x0004, 13),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1, "top_msdc30_1",
|
||||
msdc30_1_parents, 0x0070, 0x0074, 0x0078, 16, 3, 23, 0x0004, 14),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO, "top_audio",
|
||||
audio_parents, 0x0070, 0x0074, 0x0078, 24, 2, 31, 0x0004, 15),
|
||||
/* CLK_CFG_4 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS, "top_aud_intbus",
|
||||
aud_intbus_parents, 0x0080, 0x0084, 0x0088, 0, 2, 7, 0x0004, 16),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1, "top_aud_1",
|
||||
aud_1_parents, 0x0080, 0x0084, 0x0088, 8, 1, 15, 0x0004, 17),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2, "top_aud_2",
|
||||
aud_2_parents, 0x0080, 0x0084, 0x0088, 16, 1, 23, 0x0004, 18),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1, "top_aud_engen1",
|
||||
aud_engen1_parents, 0x0080, 0x0084, 0x0088, 24, 2, 31, 0x0004, 19),
|
||||
/*
|
||||
* CLK_CFG_5
|
||||
* top_sspm is main clock in always-on co-processor, should not be closed
|
||||
* in Linux.
|
||||
*/
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2, "top_aud_engen2",
|
||||
aud_engen2_parents, 0x0090, 0x0094, 0x0098, 0, 2, 7, 0x0004, 20),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM, "top_disp_pwm",
|
||||
disp_pwm_parents, 0x0090, 0x0094, 0x0098, 8, 3, 15, 0x0004, 21),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SSPM, "top_sspm", sspm_parents,
|
||||
0x0090, 0x0094, 0x0098, 16, 3, 23, 0x0004, 22,
|
||||
CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC, "top_dxcc",
|
||||
dxcc_parents, 0x0090, 0x0094, 0x0098, 24, 2, 31, 0x0004, 23),
|
||||
/*
|
||||
* CLK_CFG_6
|
||||
* top_spm and top_srck are main clocks in always-on co-processor.
|
||||
*/
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP, "top_usb",
|
||||
usb_parents, 0x00a0, 0x00a4, 0x00a8, 0, 2, 7, 0x0004, 24),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SRCK, "top_srck", srck_parents,
|
||||
0x00a0, 0x00a4, 0x00a8, 8, 2, 15, 0x0004, 25,
|
||||
CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SPM, "top_spm", spm_parents,
|
||||
0x00a0, 0x00a4, 0x00a8, 16, 2, 23, 0x0004, 26,
|
||||
CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C, "top_i2c",
|
||||
i2c_parents, 0x00a0, 0x00a4, 0x00a8, 24, 2, 31, 0x0004, 27),
|
||||
/* CLK_CFG_7 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM, "top_pwm",
|
||||
pwm_parents, 0x00b0, 0x00b4, 0x00b8, 0, 2, 7, 0x0004, 28),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF, "top_seninf",
|
||||
seninf_parents, 0x00b0, 0x00b4, 0x00b8, 8, 2, 15, 0x0004, 29),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1, "top_seninf1",
|
||||
seninf_parents, 0x00b0, 0x00b4, 0x00b8, 16, 2, 23, 0x0004, 30),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF2, "top_seninf2",
|
||||
seninf_parents, 0x00b0, 0x00b4, 0x00b8, 24, 2, 31, 0x0008, 0),
|
||||
/* CLK_CFG_8 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF3, "top_seninf3",
|
||||
seninf_parents, 0x00c0, 0x00c4, 0x00c8, 0, 2, 7, 0x0008, 1),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE, "top_aes_msdcfde",
|
||||
aes_msdcfde_parents, 0x00c0, 0x00c4, 0x00c8, 8, 3, 15, 0x0008, 2),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWRAP_ULPOSC, "top_pwrap_ulposc",
|
||||
pwrap_ulposc_parents, 0x00c0, 0x00c4, 0x00c8, 16, 3, 23, 0x0008, 3),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM, "top_camtm",
|
||||
camtm_parents, 0x00c0, 0x00c4, 0x00c8, 24, 2, 31, 0x0008, 4),
|
||||
/* CLK_CFG_9 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC, "top_venc",
|
||||
venc_parents, 0x00d0, 0x00d4, 0x00d8, 0, 3, 7, 0x0008, 5),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM, "top_cam",
|
||||
isp_parents, 0x00d0, 0x00d4, 0x00d8, 8, 4, 15, 0x0008, 6),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1, "top_img1",
|
||||
isp_parents, 0x00d0, 0x00d4, 0x00d8, 16, 4, 23, 0x0008, 7),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE, "top_ipe",
|
||||
isp_parents, 0x00d0, 0x00d4, 0x00d8, 24, 4, 31, 0x0008, 8),
|
||||
/* CLK_CFG_10 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPMAIF, "top_dpmaif",
|
||||
dpmaif_parents, 0x00e0, 0x00e4, 0x00e8, 0, 3, 7, 0x0008, 9),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC, "top_vdec",
|
||||
vdec_parents, 0x00e0, 0x00e4, 0x00e8, 8, 3, 15, 0x0008, 10),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP, "top_disp",
|
||||
disp_parents, 0x00e0, 0x00e4, 0x00e8, 16, 4, 23, 0x0008, 11),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP, "top_mdp",
|
||||
mdp_parents, 0x00e0, 0x00e4, 0x00e8, 24, 4, 31, 0x0008, 12),
|
||||
/* CLK_CFG_11 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H, "top_audio_h",
|
||||
audio_h_parents, 0x00ec, 0x00f0, 0x00f4, 0, 2, 7, 0x0008, 13),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_UFS, "top_ufs",
|
||||
ufs_parents, 0x00ec, 0x00f0, 0x00f4, 8, 2, 15, 0x0008, 14),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE, "top_aes_fde",
|
||||
aes_fde_parents, 0x00ec, 0x00f0, 0x00f4, 16, 2, 23, 0x0008, 15),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIODSP, "top_audiodsp",
|
||||
audiodsp_parents, 0x00ec, 0x00f0, 0x00f4, 24, 3, 31, 0x0008, 16),
|
||||
/*
|
||||
* CLK_CFG_12
|
||||
* dvfsrc is for internal DVFS usage, should not be closed in Linux.
|
||||
*/
|
||||
MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DVFSRC, "top_dvfsrc", dvfsrc_parents,
|
||||
0x0100, 0x0104, 0x0108, 0, 1, 7, 0x0008, 17,
|
||||
CLK_IS_CRITICAL),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC, "top_dsi_occ",
|
||||
dsi_occ_parents, 0x0100, 0x0104, 0x0108, 8, 2, 15, 0x0008, 18),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPMI_MST, "top_spmi_mst",
|
||||
spmi_mst_parents, 0x0100, 0x0104, 0x0108, 16, 3, 23, 0x0008, 19),
|
||||
/* CLK_CFG_13 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINOR, "top_spinor",
|
||||
spinor_parents, 0x0110, 0x0114, 0x0118, 0, 3, 6, 0x0008, 20),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA, "top_nna",
|
||||
nna_parents, 0x0110, 0x0114, 0x0118, 7, 4, 14, 0x0008, 21),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA1, "top_nna1",
|
||||
nna_parents, 0x0110, 0x0114, 0x0118, 15, 4, 22, 0x0008, 22),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_NNA2, "top_nna2",
|
||||
nna2_parents, 0x0110, 0x0114, 0x0118, 23, 4, 30, 0x0008, 23),
|
||||
/* CLK_CFG_14 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI, "top_ssusb_xhci",
|
||||
ssusb_parents, 0x0120, 0x0124, 0x0128, 0, 2, 5, 0x0008, 24),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_TOP_1P, "top_ssusb_1p",
|
||||
ssusb_parents, 0x0120, 0x0124, 0x0128, 6, 2, 11, 0x0008, 25),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_SSUSB_XHCI_1P, "top_ssusb_xhci_1p",
|
||||
ssusb_parents, 0x0120, 0x0124, 0x0128, 12, 2, 17, 0x0008, 26),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_WPE, "top_wpe",
|
||||
wpe_parents, 0x0120, 0x0124, 0x0128, 18, 4, 25, 0x0008, 27),
|
||||
/* CLK_CFG_15 */
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_DPI, "top_dpi",
|
||||
dpi_parents, 0x0180, 0x0184, 0x0188, 0, 3, 6, 0x0008, 28),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_U3_OCC_250M, "top_u3_occ_250m",
|
||||
u3_occ_250m_parents, 0x0180, 0x0184, 0x0188, 7, 1, 11, 0x0008, 29),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_U3_OCC_500M, "top_u3_occ_500m",
|
||||
u3_occ_500m_parents, 0x0180, 0x0184, 0x0188, 12, 1, 16, 0x0008, 30),
|
||||
MUX_GATE_CLR_SET_UPD(CLK_TOP_ADSP_BUS, "top_adsp_bus",
|
||||
adsp_bus_parents, 0x0180, 0x0184, 0x0188, 17, 3, 23, 0x0008, 31),
|
||||
};
|
||||
|
||||
static struct mtk_composite top_muxes[] = {
|
||||
/* CLK_AUDDIV_0 */
|
||||
MUX(CLK_TOP_APLL_I2S0_MCK_SEL, "apll_i2s0_mck_sel", apll_mck_parents, 0x0320, 16, 1),
|
||||
MUX(CLK_TOP_APLL_I2S1_MCK_SEL, "apll_i2s1_mck_sel", apll_mck_parents, 0x0320, 17, 1),
|
||||
MUX(CLK_TOP_APLL_I2S2_MCK_SEL, "apll_i2s2_mck_sel", apll_mck_parents, 0x0320, 18, 1),
|
||||
MUX(CLK_TOP_APLL_I2S4_MCK_SEL, "apll_i2s4_mck_sel", apll_mck_parents, 0x0320, 19, 1),
|
||||
MUX(CLK_TOP_APLL_TDMOUT_MCK_SEL, "apll_tdmout_mck_sel", apll_mck_parents,
|
||||
0x0320, 20, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_composite top_adj_divs[] = {
|
||||
DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "apll_i2s0_mck_sel",
|
||||
0x0320, 0, 0x0328, 8, 0),
|
||||
DIV_GATE(CLK_TOP_APLL12_CK_DIV1, "apll12_div1", "apll_i2s1_mck_sel",
|
||||
0x0320, 1, 0x0328, 8, 8),
|
||||
DIV_GATE(CLK_TOP_APLL12_CK_DIV2, "apll12_div2", "apll_i2s2_mck_sel",
|
||||
0x0320, 2, 0x0328, 8, 16),
|
||||
DIV_GATE(CLK_TOP_APLL12_CK_DIV4, "apll12_div4", "apll_i2s4_mck_sel",
|
||||
0x0320, 3, 0x0328, 8, 24),
|
||||
DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_M, "apll12_div_tdmout_m", "apll_tdmout_mck_sel",
|
||||
0x0320, 4, 0x0334, 8, 0),
|
||||
};
|
||||
|
||||
static const struct of_device_id of_match_clk_mt8186_topck[] = {
|
||||
{ .compatible = "mediatek,mt8186-topckgen", },
|
||||
{}
|
||||
};
|
||||
|
||||
static int clk_mt8186_topck_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
void __iomem *base;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(base)) {
|
||||
r = PTR_ERR(base);
|
||||
goto free_top_data;
|
||||
}
|
||||
|
||||
r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
|
||||
clk_data);
|
||||
if (r)
|
||||
goto free_top_data;
|
||||
|
||||
r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
|
||||
if (r)
|
||||
goto unregister_fixed_clks;
|
||||
|
||||
r = mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node,
|
||||
&mt8186_clk_lock, clk_data);
|
||||
if (r)
|
||||
goto unregister_factors;
|
||||
|
||||
r = mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
|
||||
&mt8186_clk_lock, clk_data);
|
||||
if (r)
|
||||
goto unregister_muxes;
|
||||
|
||||
r = mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
|
||||
&mt8186_clk_lock, clk_data);
|
||||
if (r)
|
||||
goto unregister_composite_muxes;
|
||||
|
||||
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
|
||||
if (r)
|
||||
goto unregister_composite_divs;
|
||||
|
||||
platform_set_drvdata(pdev, clk_data);
|
||||
|
||||
return r;
|
||||
|
||||
unregister_composite_divs:
|
||||
mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), clk_data);
|
||||
unregister_composite_muxes:
|
||||
mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), clk_data);
|
||||
unregister_muxes:
|
||||
mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), clk_data);
|
||||
unregister_factors:
|
||||
mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
|
||||
unregister_fixed_clks:
|
||||
mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), clk_data);
|
||||
free_top_data:
|
||||
mtk_free_clk_data(clk_data);
|
||||
return r;
|
||||
}
|
||||
|
||||
static int clk_mt8186_topck_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
of_clk_del_provider(node);
|
||||
mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), clk_data);
|
||||
mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), clk_data);
|
||||
mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), clk_data);
|
||||
mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
|
||||
mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), clk_data);
|
||||
mtk_free_clk_data(clk_data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt8186_topck_drv = {
|
||||
.probe = clk_mt8186_topck_probe,
|
||||
.remove = clk_mt8186_topck_remove,
|
||||
.driver = {
|
||||
.name = "clk-mt8186-topck",
|
||||
.of_match_table = of_match_clk_mt8186_topck,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(clk_mt8186_topck_drv);
|
||||
Некоторые файлы не были показаны из-за слишком большого количества измененных файлов Показать больше
Загрузка…
Ссылка в новой задаче