ARM: cleanup undefined instruction entry code
We don't need to keep reloading the thread into into r10 - we can do this once and keep the value cached in the register. Also, schedule some instructions better so that the pipeline doesn't stall after a load in the neon code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -562,21 +562,21 @@ ENDPROC(__und_usr)
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@ Fall-through from Thumb-2 __und_usr
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@
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#ifdef CONFIG_NEON
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get_thread_info r10 @ get current thread
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adr r6, .LCneon_thumb_opcodes
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b 2f
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#endif
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call_fpe:
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get_thread_info r10 @ get current thread
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#ifdef CONFIG_NEON
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adr r6, .LCneon_arm_opcodes
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2:
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ldr r7, [r6], #4 @ mask value
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cmp r7, #0 @ end mask?
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beq 1f
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and r8, r0, r7
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2: ldr r5, [r6], #4 @ mask value
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ldr r7, [r6], #4 @ opcode bits matching in mask
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cmp r5, #0 @ end mask?
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beq 1f
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and r8, r0, r5
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cmp r8, r7 @ NEON instruction?
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bne 2b
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get_thread_info r10
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mov r7, #1
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strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
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strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
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@ -586,7 +586,6 @@ call_fpe:
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tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
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tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
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moveq pc, lr
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get_thread_info r10 @ get current thread
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and r8, r0, #0x00000f00 @ mask out CP number
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THUMB( lsr r8, r8, #8 )
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mov r7, #1
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