clk: add pxa27x clock drivers
Move pxa27x clock drivers from arch/arm/mach-pxa to driver/clk. In the move : - convert to new clock framework legacy clocks - provide clocks as before for platform data based boards - provide clocks through devicetree Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Robert Jarzmik
Mike Turquette
Родитель
108f303f0e
Коммит
d40670dc61
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@ -1 +1,2 @@
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obj-y += clk-pxa.o
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obj-$(CONFIG_PXA27x) += clk-pxa27x.o
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@ -0,0 +1,370 @@
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/*
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* Marvell PXA27x family clocks
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*
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* Copyright (C) 2014 Robert Jarzmik
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*
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* Heavily inspired from former arch/arm/mach-pxa/clock.c.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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*/
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#include <linux/clk-provider.h>
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#include <mach/pxa2xx-regs.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/of.h>
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#include <dt-bindings/clock/pxa-clock.h>
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#include "clk-pxa.h"
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#define KHz 1000
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#define MHz (1000 * 1000)
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enum {
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PXA_CORE_13Mhz = 0,
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PXA_CORE_RUN,
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PXA_CORE_TURBO,
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};
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enum {
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PXA_BUS_13Mhz = 0,
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PXA_BUS_RUN,
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};
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enum {
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PXA_LCD_13Mhz = 0,
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PXA_LCD_RUN,
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};
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enum {
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PXA_MEM_13Mhz = 0,
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PXA_MEM_SYSTEM_BUS,
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PXA_MEM_RUN,
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};
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static const char * const get_freq_khz[] = {
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"core", "run", "cpll", "memory",
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"system_bus"
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};
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/*
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* Get the clock frequency as reflected by CCSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa27x_get_clk_frequency_khz(int info)
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{
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struct clk *clk;
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unsigned long clks[5];
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int i;
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for (i = 0; i < 5; i++) {
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clk = clk_get(NULL, get_freq_khz[i]);
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if (IS_ERR(clk)) {
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clks[i] = 0;
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} else {
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clks[i] = clk_get_rate(clk);
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clk_put(clk);
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}
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}
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if (info) {
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pr_info("Run Mode clock: %ld.%02ldMHz\n",
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clks[1] / 1000000, (clks[1] % 1000000) / 10000);
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pr_info("Turbo Mode clock: %ld.%02ldMHz\n",
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clks[2] / 1000000, (clks[2] % 1000000) / 10000);
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pr_info("Memory clock: %ld.%02ldMHz\n",
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clks[3] / 1000000, (clks[3] % 1000000) / 10000);
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pr_info("System bus clock: %ld.%02ldMHz\n",
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clks[4] / 1000000, (clks[4] % 1000000) / 10000);
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}
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return (unsigned int)clks[0];
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}
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bool pxa27x_is_ppll_disabled(void)
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{
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unsigned long ccsr = CCSR;
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return ccsr & (1 << CCCR_PPDIS_BIT);
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}
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#define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \
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bit, is_lp, flags) \
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PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \
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is_lp, &CKEN, CKEN_ ## bit, flags)
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#define PXA27X_PBUS_CKEN(dev_id, con_id, bit, mult_hp, div_hp, delay) \
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PXA27X_CKEN(dev_id, con_id, pxa27x_pbus_parents, mult_hp, \
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div_hp, bit, pxa27x_is_ppll_disabled, 0)
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PARENTS(pxa27x_pbus) = { "osc_13mhz", "ppll_312mhz" };
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PARENTS(pxa27x_sbus) = { "system_bus", "system_bus" };
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PARENTS(pxa27x_32Mhz_bus) = { "osc_32_768khz", "osc_32_768khz" };
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PARENTS(pxa27x_lcd_bus) = { "lcd_base", "lcd_base" };
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PARENTS(pxa27x_membus) = { "lcd_base", "lcd_base" };
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#define PXA27X_CKEN_1RATE(dev_id, con_id, bit, parents, delay) \
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PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
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&CKEN, CKEN_ ## bit, 0)
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#define PXA27X_CKEN_1RATE_AO(dev_id, con_id, bit, parents, delay) \
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PXA_CKEN_1RATE(dev_id, con_id, bit, parents, \
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&CKEN, CKEN_ ## bit, CLK_IGNORE_UNUSED)
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static struct pxa_clk_cken pxa27x_clocks[] = {
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PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
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PXA27X_PBUS_CKEN("pxa2xx-uart.1", NULL, BTUART, 2, 42, 1),
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PXA27X_PBUS_CKEN("pxa2xx-uart.2", NULL, STUART, 2, 42, 1),
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PXA27X_PBUS_CKEN("pxa2xx-i2s", NULL, I2S, 2, 51, 0),
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PXA27X_PBUS_CKEN("pxa2xx-i2c.0", NULL, I2C, 2, 19, 0),
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PXA27X_PBUS_CKEN("pxa27x-udc", NULL, USB, 2, 13, 5),
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PXA27X_PBUS_CKEN("pxa2xx-mci.0", NULL, MMC, 2, 32, 0),
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PXA27X_PBUS_CKEN("pxa2xx-ir", "FICPCLK", FICP, 2, 13, 0),
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PXA27X_PBUS_CKEN("pxa27x-ohci", NULL, USBHOST, 2, 13, 0),
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PXA27X_PBUS_CKEN("pxa2xx-i2c.1", NULL, PWRI2C, 1, 24, 0),
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PXA27X_PBUS_CKEN("pxa27x-ssp.0", NULL, SSP1, 1, 24, 0),
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PXA27X_PBUS_CKEN("pxa27x-ssp.1", NULL, SSP2, 1, 24, 0),
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PXA27X_PBUS_CKEN("pxa27x-ssp.2", NULL, SSP3, 1, 24, 0),
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PXA27X_PBUS_CKEN("pxa27x-pwm.0", NULL, PWM0, 1, 24, 0),
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PXA27X_PBUS_CKEN("pxa27x-pwm.1", NULL, PWM1, 1, 24, 0),
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PXA27X_PBUS_CKEN(NULL, "MSLCLK", MSL, 2, 13, 0),
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PXA27X_PBUS_CKEN(NULL, "USIMCLK", USIM, 2, 13, 0),
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PXA27X_PBUS_CKEN(NULL, "MSTKCLK", MEMSTK, 2, 32, 0),
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PXA27X_PBUS_CKEN(NULL, "AC97CLK", AC97, 1, 1, 0),
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PXA27X_PBUS_CKEN(NULL, "AC97CONFCLK", AC97CONF, 1, 1, 0),
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PXA27X_PBUS_CKEN(NULL, "OSTIMER0", OSTIMER, 1, 96, 0),
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PXA27X_CKEN_1RATE("pxa27x-keypad", NULL, KEYPAD,
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pxa27x_32Mhz_bus_parents, 0),
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PXA27X_CKEN_1RATE(NULL, "IMCLK", IM, pxa27x_sbus_parents, 0),
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PXA27X_CKEN_1RATE("pxa2xx-fb", NULL, LCD, pxa27x_lcd_bus_parents, 0),
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PXA27X_CKEN_1RATE("pxa27x-camera.0", NULL, CAMERA,
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pxa27x_lcd_bus_parents, 0),
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PXA27X_CKEN_1RATE_AO("pxa2xx-pcmcia", NULL, MEMC,
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pxa27x_membus_parents, 0),
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};
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static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long clkcfg;
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unsigned int t, ht;
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unsigned int l, L, n2, N;
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unsigned long ccsr = CCSR;
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asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
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t = clkcfg & (1 << 0);
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ht = clkcfg & (1 << 2);
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l = ccsr & CCSR_L_MASK;
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n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
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L = l * parent_rate;
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N = (L * n2) / 2;
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return t ? N : L;
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}
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PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" };
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RATE_RO_OPS(clk_pxa27x_cpll, "cpll");
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static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned int l, osc_forced;
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unsigned long ccsr = CCSR;
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unsigned long cccr = CCCR;
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l = ccsr & CCSR_L_MASK;
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osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
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if (osc_forced) {
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if (cccr & (1 << CCCR_LCD_26_BIT))
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return parent_rate * 2;
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else
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return parent_rate;
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}
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if (l <= 7)
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return parent_rate;
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if (l <= 16)
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return parent_rate / 2;
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return parent_rate / 4;
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}
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static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw)
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{
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unsigned int osc_forced;
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unsigned long ccsr = CCSR;
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osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
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if (osc_forced)
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return PXA_LCD_13Mhz;
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else
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return PXA_LCD_RUN;
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}
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PARENTS(clk_pxa27x_lcd_base) = { "osc_13mhz", "run" };
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MUX_RO_RATE_RO_OPS(clk_pxa27x_lcd_base, "lcd_base");
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static void __init pxa27x_register_plls(void)
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{
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clk_register_fixed_rate(NULL, "osc_13mhz", NULL,
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CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
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13 * MHz);
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clk_register_fixed_rate(NULL, "osc_32_768khz", NULL,
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CLK_GET_RATE_NOCACHE | CLK_IS_ROOT,
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32768 * KHz);
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clk_register_fixed_rate(NULL, "clk_dummy", NULL, CLK_IS_ROOT, 0);
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clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
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}
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static unsigned long clk_pxa27x_core_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long clkcfg;
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unsigned int t, ht, b, osc_forced;
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unsigned long ccsr = CCSR;
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osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
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asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
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t = clkcfg & (1 << 0);
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ht = clkcfg & (1 << 2);
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b = clkcfg & (1 << 3);
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if (osc_forced)
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return parent_rate;
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if (ht)
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return parent_rate / 2;
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else
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return parent_rate;
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}
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static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
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{
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unsigned long clkcfg;
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unsigned int t, ht, b, osc_forced;
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unsigned long ccsr = CCSR;
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osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
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if (osc_forced)
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return PXA_CORE_13Mhz;
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asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
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t = clkcfg & (1 << 0);
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ht = clkcfg & (1 << 2);
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b = clkcfg & (1 << 3);
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if (ht || t)
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return PXA_CORE_TURBO;
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return PXA_CORE_RUN;
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}
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PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" };
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MUX_RO_RATE_RO_OPS(clk_pxa27x_core, "core");
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static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long ccsr = CCSR;
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unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
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return (parent_rate / n2) * 2;
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}
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PARENTS(clk_pxa27x_run) = { "cpll" };
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RATE_RO_OPS(clk_pxa27x_run, "run");
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static void __init pxa27x_register_core(void)
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{
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clk_register_clk_pxa27x_cpll();
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clk_register_clk_pxa27x_run();
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clkdev_pxa_register(CLK_CORE, "core", NULL,
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clk_register_clk_pxa27x_core());
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}
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static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned long clkcfg;
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unsigned int b, osc_forced;
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unsigned long ccsr = CCSR;
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osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
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asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
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b = clkcfg & (1 << 3);
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if (osc_forced)
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return parent_rate;
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if (b)
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return parent_rate / 2;
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else
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return parent_rate;
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}
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static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw)
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{
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unsigned int osc_forced;
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unsigned long ccsr = CCSR;
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osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
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if (osc_forced)
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return PXA_BUS_13Mhz;
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else
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return PXA_BUS_RUN;
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}
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PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz", "run" };
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MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus");
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static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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unsigned int a, l, osc_forced;
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unsigned long cccr = CCCR;
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unsigned long ccsr = CCSR;
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osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
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a = cccr & CCCR_A_BIT;
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l = ccsr & CCSR_L_MASK;
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if (osc_forced || a)
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return parent_rate;
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if (l <= 10)
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return parent_rate;
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if (l <= 20)
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return parent_rate / 2;
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return parent_rate / 4;
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}
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static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
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{
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unsigned int osc_forced, a;
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unsigned long cccr = CCCR;
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unsigned long ccsr = CCSR;
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osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
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a = cccr & CCCR_A_BIT;
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if (osc_forced)
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return PXA_MEM_13Mhz;
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if (a)
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return PXA_MEM_SYSTEM_BUS;
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else
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return PXA_MEM_RUN;
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}
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PARENTS(clk_pxa27x_memory) = { "osc_13mhz", "system_bus", "run" };
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MUX_RO_RATE_RO_OPS(clk_pxa27x_memory, "memory");
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static void __init pxa27x_base_clocks_init(void)
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{
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pxa27x_register_plls();
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pxa27x_register_core();
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clk_register_clk_pxa27x_system_bus();
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clk_register_clk_pxa27x_memory();
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clk_register_clk_pxa27x_lcd_base();
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}
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static int __init pxa27x_clocks_init(void)
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{
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pxa27x_base_clocks_init();
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return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks));
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}
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postcore_initcall(pxa27x_clocks_init);
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