ixgbe: Merge FCoE set_num and cache_ring calls into RSS/DCB config
This change merges the ixgbe_cache_ring_fcoe and ixgbe_set_fcoe_queues logic into the DCB and RSS initialization calls. Cc: John Fastabend <john.r.fastabend@intel.com> Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Tested-by: Ross Brattain <ross.b.brattain@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Alexander Duyck
Jeff Kirsher
Родитель
800bd607c3
Коммит
d411a9368b
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@ -28,28 +28,6 @@
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#include "ixgbe.h"
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#include "ixgbe_sriov.h"
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/**
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* ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
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* @adapter: board private structure to initialize
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*
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* Cache the descriptor ring offsets for RSS to the assigned rings.
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*
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**/
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static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
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{
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int i;
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if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
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return false;
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for (i = 0; i < adapter->num_rx_queues; i++)
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adapter->rx_ring[i]->reg_idx = i;
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for (i = 0; i < adapter->num_tx_queues; i++)
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adapter->tx_ring[i]->reg_idx = i;
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return true;
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}
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#ifdef CONFIG_IXGBE_DCB
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/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
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static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
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@ -136,39 +114,8 @@ static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
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return true;
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}
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#endif
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#ifdef IXGBE_FCOE
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/**
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* ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
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* @adapter: board private structure to initialize
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*
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* Cache the descriptor ring offsets for FCoE mode to the assigned rings.
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*
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*/
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static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
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{
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struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
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int i;
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u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
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if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
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return false;
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if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
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ixgbe_cache_ring_rss(adapter);
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fcoe_rx_i = f->offset;
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fcoe_tx_i = f->offset;
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}
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for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
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adapter->rx_ring[f->offset + i]->reg_idx = fcoe_rx_i;
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adapter->tx_ring[f->offset + i]->reg_idx = fcoe_tx_i;
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}
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return true;
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}
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#endif /* IXGBE_FCOE */
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/**
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* ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
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* @adapter: board private structure to initialize
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@ -187,6 +134,28 @@ static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
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return false;
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}
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/**
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* ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
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* @adapter: board private structure to initialize
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*
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* Cache the descriptor ring offsets for RSS to the assigned rings.
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*
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**/
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static bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
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{
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int i;
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if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
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return false;
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for (i = 0; i < adapter->num_rx_queues; i++)
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adapter->rx_ring[i]->reg_idx = i;
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for (i = 0; i < adapter->num_tx_queues; i++)
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adapter->tx_ring[i]->reg_idx = i;
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return true;
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}
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/**
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* ixgbe_cache_ring_register - Descriptor ring to register mapping
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* @adapter: board private structure to initialize
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@ -212,13 +181,7 @@ static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
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return;
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#endif
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#ifdef IXGBE_FCOE
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if (ixgbe_cache_ring_fcoe(adapter))
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return;
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#endif /* IXGBE_FCOE */
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if (ixgbe_cache_ring_rss(adapter))
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return;
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ixgbe_cache_ring_rss(adapter);
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}
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/**
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@ -234,6 +197,74 @@ static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
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return false;
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}
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#define IXGBE_RSS_16Q_MASK 0xF
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#define IXGBE_RSS_8Q_MASK 0x7
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#define IXGBE_RSS_4Q_MASK 0x3
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#define IXGBE_RSS_2Q_MASK 0x1
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#define IXGBE_RSS_DISABLED_MASK 0x0
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#ifdef CONFIG_IXGBE_DCB
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static bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
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{
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struct net_device *dev = adapter->netdev;
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struct ixgbe_ring_feature *f;
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int rss_i, rss_m, i;
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int tcs;
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/* Map queue offset and counts onto allocated tx queues */
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tcs = netdev_get_num_tc(dev);
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/* verify we have DCB queueing enabled before proceeding */
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if (tcs <= 1)
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return false;
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/* determine the upper limit for our current DCB mode */
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rss_i = dev->num_tx_queues / tcs;
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if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
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/* 8 TC w/ 4 queues per TC */
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rss_i = min_t(u16, rss_i, 4);
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rss_m = IXGBE_RSS_4Q_MASK;
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} else if (tcs > 4) {
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/* 8 TC w/ 8 queues per TC */
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rss_i = min_t(u16, rss_i, 8);
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rss_m = IXGBE_RSS_8Q_MASK;
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} else {
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/* 4 TC w/ 16 queues per TC */
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rss_i = min_t(u16, rss_i, 16);
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rss_m = IXGBE_RSS_16Q_MASK;
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}
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/* set RSS mask and indices */
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f = &adapter->ring_feature[RING_F_RSS];
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rss_i = min_t(int, rss_i, f->limit);
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f->indices = rss_i;
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f->mask = rss_m;
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#ifdef IXGBE_FCOE
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/* FCoE enabled queues require special configuration indexed
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* by feature specific indices and offset. Here we map FCoE
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* indices onto the DCB queue pairs allowing FCoE to own
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* configuration later.
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*/
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if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
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u8 tc = ixgbe_fcoe_get_tc(adapter);
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f = &adapter->ring_feature[RING_F_FCOE];
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f->indices = min_t(u16, rss_i, f->limit);
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f->offset = rss_i * tc;
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}
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#endif /* IXGBE_FCOE */
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for (i = 0; i < tcs; i++)
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netdev_set_tc_queue(dev, i, rss_i, rss_i * i);
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adapter->num_tx_queues = rss_i * tcs;
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adapter->num_rx_queues = rss_i * tcs;
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return true;
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}
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#endif
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/**
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* ixgbe_set_rss_queues - Allocate queues for RSS
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* @adapter: board private structure to initialize
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@ -257,7 +288,7 @@ static bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
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rss_i = f->limit;
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f->indices = rss_i;
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f->mask = 0xF;
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f->mask = IXGBE_RSS_16Q_MASK;
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/*
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* Use Flow Director in addition to RSS to ensure the best
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@ -271,91 +302,42 @@ static bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
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rss_i = max_t(u16, rss_i, f->indices);
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}
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#ifdef IXGBE_FCOE
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/*
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* FCoE can exist on the same rings as standard network traffic
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* however it is preferred to avoid that if possible. In order
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* to get the best performance we allocate as many FCoE queues
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* as we can and we place them at the end of the ring array to
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* avoid sharing queues with standard RSS on systems with 24 or
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* more CPUs.
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*/
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if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
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struct net_device *dev = adapter->netdev;
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u16 fcoe_i;
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f = &adapter->ring_feature[RING_F_FCOE];
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/* merge FCoE queues with RSS queues */
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fcoe_i = min_t(u16, f->limit + rss_i, num_online_cpus());
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fcoe_i = min_t(u16, fcoe_i, dev->num_tx_queues);
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/* limit indices to rss_i if MSI-X is disabled */
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if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
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fcoe_i = rss_i;
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/* attempt to reserve some queues for just FCoE */
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f->indices = min_t(u16, fcoe_i, f->limit);
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f->offset = fcoe_i - f->indices;
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rss_i = max_t(u16, fcoe_i, rss_i);
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}
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#endif /* IXGBE_FCOE */
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adapter->num_rx_queues = rss_i;
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adapter->num_tx_queues = rss_i;
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return true;
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}
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#ifdef IXGBE_FCOE
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/**
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* ixgbe_set_fcoe_queues - Allocate queues for Fiber Channel over Ethernet (FCoE)
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* @adapter: board private structure to initialize
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*
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* FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
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* Offset is used as the index of the first rx queue used by FCoE.
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**/
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static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
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{
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struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
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if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
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return false;
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f->indices = min_t(int, num_online_cpus(), f->limit);
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adapter->num_rx_queues = 1;
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adapter->num_tx_queues = 1;
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if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
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e_info(probe, "FCoE enabled with RSS\n");
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ixgbe_set_rss_queues(adapter);
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}
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/* adding FCoE rx rings to the end */
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f->offset = adapter->num_rx_queues;
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adapter->num_rx_queues += f->indices;
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adapter->num_tx_queues += f->indices;
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return true;
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}
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#endif /* IXGBE_FCOE */
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/* Artificial max queue cap per traffic class in DCB mode */
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#define DCB_QUEUE_CAP 8
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#ifdef CONFIG_IXGBE_DCB
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static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
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{
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int per_tc_q, q, i, offset = 0;
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struct net_device *dev = adapter->netdev;
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int tcs = netdev_get_num_tc(dev);
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if (!tcs)
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return false;
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/* Map queue offset and counts onto allocated tx queues */
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per_tc_q = min_t(unsigned int, dev->num_tx_queues / tcs, DCB_QUEUE_CAP);
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q = min_t(int, num_online_cpus(), per_tc_q);
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for (i = 0; i < tcs; i++) {
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netdev_set_tc_queue(dev, i, q, offset);
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offset += q;
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}
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adapter->num_tx_queues = q * tcs;
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adapter->num_rx_queues = q * tcs;
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#ifdef IXGBE_FCOE
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/* FCoE enabled queues require special configuration indexed
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* by feature specific indices and offset. Here we map FCoE
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* indices onto the DCB queue pairs allowing FCoE to own
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* configuration later.
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*/
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if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
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u8 tc = ixgbe_fcoe_get_tc(adapter);
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struct ixgbe_ring_feature *f =
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&adapter->ring_feature[RING_F_FCOE];
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f->indices = dev->tc_to_txq[tc].count;
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f->offset = dev->tc_to_txq[tc].offset;
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}
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#endif
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return true;
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}
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#endif
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/**
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* ixgbe_set_num_queues - Allocate queues for device, feature dependent
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* @adapter: board private structure to initialize
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@ -383,11 +365,6 @@ static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
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goto done;
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#endif
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#ifdef IXGBE_FCOE
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if (ixgbe_set_fcoe_queues(adapter))
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goto done;
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#endif /* IXGBE_FCOE */
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if (ixgbe_set_rss_queues(adapter))
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goto done;
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@ -3610,16 +3610,17 @@ static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
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if (hw->mac.type != ixgbe_mac_82598EB) {
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int i;
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u32 reg = 0;
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u8 msb = 0;
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u8 rss_i = adapter->netdev->tc_to_txq[0].count - 1;
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
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u8 msb = 0;
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u8 cnt = adapter->netdev->tc_to_txq[i].count;
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while (cnt >>= 1)
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msb++;
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reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
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while (rss_i) {
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msb++;
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rss_i >>= 1;
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}
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for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
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reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
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IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
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}
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}
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@ -7027,7 +7028,11 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
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#endif
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if (ii->mac == ixgbe_mac_82598EB)
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#ifdef CONFIG_IXGBE_DCB
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indices = min_t(unsigned int, indices, MAX_TRAFFIC_CLASS * 4);
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#else
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indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
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#endif
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else
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indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
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