drivers: net: cpsw-phy-sel: add dra7xx support for phy sel
Add dra7xx support for selecting the phy mode which is present in control module of dra7xx SoC Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Коммит
d415fa1b88
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@ -2,7 +2,8 @@ TI CPSW Phy mode Selection Device Tree Bindings
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-----------------------------------------------
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-----------------------------------------------
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Required properties:
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Required properties:
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- compatible : Should be "ti,am3352-cpsw-phy-sel"
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- compatible : Should be "ti,am3352-cpsw-phy-sel" for am335x platform and
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"ti,dra7xx-cpsw-phy-sel" for dra7xx platform
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- reg : physical base address and size of the cpsw
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- reg : physical base address and size of the cpsw
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registers map
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registers map
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- reg-names : names of the register map given in "reg" node
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- reg-names : names of the register map given in "reg" node
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@ -29,6 +29,8 @@
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#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
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#define AM33XX_GMII_SEL_RMII2_IO_CLK_EN BIT(7)
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#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
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#define AM33XX_GMII_SEL_RMII1_IO_CLK_EN BIT(6)
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#define GMII_SEL_MODE_MASK 0x3
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struct cpsw_phy_sel_priv {
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struct cpsw_phy_sel_priv {
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struct device *dev;
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struct device *dev;
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u32 __iomem *gmii_sel;
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u32 __iomem *gmii_sel;
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@ -65,7 +67,7 @@ static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv,
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break;
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break;
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};
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};
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mask = 0x3 << (slave * 2) | BIT(slave + 6);
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mask = GMII_SEL_MODE_MASK << (slave * 2) | BIT(slave + 6);
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mode <<= slave * 2;
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mode <<= slave * 2;
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if (priv->rmii_clock_external) {
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if (priv->rmii_clock_external) {
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@ -81,6 +83,55 @@ static void cpsw_gmii_sel_am3352(struct cpsw_phy_sel_priv *priv,
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writel(reg, priv->gmii_sel);
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writel(reg, priv->gmii_sel);
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}
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}
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static void cpsw_gmii_sel_dra7xx(struct cpsw_phy_sel_priv *priv,
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phy_interface_t phy_mode, int slave)
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{
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u32 reg;
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u32 mask;
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u32 mode = 0;
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reg = readl(priv->gmii_sel);
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switch (phy_mode) {
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case PHY_INTERFACE_MODE_RMII:
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mode = AM33XX_GMII_SEL_MODE_RMII;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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mode = AM33XX_GMII_SEL_MODE_RGMII;
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break;
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case PHY_INTERFACE_MODE_MII:
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default:
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mode = AM33XX_GMII_SEL_MODE_MII;
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break;
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};
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switch (slave) {
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case 0:
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mask = GMII_SEL_MODE_MASK;
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break;
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case 1:
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mask = GMII_SEL_MODE_MASK << 4;
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mode <<= 4;
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break;
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default:
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dev_err(priv->dev, "invalid slave number...\n");
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return;
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}
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if (priv->rmii_clock_external)
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dev_err(priv->dev, "RMII External clock is not supported\n");
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reg &= ~mask;
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reg |= mode;
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writel(reg, priv->gmii_sel);
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}
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static struct platform_driver cpsw_phy_sel_driver;
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static struct platform_driver cpsw_phy_sel_driver;
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static int match(struct device *dev, void *data)
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static int match(struct device *dev, void *data)
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{
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{
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@ -112,6 +163,10 @@ static const struct of_device_id cpsw_phy_sel_id_table[] = {
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.compatible = "ti,am3352-cpsw-phy-sel",
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.compatible = "ti,am3352-cpsw-phy-sel",
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.data = &cpsw_gmii_sel_am3352,
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.data = &cpsw_gmii_sel_am3352,
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},
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},
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{
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.compatible = "ti,dra7xx-cpsw-phy-sel",
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.data = &cpsw_gmii_sel_dra7xx,
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},
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{}
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{}
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};
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};
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MODULE_DEVICE_TABLE(of, cpsw_phy_sel_id_table);
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MODULE_DEVICE_TABLE(of, cpsw_phy_sel_id_table);
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