[PATCH] bitops: xtensa: use generic bitops
- remove {,test_and_}{set,clear,change}_bit()
- remove __{,test_and_}{set,clear,change}_bit() and test_bit()
- remove generic_fls64()
- remove find_{next,first}{,_zero}_bit()
- remove ext2_{set,clear,test,find_first_zero,find_next_zero}_bit()
- remove generic_hweight{32,16,8}()
- remove sched_find_first_bit()
- remove minix_{test,set,test_and_clear,test,find_first_zero}_bit()
Signed-off-by: Akinobu Mita <mita@miraclelinux.com>
Cc: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Akinobu Mita
Linus Torvalds
Родитель
f33e2fbacc
Коммит
d4337aa528
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@ -22,6 +22,14 @@ config RWSEM_XCHGADD_ALGORITHM
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bool
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default y
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config GENERIC_FIND_NEXT_BIT
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bool
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default y
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config GENERIC_HWEIGHT
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bool
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default y
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config GENERIC_HARDIRQS
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bool
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default y
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@ -23,156 +23,11 @@
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# error SMP not supported on this architecture
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#endif
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static __inline__ void set_bit(int nr, volatile void * addr)
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{
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
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unsigned long flags;
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local_irq_save(flags);
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*a |= mask;
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local_irq_restore(flags);
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}
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static __inline__ void __set_bit(int nr, volatile unsigned long * addr)
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{
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
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*a |= mask;
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}
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static __inline__ void clear_bit(int nr, volatile void * addr)
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{
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
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unsigned long flags;
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local_irq_save(flags);
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*a &= ~mask;
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local_irq_restore(flags);
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}
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static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
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*a &= ~mask;
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}
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/*
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* clear_bit() doesn't provide any barrier for the compiler.
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*/
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#define smp_mb__before_clear_bit() barrier()
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#define smp_mb__after_clear_bit() barrier()
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static __inline__ void change_bit(int nr, volatile void * addr)
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{
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
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unsigned long flags;
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local_irq_save(flags);
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*a ^= mask;
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local_irq_restore(flags);
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}
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static __inline__ void __change_bit(int nr, volatile void * addr)
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{
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
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*a ^= mask;
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}
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static __inline__ int test_and_set_bit(int nr, volatile void * addr)
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{
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unsigned long retval;
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
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unsigned long flags;
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local_irq_save(flags);
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retval = (mask & *a) != 0;
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*a |= mask;
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local_irq_restore(flags);
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return retval;
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}
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static __inline__ int __test_and_set_bit(int nr, volatile void * addr)
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{
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unsigned long retval;
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
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retval = (mask & *a) != 0;
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*a |= mask;
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return retval;
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}
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static __inline__ int test_and_clear_bit(int nr, volatile void * addr)
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{
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unsigned long retval;
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
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unsigned long flags;
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local_irq_save(flags);
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retval = (mask & *a) != 0;
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*a &= ~mask;
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local_irq_restore(flags);
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return retval;
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}
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static __inline__ int __test_and_clear_bit(int nr, volatile void * addr)
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{
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
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unsigned long old = *a;
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*a = old & ~mask;
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return (old & mask) != 0;
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}
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static __inline__ int test_and_change_bit(int nr, volatile void * addr)
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{
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unsigned long retval;
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
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unsigned long flags;
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local_irq_save(flags);
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retval = (mask & *a) != 0;
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*a ^= mask;
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local_irq_restore(flags);
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return retval;
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}
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/*
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* non-atomic version; can be reordered
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*/
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static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
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{
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unsigned long mask = 1 << (nr & 0x1f);
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unsigned long *a = ((unsigned long *)addr) + (nr >> 5);
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unsigned long old = *a;
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*a = old ^ mask;
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return (old & mask) != 0;
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}
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static __inline__ int test_bit(int nr, const volatile void *addr)
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{
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return 1UL & (((const volatile unsigned int *)addr)[nr>>5] >> (nr&31));
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}
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#include <asm-generic/bitops/atomic.h>
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#include <asm-generic/bitops/non-atomic.h>
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#if XCHAL_HAVE_NSA
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@ -245,202 +100,23 @@ static __inline__ int fls (unsigned int x)
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{
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return __cntlz(x);
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}
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#define fls64(x) generic_fls64(x)
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static __inline__ int
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find_next_bit(const unsigned long *addr, int size, int offset)
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{
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const unsigned long *p = addr + (offset >> 5);
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unsigned long result = offset & ~31UL;
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unsigned long tmp;
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if (offset >= size)
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return size;
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size -= result;
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offset &= 31UL;
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if (offset) {
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tmp = *p++;
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tmp &= ~0UL << offset;
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if (size < 32)
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goto found_first;
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if (tmp)
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goto found_middle;
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size -= 32;
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result += 32;
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}
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while (size >= 32) {
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if ((tmp = *p++) != 0)
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goto found_middle;
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result += 32;
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size -= 32;
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}
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if (!size)
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return result;
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tmp = *p;
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found_first:
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tmp &= ~0UL >> (32 - size);
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if (tmp == 0UL) /* Are any bits set? */
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return result + size; /* Nope. */
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found_middle:
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return result + __ffs(tmp);
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}
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/**
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* find_first_bit - find the first set bit in a memory region
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* @addr: The address to start the search at
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* @size: The maximum size to search
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*
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* Returns the bit-number of the first set bit, not the number of the byte
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* containing a bit.
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*/
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#define find_first_bit(addr, size) \
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find_next_bit((addr), (size), 0)
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static __inline__ int
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find_next_zero_bit(const unsigned long *addr, int size, int offset)
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{
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const unsigned long *p = addr + (offset >> 5);
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unsigned long result = offset & ~31UL;
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unsigned long tmp;
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if (offset >= size)
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return size;
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size -= result;
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offset &= 31UL;
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if (offset) {
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tmp = *p++;
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tmp |= ~0UL >> (32-offset);
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if (size < 32)
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goto found_first;
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if (~tmp)
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goto found_middle;
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size -= 32;
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result += 32;
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}
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while (size & ~31UL) {
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if (~(tmp = *p++))
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goto found_middle;
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result += 32;
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size -= 32;
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}
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if (!size)
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return result;
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tmp = *p;
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found_first:
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tmp |= ~0UL << size;
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found_middle:
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return result + ffz(tmp);
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}
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#define find_first_zero_bit(addr, size) \
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find_next_zero_bit((addr), (size), 0)
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#include <asm-generic/bitops/fls64.h>
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#include <asm-generic/bitops/find.h>
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#include <asm-generic/bitops/ext2-non-atomic.h>
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#ifdef __XTENSA_EL__
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# define ext2_set_bit(nr,addr) __test_and_set_bit((nr), (addr))
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# define ext2_set_bit_atomic(lock,nr,addr) test_and_set_bit((nr),(addr))
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# define ext2_clear_bit(nr,addr) __test_and_clear_bit((nr), (addr))
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# define ext2_clear_bit_atomic(lock,nr,addr) test_and_clear_bit((nr),(addr))
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# define ext2_test_bit(nr,addr) test_bit((nr), (addr))
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# define ext2_find_first_zero_bit(addr, size) find_first_zero_bit((addr),(size))
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# define ext2_find_next_zero_bit(addr, size, offset) \
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find_next_zero_bit((addr), (size), (offset))
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#elif defined(__XTENSA_EB__)
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# define ext2_set_bit(nr,addr) __test_and_set_bit((nr) ^ 0x18, (addr))
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# define ext2_set_bit_atomic(lock,nr,addr) test_and_set_bit((nr) ^ 0x18, (addr))
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# define ext2_clear_bit(nr,addr) __test_and_clear_bit((nr) ^ 18, (addr))
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# define ext2_clear_bit_atomic(lock,nr,addr) test_and_clear_bit((nr)^0x18,(addr))
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# define ext2_test_bit(nr,addr) test_bit((nr) ^ 0x18, (addr))
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# define ext2_find_first_zero_bit(addr, size) \
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ext2_find_next_zero_bit((addr), (size), 0)
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static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset)
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{
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unsigned long *p = ((unsigned long *) addr) + (offset >> 5);
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unsigned long result = offset & ~31UL;
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unsigned long tmp;
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if (offset >= size)
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return size;
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size -= result;
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offset &= 31UL;
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if(offset) {
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/* We hold the little endian value in tmp, but then the
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* shift is illegal. So we could keep a big endian value
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* in tmp, like this:
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*
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* tmp = __swab32(*(p++));
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* tmp |= ~0UL >> (32-offset);
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*
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* but this would decrease preformance, so we change the
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* shift:
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*/
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tmp = *(p++);
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tmp |= __swab32(~0UL >> (32-offset));
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if(size < 32)
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goto found_first;
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if(~tmp)
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goto found_middle;
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size -= 32;
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result += 32;
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}
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while(size & ~31UL) {
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if(~(tmp = *(p++)))
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goto found_middle;
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result += 32;
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size -= 32;
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}
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if(!size)
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return result;
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tmp = *p;
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found_first:
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/* tmp is little endian, so we would have to swab the shift,
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* see above. But then we have to swab tmp below for ffz, so
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* we might as well do this here.
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*/
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return result + ffz(__swab32(tmp) | (~0UL << size));
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found_middle:
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return result + ffz(__swab32(tmp));
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}
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#else
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# error processor byte order undefined!
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#endif
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#define hweight32(x) generic_hweight32(x)
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#define hweight16(x) generic_hweight16(x)
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#define hweight8(x) generic_hweight8(x)
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/*
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* Find the first bit set in a 140-bit bitmap.
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* The first 100 bits are unlikely to be set.
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*/
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static inline int sched_find_first_bit(const unsigned long *b)
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{
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if (unlikely(b[0]))
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return __ffs(b[0]);
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if (unlikely(b[1]))
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return __ffs(b[1]) + 32;
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if (unlikely(b[2]))
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return __ffs(b[2]) + 64;
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if (b[3])
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return __ffs(b[3]) + 96;
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return __ffs(b[4]) + 128;
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}
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/* Bitmap functions for the minix filesystem. */
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#define minix_test_and_set_bit(nr,addr) __test_and_set_bit(nr,addr)
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#define minix_set_bit(nr,addr) __set_bit(nr,addr)
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#define minix_test_and_clear_bit(nr,addr) __test_and_clear_bit(nr,addr)
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#define minix_test_bit(nr,addr) test_bit(nr,addr)
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#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
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#include <asm-generic/bitops/hweight.h>
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/minix.h>
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#endif /* __KERNEL__ */
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