EDAC, fsl_ddr: Rename macros and names
Use FSL-specific prefix for macros, variables and functions. Signed-off-by: York Sun <york.sun@nxp.com> Cc: Johannes Thumshirn <morbidrsa@gmail.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: oss@buserror.net Cc: stuart.yoder@nxp.com Link: http://lkml.kernel.org/r/1470779760-16483-5-git-send-email-york.sun@nxp.com Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
York Sun
Borislav Petkov
Родитель
ea2eb9a8b6
Коммит
d43a9fb202
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@ -42,74 +42,74 @@ static u32 orig_ddr_err_sbe;
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#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
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static ssize_t mpc85xx_mc_inject_data_hi_show(struct device *dev,
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struct device_attribute *mattr,
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static ssize_t fsl_mc_inject_data_hi_show(struct device *dev,
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struct device_attribute *mattr,
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char *data)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->mc_vbase +
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FSL_MC_DATA_ERR_INJECT_HI));
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}
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static ssize_t fsl_mc_inject_data_lo_show(struct device *dev,
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struct device_attribute *mattr,
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char *data)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->mc_vbase +
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MPC85XX_MC_DATA_ERR_INJECT_HI));
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FSL_MC_DATA_ERR_INJECT_LO));
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}
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static ssize_t mpc85xx_mc_inject_data_lo_show(struct device *dev,
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struct device_attribute *mattr,
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char *data)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->mc_vbase +
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MPC85XX_MC_DATA_ERR_INJECT_LO));
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}
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static ssize_t mpc85xx_mc_inject_ctrl_show(struct device *dev,
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struct device_attribute *mattr,
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static ssize_t fsl_mc_inject_ctrl_show(struct device *dev,
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struct device_attribute *mattr,
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char *data)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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return sprintf(data, "0x%08x",
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in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT));
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in_be32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT));
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}
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static ssize_t mpc85xx_mc_inject_data_hi_store(struct device *dev,
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struct device_attribute *mattr,
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static ssize_t fsl_mc_inject_data_hi_store(struct device *dev,
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struct device_attribute *mattr,
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const char *data, size_t count)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI,
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out_be32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_HI,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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return 0;
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}
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static ssize_t mpc85xx_mc_inject_data_lo_store(struct device *dev,
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struct device_attribute *mattr,
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static ssize_t fsl_mc_inject_data_lo_store(struct device *dev,
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struct device_attribute *mattr,
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const char *data, size_t count)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO,
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out_be32(pdata->mc_vbase + FSL_MC_DATA_ERR_INJECT_LO,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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return 0;
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}
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static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev,
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struct device_attribute *mattr,
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static ssize_t fsl_mc_inject_ctrl_store(struct device *dev,
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struct device_attribute *mattr,
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const char *data, size_t count)
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{
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struct mem_ctl_info *mci = to_mci(dev);
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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if (isdigit(*data)) {
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out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT,
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out_be32(pdata->mc_vbase + FSL_MC_ECC_ERR_INJECT,
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simple_strtoul(data, NULL, 0));
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return count;
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}
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@ -117,20 +117,20 @@ static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev,
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}
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DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR,
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mpc85xx_mc_inject_data_hi_show, mpc85xx_mc_inject_data_hi_store);
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fsl_mc_inject_data_hi_show, fsl_mc_inject_data_hi_store);
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DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR,
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mpc85xx_mc_inject_data_lo_show, mpc85xx_mc_inject_data_lo_store);
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fsl_mc_inject_data_lo_show, fsl_mc_inject_data_lo_store);
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DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR,
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mpc85xx_mc_inject_ctrl_show, mpc85xx_mc_inject_ctrl_store);
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fsl_mc_inject_ctrl_show, fsl_mc_inject_ctrl_store);
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static struct attribute *mpc85xx_dev_attrs[] = {
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static struct attribute *fsl_ddr_dev_attrs[] = {
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&dev_attr_inject_data_hi.attr,
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&dev_attr_inject_data_lo.attr,
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&dev_attr_inject_ctrl.attr,
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NULL
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};
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ATTRIBUTE_GROUPS(mpc85xx_dev);
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ATTRIBUTE_GROUPS(fsl_ddr_dev);
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/**************************** MC Err device ***************************/
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@ -241,9 +241,9 @@ static void sbe_ecc_decode(u32 cap_high, u32 cap_low, u32 cap_ecc,
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#define make64(high, low) (((u64)(high) << 32) | (low))
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static void mpc85xx_mc_check(struct mem_ctl_info *mci)
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static void fsl_mc_check(struct mem_ctl_info *mci)
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{
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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struct csrow_info *csrow;
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u32 bus_width;
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u32 err_detect;
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@ -256,23 +256,23 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
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int bad_data_bit;
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int bad_ecc_bit;
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err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
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err_detect = in_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
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if (!err_detect)
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return;
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mpc85xx_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
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err_detect);
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fsl_mc_printk(mci, KERN_ERR, "Err Detect Register: %#8.8x\n",
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err_detect);
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/* no more processing if not ECC bit errors */
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if (!(err_detect & (DDR_EDE_SBE | DDR_EDE_MBE))) {
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out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
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out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
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return;
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}
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syndrome = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ECC);
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syndrome = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_ECC);
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/* Mask off appropriate bits of syndrome based on bus width */
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bus_width = (in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG) &
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bus_width = (in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG) &
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DSC_DBW_MASK) ? 32 : 64;
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if (bus_width == 64)
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syndrome &= 0xff;
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@ -280,8 +280,8 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
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syndrome &= 0xffff;
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err_addr = make64(
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in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_EXT_ADDRESS),
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in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_ADDRESS));
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in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_EXT_ADDRESS),
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in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_ADDRESS));
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pfn = err_addr >> PAGE_SHIFT;
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for (row_index = 0; row_index < mci->nr_csrows; row_index++) {
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@ -290,8 +290,8 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
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break;
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}
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cap_high = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_HI);
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cap_low = in_be32(pdata->mc_vbase + MPC85XX_MC_CAPTURE_DATA_LO);
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cap_high = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_HI);
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cap_low = in_be32(pdata->mc_vbase + FSL_MC_CAPTURE_DATA_LO);
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/*
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* Analyze single-bit errors on 64-bit wide buses
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@ -302,28 +302,28 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
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&bad_data_bit, &bad_ecc_bit);
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if (bad_data_bit != -1)
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mpc85xx_mc_printk(mci, KERN_ERR,
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fsl_mc_printk(mci, KERN_ERR,
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"Faulty Data bit: %d\n", bad_data_bit);
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if (bad_ecc_bit != -1)
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mpc85xx_mc_printk(mci, KERN_ERR,
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fsl_mc_printk(mci, KERN_ERR,
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"Faulty ECC bit: %d\n", bad_ecc_bit);
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mpc85xx_mc_printk(mci, KERN_ERR,
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fsl_mc_printk(mci, KERN_ERR,
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"Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
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cap_high ^ (1 << (bad_data_bit - 32)),
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cap_low ^ (1 << bad_data_bit),
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syndrome ^ (1 << bad_ecc_bit));
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}
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mpc85xx_mc_printk(mci, KERN_ERR,
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fsl_mc_printk(mci, KERN_ERR,
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"Captured Data / ECC:\t%#8.8x_%08x / %#2.2x\n",
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cap_high, cap_low, syndrome);
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mpc85xx_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr);
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mpc85xx_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
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fsl_mc_printk(mci, KERN_ERR, "Err addr: %#8.8llx\n", err_addr);
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fsl_mc_printk(mci, KERN_ERR, "PFN: %#8.8x\n", pfn);
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/* we are out of range */
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if (row_index == mci->nr_csrows)
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mpc85xx_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
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fsl_mc_printk(mci, KERN_ERR, "PFN out of range!\n");
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if (err_detect & DDR_EDE_SBE)
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
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@ -337,27 +337,27 @@ static void mpc85xx_mc_check(struct mem_ctl_info *mci)
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row_index, 0, -1,
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mci->ctl_name, "");
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out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, err_detect);
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out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, err_detect);
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}
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static irqreturn_t mpc85xx_mc_isr(int irq, void *dev_id)
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static irqreturn_t fsl_mc_isr(int irq, void *dev_id)
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{
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struct mem_ctl_info *mci = dev_id;
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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u32 err_detect;
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err_detect = in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT);
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err_detect = in_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT);
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if (!err_detect)
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return IRQ_NONE;
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mpc85xx_mc_check(mci);
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fsl_mc_check(mci);
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return IRQ_HANDLED;
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}
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static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
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static void fsl_ddr_init_csrows(struct mem_ctl_info *mci)
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{
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struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
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struct fsl_mc_pdata *pdata = mci->pvt_info;
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struct csrow_info *csrow;
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struct dimm_info *dimm;
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u32 sdram_ctl;
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@ -366,7 +366,7 @@ static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
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u32 cs_bnds;
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int index;
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sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
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sdram_ctl = in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
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sdtype = sdram_ctl & DSC_SDTYPE_MASK;
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if (sdram_ctl & DSC_RD_EN) {
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@ -408,8 +408,8 @@ static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
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csrow = mci->csrows[index];
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dimm = csrow->channels[0]->dimm;
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cs_bnds = in_be32(pdata->mc_vbase + MPC85XX_MC_CS_BNDS_0 +
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(index * MPC85XX_MC_CS_BNDS_OFS));
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cs_bnds = in_be32(pdata->mc_vbase + FSL_MC_CS_BNDS_0 +
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(index * FSL_MC_CS_BNDS_OFS));
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start = (cs_bnds & 0xffff0000) >> 16;
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end = (cs_bnds & 0x0000ffff);
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@ -434,16 +434,16 @@ static void mpc85xx_init_csrows(struct mem_ctl_info *mci)
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}
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}
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int mpc85xx_mc_err_probe(struct platform_device *op)
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int fsl_mc_err_probe(struct platform_device *op)
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{
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struct mem_ctl_info *mci;
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struct edac_mc_layer layers[2];
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struct mpc85xx_mc_pdata *pdata;
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struct fsl_mc_pdata *pdata;
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struct resource r;
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u32 sdram_ctl;
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int res;
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if (!devres_open_group(&op->dev, mpc85xx_mc_err_probe, GFP_KERNEL))
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if (!devres_open_group(&op->dev, fsl_mc_err_probe, GFP_KERNEL))
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return -ENOMEM;
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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@ -455,12 +455,12 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
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mci = edac_mc_alloc(edac_mc_idx, ARRAY_SIZE(layers), layers,
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sizeof(*pdata));
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if (!mci) {
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devres_release_group(&op->dev, mpc85xx_mc_err_probe);
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devres_release_group(&op->dev, fsl_mc_err_probe);
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return -ENOMEM;
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}
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pdata = mci->pvt_info;
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pdata->name = "mpc85xx_mc_err";
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pdata->name = "fsl_mc_err";
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pdata->irq = NO_IRQ;
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mci->pdev = &op->dev;
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pdata->edac_idx = edac_mc_idx++;
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@ -490,7 +490,7 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
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goto err;
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}
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sdram_ctl = in_be32(pdata->mc_vbase + MPC85XX_MC_DDR_SDRAM_CFG);
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sdram_ctl = in_be32(pdata->mc_vbase + FSL_MC_DDR_SDRAM_CFG);
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if (!(sdram_ctl & DSC_ECC_EN)) {
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/* no ECC */
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pr_warn("%s: No ECC DIMMs discovered\n", __func__);
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@ -506,46 +506,46 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
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mci->mod_name = EDAC_MOD_STR;
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if (edac_op_state == EDAC_OPSTATE_POLL)
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mci->edac_check = mpc85xx_mc_check;
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mci->edac_check = fsl_mc_check;
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mci->ctl_page_to_phys = NULL;
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mci->scrub_mode = SCRUB_SW_SRC;
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mpc85xx_init_csrows(mci);
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fsl_ddr_init_csrows(mci);
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/* store the original error disable bits */
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orig_ddr_err_disable =
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in_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE);
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out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE, 0);
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in_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE);
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out_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE, 0);
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/* clear all error bits */
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||||
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DETECT, ~0);
|
||||
out_be32(pdata->mc_vbase + FSL_MC_ERR_DETECT, ~0);
|
||||
|
||||
if (edac_mc_add_mc_with_groups(mci, mpc85xx_dev_groups)) {
|
||||
if (edac_mc_add_mc_with_groups(mci, fsl_ddr_dev_groups)) {
|
||||
edac_dbg(3, "failed edac_mc_add_mc()\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (edac_op_state == EDAC_OPSTATE_INT) {
|
||||
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN,
|
||||
out_be32(pdata->mc_vbase + FSL_MC_ERR_INT_EN,
|
||||
DDR_EIE_MBEE | DDR_EIE_SBEE);
|
||||
|
||||
/* store the original error management threshold */
|
||||
orig_ddr_err_sbe = in_be32(pdata->mc_vbase +
|
||||
MPC85XX_MC_ERR_SBE) & 0xff0000;
|
||||
FSL_MC_ERR_SBE) & 0xff0000;
|
||||
|
||||
/* set threshold to 1 error per interrupt */
|
||||
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, 0x10000);
|
||||
out_be32(pdata->mc_vbase + FSL_MC_ERR_SBE, 0x10000);
|
||||
|
||||
/* register interrupts */
|
||||
pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0);
|
||||
res = devm_request_irq(&op->dev, pdata->irq,
|
||||
mpc85xx_mc_isr,
|
||||
fsl_mc_isr,
|
||||
IRQF_SHARED,
|
||||
"[EDAC] MC err", mci);
|
||||
if (res < 0) {
|
||||
pr_err("%s: Unable to request irq %d for MPC85xx DRAM ERR\n",
|
||||
pr_err("%s: Unable to request irq %d for FSL DDR DRAM ERR\n",
|
||||
__func__, pdata->irq);
|
||||
irq_dispose_mapping(pdata->irq);
|
||||
res = -ENODEV;
|
||||
|
|
@ -556,7 +556,7 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
|
|||
pdata->irq);
|
||||
}
|
||||
|
||||
devres_remove_group(&op->dev, mpc85xx_mc_err_probe);
|
||||
devres_remove_group(&op->dev, fsl_mc_err_probe);
|
||||
edac_dbg(3, "success\n");
|
||||
pr_info(EDAC_MOD_STR " MC err registered\n");
|
||||
|
||||
|
|
@ -565,26 +565,26 @@ int mpc85xx_mc_err_probe(struct platform_device *op)
|
|||
err2:
|
||||
edac_mc_del_mc(&op->dev);
|
||||
err:
|
||||
devres_release_group(&op->dev, mpc85xx_mc_err_probe);
|
||||
devres_release_group(&op->dev, fsl_mc_err_probe);
|
||||
edac_mc_free(mci);
|
||||
return res;
|
||||
}
|
||||
|
||||
int mpc85xx_mc_err_remove(struct platform_device *op)
|
||||
int fsl_mc_err_remove(struct platform_device *op)
|
||||
{
|
||||
struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
|
||||
struct mpc85xx_mc_pdata *pdata = mci->pvt_info;
|
||||
struct fsl_mc_pdata *pdata = mci->pvt_info;
|
||||
|
||||
edac_dbg(0, "\n");
|
||||
|
||||
if (edac_op_state == EDAC_OPSTATE_INT) {
|
||||
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_INT_EN, 0);
|
||||
out_be32(pdata->mc_vbase + FSL_MC_ERR_INT_EN, 0);
|
||||
irq_dispose_mapping(pdata->irq);
|
||||
}
|
||||
|
||||
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_DISABLE,
|
||||
out_be32(pdata->mc_vbase + FSL_MC_ERR_DISABLE,
|
||||
orig_ddr_err_disable);
|
||||
out_be32(pdata->mc_vbase + MPC85XX_MC_ERR_SBE, orig_ddr_err_sbe);
|
||||
out_be32(pdata->mc_vbase + FSL_MC_ERR_SBE, orig_ddr_err_sbe);
|
||||
|
||||
edac_mc_del_mc(&op->dev);
|
||||
edac_mc_free(mci);
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
#ifndef _FSL_DDR_EDAC_H_
|
||||
#define _FSL_DDR_EDAC_H_
|
||||
|
||||
#define mpc85xx_mc_printk(mci, level, fmt, arg...) \
|
||||
#define fsl_mc_printk(mci, level, fmt, arg...) \
|
||||
edac_mc_chipset_printk(mci, level, "FSL_DDR", fmt, ##arg)
|
||||
|
||||
/*
|
||||
|
|
@ -24,26 +24,23 @@
|
|||
*/
|
||||
|
||||
/* DDR_SDRAM_CFG */
|
||||
#define MPC85XX_MC_DDR_SDRAM_CFG 0x0110
|
||||
#define MPC85XX_MC_CS_BNDS_0 0x0000
|
||||
#define MPC85XX_MC_CS_BNDS_1 0x0008
|
||||
#define MPC85XX_MC_CS_BNDS_2 0x0010
|
||||
#define MPC85XX_MC_CS_BNDS_3 0x0018
|
||||
#define MPC85XX_MC_CS_BNDS_OFS 0x0008
|
||||
#define FSL_MC_DDR_SDRAM_CFG 0x0110
|
||||
#define FSL_MC_CS_BNDS_0 0x0000
|
||||
#define FSL_MC_CS_BNDS_OFS 0x0008
|
||||
|
||||
#define MPC85XX_MC_DATA_ERR_INJECT_HI 0x0e00
|
||||
#define MPC85XX_MC_DATA_ERR_INJECT_LO 0x0e04
|
||||
#define MPC85XX_MC_ECC_ERR_INJECT 0x0e08
|
||||
#define MPC85XX_MC_CAPTURE_DATA_HI 0x0e20
|
||||
#define MPC85XX_MC_CAPTURE_DATA_LO 0x0e24
|
||||
#define MPC85XX_MC_CAPTURE_ECC 0x0e28
|
||||
#define MPC85XX_MC_ERR_DETECT 0x0e40
|
||||
#define MPC85XX_MC_ERR_DISABLE 0x0e44
|
||||
#define MPC85XX_MC_ERR_INT_EN 0x0e48
|
||||
#define MPC85XX_MC_CAPTURE_ATRIBUTES 0x0e4c
|
||||
#define MPC85XX_MC_CAPTURE_ADDRESS 0x0e50
|
||||
#define MPC85XX_MC_CAPTURE_EXT_ADDRESS 0x0e54
|
||||
#define MPC85XX_MC_ERR_SBE 0x0e58
|
||||
#define FSL_MC_DATA_ERR_INJECT_HI 0x0e00
|
||||
#define FSL_MC_DATA_ERR_INJECT_LO 0x0e04
|
||||
#define FSL_MC_ECC_ERR_INJECT 0x0e08
|
||||
#define FSL_MC_CAPTURE_DATA_HI 0x0e20
|
||||
#define FSL_MC_CAPTURE_DATA_LO 0x0e24
|
||||
#define FSL_MC_CAPTURE_ECC 0x0e28
|
||||
#define FSL_MC_ERR_DETECT 0x0e40
|
||||
#define FSL_MC_ERR_DISABLE 0x0e44
|
||||
#define FSL_MC_ERR_INT_EN 0x0e48
|
||||
#define FSL_MC_CAPTURE_ATRIBUTES 0x0e4c
|
||||
#define FSL_MC_CAPTURE_ADDRESS 0x0e50
|
||||
#define FSL_MC_CAPTURE_EXT_ADDRESS 0x0e54
|
||||
#define FSL_MC_ERR_SBE 0x0e58
|
||||
|
||||
#define DSC_MEM_EN 0x80000000
|
||||
#define DSC_ECC_EN 0x20000000
|
||||
|
|
@ -75,12 +72,12 @@
|
|||
#define DDR_EDI_SBED 0x4 /* single-bit ECC error disable */
|
||||
#define DDR_EDI_MBED 0x8 /* multi-bit ECC error disable */
|
||||
|
||||
struct mpc85xx_mc_pdata {
|
||||
struct fsl_mc_pdata {
|
||||
char *name;
|
||||
int edac_idx;
|
||||
void __iomem *mc_vbase;
|
||||
int irq;
|
||||
};
|
||||
int mpc85xx_mc_err_probe(struct platform_device *op);
|
||||
int mpc85xx_mc_err_remove(struct platform_device *op);
|
||||
int fsl_mc_err_probe(struct platform_device *op);
|
||||
int fsl_mc_err_remove(struct platform_device *op);
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -656,8 +656,8 @@ static const struct of_device_id mpc85xx_mc_err_of_match[] = {
|
|||
MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match);
|
||||
|
||||
static struct platform_driver mpc85xx_mc_err_driver = {
|
||||
.probe = mpc85xx_mc_err_probe,
|
||||
.remove = mpc85xx_mc_err_remove,
|
||||
.probe = fsl_mc_err_probe,
|
||||
.remove = fsl_mc_err_remove,
|
||||
.driver = {
|
||||
.name = "mpc85xx_mc_err",
|
||||
.of_match_table = mpc85xx_mc_err_of_match,
|
||||
|
|
|
|||
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