iio: adc: Add driver for Renesas RZ/G2L A/D converter
Add ADC driver support for Renesas RZ/G2L A/D converter in SW trigger mode. A/D Converter block is a successive approximation analog-to-digital converter with a 12-bit accuracy and supports a maximum of 8 input channels. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20210804202118.25745-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Lad Prabhakar
Jonathan Cameron
Родитель
0808096316
Коммит
d484c21bac
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@ -15856,6 +15856,14 @@ L: linux-renesas-soc@vger.kernel.org
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S: Maintained
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F: drivers/phy/renesas/phy-rcar-gen3-usb*.c
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RENESAS RZ/G2L A/D DRIVER
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M: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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L: linux-iio@vger.kernel.org
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L: linux-renesas-soc@vger.kernel.org
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S: Supported
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F: Documentation/devicetree/bindings/iio/adc/renesas,rzg2l-adc.yaml
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F: drivers/iio/adc/rzg2l_adc.c
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RESET CONTROLLER FRAMEWORK
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M: Philipp Zabel <p.zabel@pengutronix.de>
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S: Maintained
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@ -887,6 +887,16 @@ config ROCKCHIP_SARADC
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To compile this driver as a module, choose M here: the
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module will be called rockchip_saradc.
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config RZG2L_ADC
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tristate "Renesas RZ/G2L ADC driver"
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depends on ARCH_R9A07G044 || COMPILE_TEST
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help
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Say yes here to build support for the ADC found in Renesas
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RZ/G2L family.
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To compile this driver as a module, choose M here: the
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module will be called rzg2l_adc.
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config SC27XX_ADC
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tristate "Spreadtrum SC27xx series PMICs ADC"
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depends on MFD_SC27XX_PMIC || COMPILE_TEST
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@ -82,6 +82,7 @@ obj-$(CONFIG_QCOM_PM8XXX_XOADC) += qcom-pm8xxx-xoadc.o
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obj-$(CONFIG_RCAR_GYRO_ADC) += rcar-gyroadc.o
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obj-$(CONFIG_RN5T618_ADC) += rn5t618-adc.o
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obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
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obj-$(CONFIG_RZG2L_ADC) += rzg2l_adc.o
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obj-$(CONFIG_SC27XX_ADC) += sc27xx_adc.o
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obj-$(CONFIG_SPEAR_ADC) += spear_adc.o
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obj-$(CONFIG_STX104) += stx104.o
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@ -0,0 +1,600 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* RZ/G2L A/D Converter driver
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*
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* Copyright (c) 2021 Renesas Electronics Europe GmbH
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*
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* Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/iio/iio.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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#define DRIVER_NAME "rzg2l-adc"
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#define RZG2L_ADM(n) ((n) * 0x4)
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#define RZG2L_ADM0_ADCE BIT(0)
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#define RZG2L_ADM0_ADBSY BIT(1)
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#define RZG2L_ADM0_PWDWNB BIT(2)
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#define RZG2L_ADM0_SRESB BIT(15)
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#define RZG2L_ADM1_TRG BIT(0)
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#define RZG2L_ADM1_MS BIT(2)
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#define RZG2L_ADM1_BS BIT(4)
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#define RZG2L_ADM1_EGA_MASK GENMASK(13, 12)
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#define RZG2L_ADM2_CHSEL_MASK GENMASK(7, 0)
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#define RZG2L_ADM3_ADIL_MASK GENMASK(31, 24)
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#define RZG2L_ADM3_ADCMP_MASK GENMASK(23, 16)
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#define RZG2L_ADM3_ADCMP_E FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, 0xe)
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#define RZG2L_ADM3_ADSMP_MASK GENMASK(15, 0)
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#define RZG2L_ADINT 0x20
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#define RZG2L_ADINT_INTEN_MASK GENMASK(7, 0)
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#define RZG2L_ADINT_CSEEN BIT(16)
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#define RZG2L_ADINT_INTS BIT(31)
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#define RZG2L_ADSTS 0x24
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#define RZG2L_ADSTS_CSEST BIT(16)
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#define RZG2L_ADSTS_INTST_MASK GENMASK(7, 0)
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#define RZG2L_ADIVC 0x28
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#define RZG2L_ADIVC_DIVADC_MASK GENMASK(8, 0)
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#define RZG2L_ADIVC_DIVADC_4 FIELD_PREP(RZG2L_ADIVC_DIVADC_MASK, 0x4)
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#define RZG2L_ADFIL 0x2c
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#define RZG2L_ADCR(n) (0x30 + ((n) * 0x4))
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#define RZG2L_ADCR_AD_MASK GENMASK(11, 0)
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#define RZG2L_ADSMP_DEFUALT_SAMPLING 0x578
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#define RZG2L_ADC_MAX_CHANNELS 8
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#define RZG2L_ADC_CHN_MASK 0x7
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#define RZG2L_ADC_TIMEOUT usecs_to_jiffies(1 * 4)
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struct rzg2l_adc_data {
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const struct iio_chan_spec *channels;
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u8 num_channels;
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};
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struct rzg2l_adc {
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void __iomem *base;
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struct clk *pclk;
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struct clk *adclk;
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struct reset_control *presetn;
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struct reset_control *adrstn;
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struct completion completion;
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const struct rzg2l_adc_data *data;
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struct mutex lock;
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u16 last_val[RZG2L_ADC_MAX_CHANNELS];
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};
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static const char * const rzg2l_adc_channel_name[] = {
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"adc0",
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"adc1",
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"adc2",
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"adc3",
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"adc4",
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"adc5",
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"adc6",
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"adc7",
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};
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static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg)
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{
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return readl(adc->base + reg);
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}
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static void rzg2l_adc_writel(struct rzg2l_adc *adc, unsigned int reg, u32 val)
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{
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writel(val, adc->base + reg);
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}
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static void rzg2l_adc_pwr(struct rzg2l_adc *adc, bool on)
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{
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u32 reg;
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reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
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if (on)
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reg |= RZG2L_ADM0_PWDWNB;
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else
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reg &= ~RZG2L_ADM0_PWDWNB;
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rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
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udelay(2);
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}
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static void rzg2l_adc_start_stop(struct rzg2l_adc *adc, bool start)
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{
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int timeout = 5;
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u32 reg;
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reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
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if (start)
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reg |= RZG2L_ADM0_ADCE;
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else
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reg &= ~RZG2L_ADM0_ADCE;
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rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
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if (start)
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return;
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do {
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usleep_range(100, 200);
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reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
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timeout--;
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if (!timeout) {
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pr_err("%s stopping ADC timed out\n", __func__);
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break;
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}
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} while (((reg & RZG2L_ADM0_ADBSY) || (reg & RZG2L_ADM0_ADCE)));
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}
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static void rzg2l_set_trigger(struct rzg2l_adc *adc)
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{
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u32 reg;
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/*
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* Setup ADM1 for SW trigger
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* EGA[13:12] - Set 00 to indicate hardware trigger is invalid
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* BS[4] - Enable 1-buffer mode
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* MS[1] - Enable Select mode
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* TRG[0] - Enable software trigger mode
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*/
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reg = rzg2l_adc_readl(adc, RZG2L_ADM(1));
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reg &= ~RZG2L_ADM1_EGA_MASK;
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reg &= ~RZG2L_ADM1_BS;
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reg &= ~RZG2L_ADM1_TRG;
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reg |= RZG2L_ADM1_MS;
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rzg2l_adc_writel(adc, RZG2L_ADM(1), reg);
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}
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static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)
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{
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u32 reg;
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if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY)
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return -EBUSY;
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rzg2l_set_trigger(adc);
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/* Select analog input channel subjected to conversion. */
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reg = rzg2l_adc_readl(adc, RZG2L_ADM(2));
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reg &= ~RZG2L_ADM2_CHSEL_MASK;
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reg |= BIT(ch);
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rzg2l_adc_writel(adc, RZG2L_ADM(2), reg);
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/*
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* Setup ADINT
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* INTS[31] - Select pulse signal
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* CSEEN[16] - Enable channel select error interrupt
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* INTEN[7:0] - Select channel interrupt
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*/
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reg = rzg2l_adc_readl(adc, RZG2L_ADINT);
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reg &= ~RZG2L_ADINT_INTS;
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reg &= ~RZG2L_ADINT_INTEN_MASK;
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reg |= (RZG2L_ADINT_CSEEN | BIT(ch));
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rzg2l_adc_writel(adc, RZG2L_ADINT, reg);
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return 0;
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}
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static int rzg2l_adc_set_power(struct iio_dev *indio_dev, bool on)
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{
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struct device *dev = indio_dev->dev.parent;
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if (on)
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return pm_runtime_resume_and_get(dev);
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return pm_runtime_put_sync(dev);
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}
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static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch)
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{
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int ret;
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ret = rzg2l_adc_set_power(indio_dev, true);
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if (ret)
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return ret;
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ret = rzg2l_adc_conversion_setup(adc, ch);
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if (ret) {
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rzg2l_adc_set_power(indio_dev, false);
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return ret;
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}
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reinit_completion(&adc->completion);
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rzg2l_adc_start_stop(adc, true);
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if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) {
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rzg2l_adc_writel(adc, RZG2L_ADINT,
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rzg2l_adc_readl(adc, RZG2L_ADINT) & ~RZG2L_ADINT_INTEN_MASK);
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rzg2l_adc_start_stop(adc, false);
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rzg2l_adc_set_power(indio_dev, false);
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return -ETIMEDOUT;
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}
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return rzg2l_adc_set_power(indio_dev, false);
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}
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static int rzg2l_adc_read_raw(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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int *val, int *val2, long mask)
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{
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struct rzg2l_adc *adc = iio_priv(indio_dev);
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int ret;
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u8 ch;
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switch (mask) {
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case IIO_CHAN_INFO_RAW:
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if (chan->type != IIO_VOLTAGE)
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return -EINVAL;
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mutex_lock(&adc->lock);
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ch = chan->channel & RZG2L_ADC_CHN_MASK;
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ret = rzg2l_adc_conversion(indio_dev, adc, ch);
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if (ret) {
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mutex_unlock(&adc->lock);
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return ret;
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}
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*val = adc->last_val[ch];
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mutex_unlock(&adc->lock);
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return IIO_VAL_INT;
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default:
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return -EINVAL;
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}
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}
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static int rzg2l_adc_read_label(struct iio_dev *iio_dev,
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const struct iio_chan_spec *chan,
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char *label)
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{
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if (chan->channel >= RZG2L_ADC_MAX_CHANNELS)
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return -EINVAL;
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return sysfs_emit(label, "%s\n", rzg2l_adc_channel_name[chan->channel]);
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}
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static const struct iio_info rzg2l_adc_iio_info = {
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.read_raw = rzg2l_adc_read_raw,
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.read_label = rzg2l_adc_read_label,
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};
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static irqreturn_t rzg2l_adc_isr(int irq, void *dev_id)
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{
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struct rzg2l_adc *adc = dev_id;
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unsigned long intst;
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u32 reg;
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int ch;
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reg = rzg2l_adc_readl(adc, RZG2L_ADSTS);
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/* A/D conversion channel select error interrupt */
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if (reg & RZG2L_ADSTS_CSEST) {
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rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
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return IRQ_HANDLED;
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}
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intst = reg & RZG2L_ADSTS_INTST_MASK;
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if (!intst)
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return IRQ_NONE;
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for_each_set_bit(ch, &intst, RZG2L_ADC_MAX_CHANNELS)
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adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK;
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/* clear the channel interrupt */
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rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
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complete(&adc->completion);
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return IRQ_HANDLED;
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}
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static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l_adc *adc)
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{
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struct iio_chan_spec *chan_array;
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struct fwnode_handle *fwnode;
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struct rzg2l_adc_data *data;
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unsigned int channel;
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int num_channels;
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int ret;
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u8 i;
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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num_channels = device_get_child_node_count(&pdev->dev);
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if (!num_channels) {
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dev_err(&pdev->dev, "no channel children\n");
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return -ENODEV;
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}
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if (num_channels > RZG2L_ADC_MAX_CHANNELS) {
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dev_err(&pdev->dev, "num of channel children out of range\n");
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return -EINVAL;
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}
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chan_array = devm_kcalloc(&pdev->dev, num_channels, sizeof(*chan_array),
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GFP_KERNEL);
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if (!chan_array)
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return -ENOMEM;
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i = 0;
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device_for_each_child_node(&pdev->dev, fwnode) {
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ret = fwnode_property_read_u32(fwnode, "reg", &channel);
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if (ret)
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return ret;
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if (channel >= RZG2L_ADC_MAX_CHANNELS)
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return -EINVAL;
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chan_array[i].type = IIO_VOLTAGE;
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chan_array[i].indexed = 1;
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chan_array[i].channel = channel;
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chan_array[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
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chan_array[i].datasheet_name = rzg2l_adc_channel_name[channel];
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i++;
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}
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data->num_channels = num_channels;
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data->channels = chan_array;
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adc->data = data;
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return 0;
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}
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static int rzg2l_adc_hw_init(struct rzg2l_adc *adc)
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{
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int timeout = 5;
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u32 reg;
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int ret;
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ret = clk_prepare_enable(adc->pclk);
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if (ret)
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return ret;
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/* SW reset */
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reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
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reg |= RZG2L_ADM0_SRESB;
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rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
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while (!(rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_SRESB)) {
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if (!timeout) {
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ret = -EBUSY;
|
||||
goto exit_hw_init;
|
||||
}
|
||||
timeout--;
|
||||
usleep_range(100, 200);
|
||||
}
|
||||
|
||||
/* Only division by 4 can be set */
|
||||
reg = rzg2l_adc_readl(adc, RZG2L_ADIVC);
|
||||
reg &= ~RZG2L_ADIVC_DIVADC_MASK;
|
||||
reg |= RZG2L_ADIVC_DIVADC_4;
|
||||
rzg2l_adc_writel(adc, RZG2L_ADIVC, reg);
|
||||
|
||||
/*
|
||||
* Setup AMD3
|
||||
* ADIL[31:24] - Should be always set to 0
|
||||
* ADCMP[23:16] - Should be always set to 0xe
|
||||
* ADSMP[15:0] - Set default (0x578) sampling period
|
||||
*/
|
||||
reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
|
||||
reg &= ~RZG2L_ADM3_ADIL_MASK;
|
||||
reg &= ~RZG2L_ADM3_ADCMP_MASK;
|
||||
reg &= ~RZG2L_ADM3_ADSMP_MASK;
|
||||
reg |= (RZG2L_ADM3_ADCMP_E | RZG2L_ADSMP_DEFUALT_SAMPLING);
|
||||
rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
|
||||
|
||||
exit_hw_init:
|
||||
clk_disable_unprepare(adc->pclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rzg2l_adc_pm_runtime_disable(void *data)
|
||||
{
|
||||
struct device *dev = data;
|
||||
|
||||
pm_runtime_disable(dev->parent);
|
||||
}
|
||||
|
||||
static void rzg2l_adc_pm_runtime_set_suspended(void *data)
|
||||
{
|
||||
struct device *dev = data;
|
||||
|
||||
pm_runtime_set_suspended(dev->parent);
|
||||
}
|
||||
|
||||
static void rzg2l_adc_reset_assert(void *data)
|
||||
{
|
||||
reset_control_assert(data);
|
||||
}
|
||||
|
||||
static int rzg2l_adc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct iio_dev *indio_dev;
|
||||
struct rzg2l_adc *adc;
|
||||
int ret;
|
||||
int irq;
|
||||
|
||||
indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
|
||||
if (!indio_dev)
|
||||
return -ENOMEM;
|
||||
|
||||
adc = iio_priv(indio_dev);
|
||||
|
||||
ret = rzg2l_adc_parse_properties(pdev, adc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mutex_init(&adc->lock);
|
||||
|
||||
adc->base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(adc->base))
|
||||
return PTR_ERR(adc->base);
|
||||
|
||||
adc->pclk = devm_clk_get(dev, "pclk");
|
||||
if (IS_ERR(adc->pclk)) {
|
||||
dev_err(dev, "Failed to get pclk");
|
||||
return PTR_ERR(adc->pclk);
|
||||
}
|
||||
|
||||
adc->adclk = devm_clk_get(dev, "adclk");
|
||||
if (IS_ERR(adc->adclk)) {
|
||||
dev_err(dev, "Failed to get adclk");
|
||||
return PTR_ERR(adc->adclk);
|
||||
}
|
||||
|
||||
adc->adrstn = devm_reset_control_get_exclusive(dev, "adrst-n");
|
||||
if (IS_ERR(adc->adrstn)) {
|
||||
dev_err(dev, "failed to get adrstn\n");
|
||||
return PTR_ERR(adc->adrstn);
|
||||
}
|
||||
|
||||
adc->presetn = devm_reset_control_get_exclusive(dev, "presetn");
|
||||
if (IS_ERR(adc->presetn)) {
|
||||
dev_err(dev, "failed to get presetn\n");
|
||||
return PTR_ERR(adc->presetn);
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(adc->adrstn);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to deassert adrstn pin, %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_add_action_or_reset(&pdev->dev,
|
||||
rzg2l_adc_reset_assert, adc->adrstn);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register adrstn assert devm action, %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = reset_control_deassert(adc->presetn);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to deassert presetn pin, %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_add_action_or_reset(&pdev->dev,
|
||||
rzg2l_adc_reset_assert, adc->presetn);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to register presetn assert devm action, %d\n",
|
||||
ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = rzg2l_adc_hw_init(adc);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "failed to initialize ADC HW, %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(dev, "no irq resource\n");
|
||||
return irq;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(dev, irq, rzg2l_adc_isr,
|
||||
0, dev_name(dev), adc);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
init_completion(&adc->completion);
|
||||
|
||||
platform_set_drvdata(pdev, indio_dev);
|
||||
|
||||
indio_dev->name = DRIVER_NAME;
|
||||
indio_dev->info = &rzg2l_adc_iio_info;
|
||||
indio_dev->modes = INDIO_DIRECT_MODE;
|
||||
indio_dev->channels = adc->data->channels;
|
||||
indio_dev->num_channels = adc->data->num_channels;
|
||||
|
||||
pm_runtime_set_suspended(dev);
|
||||
ret = devm_add_action_or_reset(&pdev->dev,
|
||||
rzg2l_adc_pm_runtime_set_suspended, &indio_dev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pm_runtime_enable(dev);
|
||||
ret = devm_add_action_or_reset(&pdev->dev,
|
||||
rzg2l_adc_pm_runtime_disable, &indio_dev->dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return devm_iio_device_register(dev, indio_dev);
|
||||
}
|
||||
|
||||
static const struct of_device_id rzg2l_adc_match[] = {
|
||||
{ .compatible = "renesas,rzg2l-adc",},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rzg2l_adc_match);
|
||||
|
||||
static int __maybe_unused rzg2l_adc_pm_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
||||
struct rzg2l_adc *adc = iio_priv(indio_dev);
|
||||
|
||||
rzg2l_adc_pwr(adc, false);
|
||||
clk_disable_unprepare(adc->adclk);
|
||||
clk_disable_unprepare(adc->pclk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __maybe_unused rzg2l_adc_pm_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct iio_dev *indio_dev = dev_get_drvdata(dev);
|
||||
struct rzg2l_adc *adc = iio_priv(indio_dev);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(adc->pclk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = clk_prepare_enable(adc->adclk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
rzg2l_adc_pwr(adc, true);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dev_pm_ops rzg2l_adc_pm_ops = {
|
||||
SET_RUNTIME_PM_OPS(rzg2l_adc_pm_runtime_suspend,
|
||||
rzg2l_adc_pm_runtime_resume,
|
||||
NULL)
|
||||
};
|
||||
|
||||
static struct platform_driver rzg2l_adc_driver = {
|
||||
.probe = rzg2l_adc_probe,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.of_match_table = rzg2l_adc_match,
|
||||
.pm = &rzg2l_adc_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(rzg2l_adc_driver);
|
||||
|
||||
MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
|
||||
MODULE_DESCRIPTION("Renesas RZ/G2L ADC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
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