Staging: sep: remove driver
It's currently stalled and the original submitter recommended that it just be dropped at this point in time due. Cc: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Greg Kroah-Hartman
Родитель
f86b998425
Коммит
d49824c067
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@ -113,8 +113,6 @@ source "drivers/staging/vme/Kconfig"
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source "drivers/staging/memrar/Kconfig"
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source "drivers/staging/memrar/Kconfig"
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source "drivers/staging/sep/Kconfig"
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source "drivers/staging/iio/Kconfig"
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source "drivers/staging/iio/Kconfig"
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source "drivers/staging/zram/Kconfig"
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source "drivers/staging/zram/Kconfig"
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@ -38,7 +38,6 @@ obj-$(CONFIG_FB_UDL) += udlfb/
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obj-$(CONFIG_HYPERV) += hv/
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obj-$(CONFIG_HYPERV) += hv/
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obj-$(CONFIG_VME_BUS) += vme/
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obj-$(CONFIG_VME_BUS) += vme/
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obj-$(CONFIG_MRST_RAR_HANDLER) += memrar/
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obj-$(CONFIG_MRST_RAR_HANDLER) += memrar/
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obj-$(CONFIG_DX_SEP) += sep/
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obj-$(CONFIG_IIO) += iio/
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obj-$(CONFIG_IIO) += iio/
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obj-$(CONFIG_ZRAM) += zram/
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obj-$(CONFIG_ZRAM) += zram/
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obj-$(CONFIG_WLAGS49_H2) += wlags49_h2/
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obj-$(CONFIG_WLAGS49_H2) += wlags49_h2/
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@ -1,10 +0,0 @@
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config DX_SEP
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tristate "Discretix SEP driver"
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# depends on MRST
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depends on RAR_REGISTER && PCI
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default y
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help
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Discretix SEP driver
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If unsure say M. The compiled module will be
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called sep_driver.ko
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@ -1,2 +0,0 @@
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obj-$(CONFIG_DX_SEP) := sep_driver.o
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@ -1,8 +0,0 @@
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Todo's so far (from Alan Cox)
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- Fix firmware loading
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- Get firmware into firmware git tree
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- Review and tidy each algorithm function
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- Check whether it can be plugged into any of the kernel crypto API
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interfaces
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- Do something about the magic shared memory interface and replace it
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with something saner (in Linux terms)
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@ -1,110 +0,0 @@
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#ifndef __SEP_DEV_H__
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#define __SEP_DEV_H__
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/*
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*
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* sep_dev.h - Security Processor Device Structures
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*
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* Copyright(c) 2009 Intel Corporation. All rights reserved.
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* Copyright(c) 2009 Discretix. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* CONTACTS:
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*
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* Alan Cox alan@linux.intel.com
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*
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*/
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struct sep_device {
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/* pointer to pci dev */
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struct pci_dev *pdev;
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unsigned long in_use;
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/* address of the shared memory allocated during init for SEP driver
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(coherent alloc) */
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void *shared_addr;
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/* the physical address of the shared area */
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dma_addr_t shared_bus;
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/* restricted access region (coherent alloc) */
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dma_addr_t rar_bus;
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void *rar_addr;
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/* firmware regions: cache is at rar_addr */
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unsigned long cache_size;
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/* follows the cache */
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dma_addr_t resident_bus;
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unsigned long resident_size;
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void *resident_addr;
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/* start address of the access to the SEP registers from driver */
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void __iomem *reg_addr;
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/* transaction counter that coordinates the transactions between SEP and HOST */
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unsigned long send_ct;
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/* counter for the messages from sep */
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unsigned long reply_ct;
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/* counter for the number of bytes allocated in the pool for the current
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transaction */
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unsigned long data_pool_bytes_allocated;
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/* array of pointers to the pages that represent input data for the synchronic
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DMA action */
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struct page **in_page_array;
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/* array of pointers to the pages that represent out data for the synchronic
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DMA action */
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struct page **out_page_array;
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/* number of pages in the sep_in_page_array */
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unsigned long in_num_pages;
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/* number of pages in the sep_out_page_array */
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unsigned long out_num_pages;
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/* global data for every flow */
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struct sep_flow_context_t flows[SEP_DRIVER_NUM_FLOWS];
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/* pointer to the workqueue that handles the flow done interrupts */
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struct workqueue_struct *flow_wq;
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};
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static struct sep_device *sep_dev;
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static inline void sep_write_reg(struct sep_device *dev, int reg, u32 value)
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{
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void __iomem *addr = dev->reg_addr + reg;
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writel(value, addr);
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}
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static inline u32 sep_read_reg(struct sep_device *dev, int reg)
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{
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void __iomem *addr = dev->reg_addr + reg;
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return readl(addr);
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}
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/* wait for SRAM write complete(indirect write */
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static inline void sep_wait_sram_write(struct sep_device *dev)
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{
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u32 reg_val;
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do
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reg_val = sep_read_reg(dev, HW_SRAM_DATA_READY_REG_ADDR);
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while (!(reg_val & 1));
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}
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#endif
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -1,425 +0,0 @@
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/*
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*
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* sep_driver_api.h - Security Processor Driver api definitions
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*
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* Copyright(c) 2009 Intel Corporation. All rights reserved.
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* Copyright(c) 2009 Discretix. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* CONTACTS:
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*
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* Mark Allyn mark.a.allyn@intel.com
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*
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* CHANGES:
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*
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* 2009.06.26 Initial publish
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*
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*/
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#ifndef __SEP_DRIVER_API_H__
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#define __SEP_DRIVER_API_H__
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/*----------------------------------------------------------------
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IOCTL command defines
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-----------------------------------------------------------------*/
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/* magic number 1 of the sep IOCTL command */
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#define SEP_IOC_MAGIC_NUMBER 's'
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/* sends interrupt to sep that message is ready */
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#define SEP_IOCSENDSEPCOMMAND _IO(SEP_IOC_MAGIC_NUMBER , 0)
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/* sends interrupt to sep that message is ready */
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#define SEP_IOCSENDSEPRPLYCOMMAND _IO(SEP_IOC_MAGIC_NUMBER , 1)
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/* allocate memory in data pool */
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#define SEP_IOCALLOCDATAPOLL _IO(SEP_IOC_MAGIC_NUMBER , 2)
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/* write to pre-allocated memory in data pool */
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#define SEP_IOCWRITEDATAPOLL _IO(SEP_IOC_MAGIC_NUMBER , 3)
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/* read from pre-allocated memory in data pool */
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#define SEP_IOCREADDATAPOLL _IO(SEP_IOC_MAGIC_NUMBER , 4)
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/* create sym dma lli tables */
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#define SEP_IOCCREATESYMDMATABLE _IO(SEP_IOC_MAGIC_NUMBER , 5)
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/* create flow dma lli tables */
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#define SEP_IOCCREATEFLOWDMATABLE _IO(SEP_IOC_MAGIC_NUMBER , 6)
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/* free dynamic data aalocated during table creation */
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#define SEP_IOCFREEDMATABLEDATA _IO(SEP_IOC_MAGIC_NUMBER , 7)
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/* get the static pool area addresses (physical and virtual) */
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#define SEP_IOCGETSTATICPOOLADDR _IO(SEP_IOC_MAGIC_NUMBER , 8)
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/* set flow id command */
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#define SEP_IOCSETFLOWID _IO(SEP_IOC_MAGIC_NUMBER , 9)
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/* add tables to the dynamic flow */
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#define SEP_IOCADDFLOWTABLE _IO(SEP_IOC_MAGIC_NUMBER , 10)
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/* add flow add tables message */
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#define SEP_IOCADDFLOWMESSAGE _IO(SEP_IOC_MAGIC_NUMBER , 11)
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/* start sep command */
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#define SEP_IOCSEPSTART _IO(SEP_IOC_MAGIC_NUMBER , 12)
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/* init sep command */
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#define SEP_IOCSEPINIT _IO(SEP_IOC_MAGIC_NUMBER , 13)
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/* end transaction command */
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#define SEP_IOCENDTRANSACTION _IO(SEP_IOC_MAGIC_NUMBER , 15)
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/* reallocate cache and resident */
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#define SEP_IOCREALLOCCACHERES _IO(SEP_IOC_MAGIC_NUMBER , 16)
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/* get the offset of the address starting from the beginnnig of the map area */
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#define SEP_IOCGETMAPPEDADDROFFSET _IO(SEP_IOC_MAGIC_NUMBER , 17)
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/* get time address and value */
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#define SEP_IOCGETIME _IO(SEP_IOC_MAGIC_NUMBER , 19)
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/*-------------------------------------------
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TYPEDEFS
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----------------------------------------------*/
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/*
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init command struct
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*/
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struct sep_driver_init_t {
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/* start of the 1G of the host memory address that SEP can access */
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unsigned long message_addr;
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/* start address of resident */
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unsigned long message_size_in_words;
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};
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/*
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realloc cache resident command
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*/
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struct sep_driver_realloc_cache_resident_t {
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/* new cache address */
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u64 new_cache_addr;
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/* new resident address */
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u64 new_resident_addr;
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/* new resident address */
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u64 new_shared_area_addr;
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/* new base address */
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u64 new_base_addr;
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};
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struct sep_driver_alloc_t {
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/* virtual address of allocated space */
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unsigned long offset;
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/* physical address of allocated space */
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unsigned long phys_address;
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/* number of bytes to allocate */
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unsigned long num_bytes;
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};
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/*
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*/
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struct sep_driver_write_t {
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/* application space address */
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unsigned long app_address;
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/* address of the data pool */
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unsigned long datapool_address;
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/* number of bytes to write */
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unsigned long num_bytes;
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};
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/*
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*/
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struct sep_driver_read_t {
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/* application space address */
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unsigned long app_address;
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/* address of the data pool */
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unsigned long datapool_address;
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/* number of bytes to read */
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unsigned long num_bytes;
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};
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/*
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*/
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struct sep_driver_build_sync_table_t {
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/* address value of the data in */
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unsigned long app_in_address;
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/* size of data in */
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unsigned long data_in_size;
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/* address of the data out */
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unsigned long app_out_address;
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/* the size of the block of the operation - if needed,
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every table will be modulo this parameter */
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unsigned long block_size;
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/* the physical address of the first input DMA table */
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unsigned long in_table_address;
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/* number of entries in the first input DMA table */
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unsigned long in_table_num_entries;
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/* the physical address of the first output DMA table */
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unsigned long out_table_address;
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/* number of entries in the first output DMA table */
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unsigned long out_table_num_entries;
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/* data in the first input table */
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unsigned long table_data_size;
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/* distinct user/kernel layout */
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bool isKernelVirtualAddress;
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};
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/*
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*/
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struct sep_driver_build_flow_table_t {
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/* flow type */
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unsigned long flow_type;
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/* flag for input output */
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unsigned long input_output_flag;
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/* address value of the data in */
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unsigned long virt_buff_data_addr;
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/* size of data in */
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unsigned long num_virtual_buffers;
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/* the physical address of the first input DMA table */
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unsigned long first_table_addr;
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/* number of entries in the first input DMA table */
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unsigned long first_table_num_entries;
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/* data in the first input table */
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unsigned long first_table_data_size;
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/* distinct user/kernel layout */
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bool isKernelVirtualAddress;
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};
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struct sep_driver_add_flow_table_t {
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/* flow id */
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unsigned long flow_id;
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/* flag for input output */
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unsigned long inputOutputFlag;
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/* address value of the data in */
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unsigned long virt_buff_data_addr;
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/* size of data in */
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unsigned long num_virtual_buffers;
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/* address of the first table */
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unsigned long first_table_addr;
|
|
||||||
|
|
||||||
/* number of entries in the first table */
|
|
||||||
unsigned long first_table_num_entries;
|
|
||||||
|
|
||||||
/* data size of the first table */
|
|
||||||
unsigned long first_table_data_size;
|
|
||||||
|
|
||||||
/* distinct user/kernel layout */
|
|
||||||
bool isKernelVirtualAddress;
|
|
||||||
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
command struct for set flow id
|
|
||||||
*/
|
|
||||||
struct sep_driver_set_flow_id_t {
|
|
||||||
/* flow id to set */
|
|
||||||
unsigned long flow_id;
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
/* command struct for add tables message */
|
|
||||||
struct sep_driver_add_message_t {
|
|
||||||
/* flow id to set */
|
|
||||||
unsigned long flow_id;
|
|
||||||
|
|
||||||
/* message size in bytes */
|
|
||||||
unsigned long message_size_in_bytes;
|
|
||||||
|
|
||||||
/* address of the message */
|
|
||||||
unsigned long message_address;
|
|
||||||
};
|
|
||||||
|
|
||||||
/* command struct for static pool addresses */
|
|
||||||
struct sep_driver_static_pool_addr_t {
|
|
||||||
/* physical address of the static pool */
|
|
||||||
unsigned long physical_static_address;
|
|
||||||
|
|
||||||
/* virtual address of the static pool */
|
|
||||||
unsigned long virtual_static_address;
|
|
||||||
};
|
|
||||||
|
|
||||||
/* command struct for getiing offset of the physical address from
|
|
||||||
the start of the mapped area */
|
|
||||||
struct sep_driver_get_mapped_offset_t {
|
|
||||||
/* physical address of the static pool */
|
|
||||||
unsigned long physical_address;
|
|
||||||
|
|
||||||
/* virtual address of the static pool */
|
|
||||||
unsigned long offset;
|
|
||||||
};
|
|
||||||
|
|
||||||
/* command struct for getting time value and address */
|
|
||||||
struct sep_driver_get_time_t {
|
|
||||||
/* physical address of stored time */
|
|
||||||
unsigned long time_physical_address;
|
|
||||||
|
|
||||||
/* value of the stored time */
|
|
||||||
unsigned long time_value;
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
structure that represent one entry in the DMA LLI table
|
|
||||||
*/
|
|
||||||
struct sep_lli_entry_t {
|
|
||||||
/* physical address */
|
|
||||||
unsigned long physical_address;
|
|
||||||
|
|
||||||
/* block size */
|
|
||||||
unsigned long block_size;
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
structure that reperesents data needed for lli table construction
|
|
||||||
*/
|
|
||||||
struct sep_lli_prepare_table_data_t {
|
|
||||||
/* pointer to the memory where the first lli entry to be built */
|
|
||||||
struct sep_lli_entry_t *lli_entry_ptr;
|
|
||||||
|
|
||||||
/* pointer to the array of lli entries from which the table is to be built */
|
|
||||||
struct sep_lli_entry_t *lli_array_ptr;
|
|
||||||
|
|
||||||
/* number of elements in lli array */
|
|
||||||
int lli_array_size;
|
|
||||||
|
|
||||||
/* number of entries in the created table */
|
|
||||||
int num_table_entries;
|
|
||||||
|
|
||||||
/* number of array entries processed during table creation */
|
|
||||||
int num_array_entries_processed;
|
|
||||||
|
|
||||||
/* the totatl data size in the created table */
|
|
||||||
int lli_table_total_data_size;
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
structure that represent tone table - it is not used in code, jkust
|
|
||||||
to show what table looks like
|
|
||||||
*/
|
|
||||||
struct sep_lli_table_t {
|
|
||||||
/* number of pages mapped in this tables. If 0 - means that the table
|
|
||||||
is not defined (used as a valid flag) */
|
|
||||||
unsigned long num_pages;
|
|
||||||
/*
|
|
||||||
pointer to array of page pointers that represent the mapping of the
|
|
||||||
virtual buffer defined by the table to the physical memory. If this
|
|
||||||
pointer is NULL, it means that the table is not defined
|
|
||||||
(used as a valid flag)
|
|
||||||
*/
|
|
||||||
struct page **table_page_array_ptr;
|
|
||||||
|
|
||||||
/* maximum flow entries in table */
|
|
||||||
struct sep_lli_entry_t lli_entries[SEP_DRIVER_MAX_FLOW_NUM_ENTRIES_IN_TABLE];
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
structure for keeping the mapping of the virtual buffer into physical pages
|
|
||||||
*/
|
|
||||||
struct sep_flow_buffer_data {
|
|
||||||
/* pointer to the array of page structs pointers to the pages of the
|
|
||||||
virtual buffer */
|
|
||||||
struct page **page_array_ptr;
|
|
||||||
|
|
||||||
/* number of pages taken by the virtual buffer */
|
|
||||||
unsigned long num_pages;
|
|
||||||
|
|
||||||
/* this flag signals if this page_array is the last one among many that were
|
|
||||||
sent in one setting to SEP */
|
|
||||||
unsigned long last_page_array_flag;
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
struct that keeps all the data for one flow
|
|
||||||
*/
|
|
||||||
struct sep_flow_context_t {
|
|
||||||
/*
|
|
||||||
work struct for handling the flow done interrupt in the workqueue
|
|
||||||
this structure must be in the first place, since it will be used
|
|
||||||
forcasting to the containing flow context
|
|
||||||
*/
|
|
||||||
struct work_struct flow_wq;
|
|
||||||
|
|
||||||
/* flow id */
|
|
||||||
unsigned long flow_id;
|
|
||||||
|
|
||||||
/* additional input tables exists */
|
|
||||||
unsigned long input_tables_flag;
|
|
||||||
|
|
||||||
/* additional output tables exists */
|
|
||||||
unsigned long output_tables_flag;
|
|
||||||
|
|
||||||
/* data of the first input file */
|
|
||||||
struct sep_lli_entry_t first_input_table;
|
|
||||||
|
|
||||||
/* data of the first output table */
|
|
||||||
struct sep_lli_entry_t first_output_table;
|
|
||||||
|
|
||||||
/* last input table data */
|
|
||||||
struct sep_lli_entry_t last_input_table;
|
|
||||||
|
|
||||||
/* last output table data */
|
|
||||||
struct sep_lli_entry_t last_output_table;
|
|
||||||
|
|
||||||
/* first list of table */
|
|
||||||
struct sep_lli_entry_t input_tables_in_process;
|
|
||||||
|
|
||||||
/* output table in process (in sep) */
|
|
||||||
struct sep_lli_entry_t output_tables_in_process;
|
|
||||||
|
|
||||||
/* size of messages in bytes */
|
|
||||||
unsigned long message_size_in_bytes;
|
|
||||||
|
|
||||||
/* message */
|
|
||||||
unsigned char message[SEP_MAX_ADD_MESSAGE_LENGTH_IN_BYTES];
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,225 +0,0 @@
|
||||||
/*
|
|
||||||
*
|
|
||||||
* sep_driver_config.h - Security Processor Driver configuration
|
|
||||||
*
|
|
||||||
* Copyright(c) 2009 Intel Corporation. All rights reserved.
|
|
||||||
* Copyright(c) 2009 Discretix. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of the GNU General Public License as published by the Free
|
|
||||||
* Software Foundation; either version 2 of the License, or (at your option)
|
|
||||||
* any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
|
||||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
||||||
* more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along with
|
|
||||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
|
||||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
|
||||||
*
|
|
||||||
* CONTACTS:
|
|
||||||
*
|
|
||||||
* Mark Allyn mark.a.allyn@intel.com
|
|
||||||
*
|
|
||||||
* CHANGES:
|
|
||||||
*
|
|
||||||
* 2009.06.26 Initial publish
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __SEP_DRIVER_CONFIG_H__
|
|
||||||
#define __SEP_DRIVER_CONFIG_H__
|
|
||||||
|
|
||||||
|
|
||||||
/*--------------------------------------
|
|
||||||
DRIVER CONFIGURATION FLAGS
|
|
||||||
-------------------------------------*/
|
|
||||||
|
|
||||||
/* if flag is on , then the driver is running in polling and
|
|
||||||
not interrupt mode */
|
|
||||||
#define SEP_DRIVER_POLLING_MODE 1
|
|
||||||
|
|
||||||
/* flag which defines if the shared area address should be
|
|
||||||
reconfiged (send to SEP anew) during init of the driver */
|
|
||||||
#define SEP_DRIVER_RECONFIG_MESSAGE_AREA 0
|
|
||||||
|
|
||||||
/* the mode for running on the ARM1172 Evaluation platform (flag is 1) */
|
|
||||||
#define SEP_DRIVER_ARM_DEBUG_MODE 0
|
|
||||||
|
|
||||||
/*-------------------------------------------
|
|
||||||
INTERNAL DATA CONFIGURATION
|
|
||||||
-------------------------------------------*/
|
|
||||||
|
|
||||||
/* flag for the input array */
|
|
||||||
#define SEP_DRIVER_IN_FLAG 0
|
|
||||||
|
|
||||||
/* flag for output array */
|
|
||||||
#define SEP_DRIVER_OUT_FLAG 1
|
|
||||||
|
|
||||||
/* maximum number of entries in one LLI tables */
|
|
||||||
#define SEP_DRIVER_ENTRIES_PER_TABLE_IN_SEP 8
|
|
||||||
|
|
||||||
|
|
||||||
/*--------------------------------------------------------
|
|
||||||
SHARED AREA memory total size is 36K
|
|
||||||
it is divided is following:
|
|
||||||
|
|
||||||
SHARED_MESSAGE_AREA 8K }
|
|
||||||
}
|
|
||||||
STATIC_POOL_AREA 4K } MAPPED AREA ( 24 K)
|
|
||||||
}
|
|
||||||
DATA_POOL_AREA 12K }
|
|
||||||
|
|
||||||
SYNCHRONIC_DMA_TABLES_AREA 5K
|
|
||||||
|
|
||||||
FLOW_DMA_TABLES_AREA 4K
|
|
||||||
|
|
||||||
SYSTEM_MEMORY_AREA 3k
|
|
||||||
|
|
||||||
SYSTEM_MEMORY total size is 3k
|
|
||||||
it is divided as following:
|
|
||||||
|
|
||||||
TIME_MEMORY_AREA 8B
|
|
||||||
-----------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
the maximum length of the message - the rest of the message shared
|
|
||||||
area will be dedicated to the dma lli tables
|
|
||||||
*/
|
|
||||||
#define SEP_DRIVER_MAX_MESSAGE_SIZE_IN_BYTES (8 * 1024)
|
|
||||||
|
|
||||||
/* the size of the message shared area in pages */
|
|
||||||
#define SEP_DRIVER_MESSAGE_SHARED_AREA_SIZE_IN_BYTES (8 * 1024)
|
|
||||||
|
|
||||||
/* the size of the data pool static area in pages */
|
|
||||||
#define SEP_DRIVER_STATIC_AREA_SIZE_IN_BYTES (4 * 1024)
|
|
||||||
|
|
||||||
/* the size of the data pool shared area size in pages */
|
|
||||||
#define SEP_DRIVER_DATA_POOL_SHARED_AREA_SIZE_IN_BYTES (12 * 1024)
|
|
||||||
|
|
||||||
/* the size of the message shared area in pages */
|
|
||||||
#define SEP_DRIVER_SYNCHRONIC_DMA_TABLES_AREA_SIZE_IN_BYTES (1024 * 5)
|
|
||||||
|
|
||||||
|
|
||||||
/* the size of the data pool shared area size in pages */
|
|
||||||
#define SEP_DRIVER_FLOW_DMA_TABLES_AREA_SIZE_IN_BYTES (1024 * 4)
|
|
||||||
|
|
||||||
/* system data (time, caller id etc') pool */
|
|
||||||
#define SEP_DRIVER_SYSTEM_DATA_MEMORY_SIZE_IN_BYTES 100
|
|
||||||
|
|
||||||
|
|
||||||
/* area size that is mapped - we map the MESSAGE AREA, STATIC POOL and
|
|
||||||
DATA POOL areas. area must be module 4k */
|
|
||||||
#define SEP_DRIVER_MMMAP_AREA_SIZE (1024 * 24)
|
|
||||||
|
|
||||||
|
|
||||||
/*-----------------------------------------------
|
|
||||||
offsets of the areas starting from the shared area start address
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* message area offset */
|
|
||||||
#define SEP_DRIVER_MESSAGE_AREA_OFFSET_IN_BYTES 0
|
|
||||||
|
|
||||||
/* static pool area offset */
|
|
||||||
#define SEP_DRIVER_STATIC_AREA_OFFSET_IN_BYTES \
|
|
||||||
(SEP_DRIVER_MESSAGE_SHARED_AREA_SIZE_IN_BYTES)
|
|
||||||
|
|
||||||
/* data pool area offset */
|
|
||||||
#define SEP_DRIVER_DATA_POOL_AREA_OFFSET_IN_BYTES \
|
|
||||||
(SEP_DRIVER_STATIC_AREA_OFFSET_IN_BYTES + \
|
|
||||||
SEP_DRIVER_STATIC_AREA_SIZE_IN_BYTES)
|
|
||||||
|
|
||||||
/* synhronic dma tables area offset */
|
|
||||||
#define SEP_DRIVER_SYNCHRONIC_DMA_TABLES_AREA_OFFSET_IN_BYTES \
|
|
||||||
(SEP_DRIVER_DATA_POOL_AREA_OFFSET_IN_BYTES + \
|
|
||||||
SEP_DRIVER_DATA_POOL_SHARED_AREA_SIZE_IN_BYTES)
|
|
||||||
|
|
||||||
/* sep driver flow dma tables area offset */
|
|
||||||
#define SEP_DRIVER_FLOW_DMA_TABLES_AREA_OFFSET_IN_BYTES \
|
|
||||||
(SEP_DRIVER_SYNCHRONIC_DMA_TABLES_AREA_OFFSET_IN_BYTES + \
|
|
||||||
SEP_DRIVER_SYNCHRONIC_DMA_TABLES_AREA_SIZE_IN_BYTES)
|
|
||||||
|
|
||||||
/* system memory offset in bytes */
|
|
||||||
#define SEP_DRIVER_SYSTEM_DATA_MEMORY_OFFSET_IN_BYTES \
|
|
||||||
(SEP_DRIVER_FLOW_DMA_TABLES_AREA_OFFSET_IN_BYTES + \
|
|
||||||
SEP_DRIVER_FLOW_DMA_TABLES_AREA_SIZE_IN_BYTES)
|
|
||||||
|
|
||||||
/* offset of the time area */
|
|
||||||
#define SEP_DRIVER_SYSTEM_TIME_MEMORY_OFFSET_IN_BYTES \
|
|
||||||
(SEP_DRIVER_SYSTEM_DATA_MEMORY_OFFSET_IN_BYTES)
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
/* start physical address of the SEP registers memory in HOST */
|
|
||||||
#define SEP_IO_MEM_REGION_START_ADDRESS 0x80000000
|
|
||||||
|
|
||||||
/* size of the SEP registers memory region in HOST (for now 100 registers) */
|
|
||||||
#define SEP_IO_MEM_REGION_SIZE (2 * 0x100000)
|
|
||||||
|
|
||||||
/* define the number of IRQ for SEP interrupts */
|
|
||||||
#define SEP_DIRVER_IRQ_NUM 1
|
|
||||||
|
|
||||||
/* maximum number of add buffers */
|
|
||||||
#define SEP_MAX_NUM_ADD_BUFFERS 100
|
|
||||||
|
|
||||||
/* number of flows */
|
|
||||||
#define SEP_DRIVER_NUM_FLOWS 4
|
|
||||||
|
|
||||||
/* maximum number of entries in flow table */
|
|
||||||
#define SEP_DRIVER_MAX_FLOW_NUM_ENTRIES_IN_TABLE 25
|
|
||||||
|
|
||||||
/* offset of the num entries in the block length entry of the LLI */
|
|
||||||
#define SEP_NUM_ENTRIES_OFFSET_IN_BITS 24
|
|
||||||
|
|
||||||
/* offset of the interrupt flag in the block length entry of the LLI */
|
|
||||||
#define SEP_INT_FLAG_OFFSET_IN_BITS 31
|
|
||||||
|
|
||||||
/* mask for extracting data size from LLI */
|
|
||||||
#define SEP_TABLE_DATA_SIZE_MASK 0xFFFFFF
|
|
||||||
|
|
||||||
/* mask for entries after being shifted left */
|
|
||||||
#define SEP_NUM_ENTRIES_MASK 0x7F
|
|
||||||
|
|
||||||
/* default flow id */
|
|
||||||
#define SEP_FREE_FLOW_ID 0xFFFFFFFF
|
|
||||||
|
|
||||||
/* temp flow id used during cretiong of new flow until receiving
|
|
||||||
real flow id from sep */
|
|
||||||
#define SEP_TEMP_FLOW_ID (SEP_DRIVER_NUM_FLOWS + 1)
|
|
||||||
|
|
||||||
/* maximum add buffers message length in bytes */
|
|
||||||
#define SEP_MAX_ADD_MESSAGE_LENGTH_IN_BYTES (7 * 4)
|
|
||||||
|
|
||||||
/* maximum number of concurrent virtual buffers */
|
|
||||||
#define SEP_MAX_VIRT_BUFFERS_CONCURRENT 100
|
|
||||||
|
|
||||||
/* the token that defines the start of time address */
|
|
||||||
#define SEP_TIME_VAL_TOKEN 0x12345678
|
|
||||||
|
|
||||||
/* DEBUG LEVEL MASKS */
|
|
||||||
#define SEP_DEBUG_LEVEL_BASIC 0x1
|
|
||||||
|
|
||||||
#define SEP_DEBUG_LEVEL_EXTENDED 0x4
|
|
||||||
|
|
||||||
|
|
||||||
/* Debug helpers */
|
|
||||||
|
|
||||||
#define dbg(fmt, args...) \
|
|
||||||
do {\
|
|
||||||
if (debug & SEP_DEBUG_LEVEL_BASIC) \
|
|
||||||
printk(KERN_DEBUG fmt, ##args); \
|
|
||||||
} while(0);
|
|
||||||
|
|
||||||
#define edbg(fmt, args...) \
|
|
||||||
do { \
|
|
||||||
if (debug & SEP_DEBUG_LEVEL_EXTENDED) \
|
|
||||||
printk(KERN_DEBUG fmt, ##args); \
|
|
||||||
} while(0);
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,232 +0,0 @@
|
||||||
/*
|
|
||||||
*
|
|
||||||
* sep_driver_hw_defs.h - Security Processor Driver hardware definitions
|
|
||||||
*
|
|
||||||
* Copyright(c) 2009 Intel Corporation. All rights reserved.
|
|
||||||
* Copyright(c) 2009 Discretix. All rights reserved.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or modify it
|
|
||||||
* under the terms of the GNU General Public License as published by the Free
|
|
||||||
* Software Foundation; either version 2 of the License, or (at your option)
|
|
||||||
* any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
|
||||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
||||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
||||||
* more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License along with
|
|
||||||
* this program; if not, write to the Free Software Foundation, Inc., 59
|
|
||||||
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
|
||||||
*
|
|
||||||
* CONTACTS:
|
|
||||||
*
|
|
||||||
* Mark Allyn mark.a.allyn@intel.com
|
|
||||||
*
|
|
||||||
* CHANGES:
|
|
||||||
*
|
|
||||||
* 2009.06.26 Initial publish
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef SEP_DRIVER_HW_DEFS__H
|
|
||||||
#define SEP_DRIVER_HW_DEFS__H
|
|
||||||
|
|
||||||
/*--------------------------------------------------------------------------*/
|
|
||||||
/* Abstract: HW Registers Defines. */
|
|
||||||
/* */
|
|
||||||
/* Note: This file was automatically created !!! */
|
|
||||||
/* DO NOT EDIT THIS FILE !!! */
|
|
||||||
/*--------------------------------------------------------------------------*/
|
|
||||||
|
|
||||||
|
|
||||||
/* cf registers */
|
|
||||||
#define HW_R0B_ADDR_0_REG_ADDR 0x0000UL
|
|
||||||
#define HW_R0B_ADDR_1_REG_ADDR 0x0004UL
|
|
||||||
#define HW_R0B_ADDR_2_REG_ADDR 0x0008UL
|
|
||||||
#define HW_R0B_ADDR_3_REG_ADDR 0x000cUL
|
|
||||||
#define HW_R0B_ADDR_4_REG_ADDR 0x0010UL
|
|
||||||
#define HW_R0B_ADDR_5_REG_ADDR 0x0014UL
|
|
||||||
#define HW_R0B_ADDR_6_REG_ADDR 0x0018UL
|
|
||||||
#define HW_R0B_ADDR_7_REG_ADDR 0x001cUL
|
|
||||||
#define HW_R0B_ADDR_8_REG_ADDR 0x0020UL
|
|
||||||
#define HW_R2B_ADDR_0_REG_ADDR 0x0080UL
|
|
||||||
#define HW_R2B_ADDR_1_REG_ADDR 0x0084UL
|
|
||||||
#define HW_R2B_ADDR_2_REG_ADDR 0x0088UL
|
|
||||||
#define HW_R2B_ADDR_3_REG_ADDR 0x008cUL
|
|
||||||
#define HW_R2B_ADDR_4_REG_ADDR 0x0090UL
|
|
||||||
#define HW_R2B_ADDR_5_REG_ADDR 0x0094UL
|
|
||||||
#define HW_R2B_ADDR_6_REG_ADDR 0x0098UL
|
|
||||||
#define HW_R2B_ADDR_7_REG_ADDR 0x009cUL
|
|
||||||
#define HW_R2B_ADDR_8_REG_ADDR 0x00a0UL
|
|
||||||
#define HW_R3B_REG_ADDR 0x00C0UL
|
|
||||||
#define HW_R4B_REG_ADDR 0x0100UL
|
|
||||||
#define HW_CSA_ADDR_0_REG_ADDR 0x0140UL
|
|
||||||
#define HW_CSA_ADDR_1_REG_ADDR 0x0144UL
|
|
||||||
#define HW_CSA_ADDR_2_REG_ADDR 0x0148UL
|
|
||||||
#define HW_CSA_ADDR_3_REG_ADDR 0x014cUL
|
|
||||||
#define HW_CSA_ADDR_4_REG_ADDR 0x0150UL
|
|
||||||
#define HW_CSA_ADDR_5_REG_ADDR 0x0154UL
|
|
||||||
#define HW_CSA_ADDR_6_REG_ADDR 0x0158UL
|
|
||||||
#define HW_CSA_ADDR_7_REG_ADDR 0x015cUL
|
|
||||||
#define HW_CSA_ADDR_8_REG_ADDR 0x0160UL
|
|
||||||
#define HW_CSA_REG_ADDR 0x0140UL
|
|
||||||
#define HW_SINB_REG_ADDR 0x0180UL
|
|
||||||
#define HW_SOUTB_REG_ADDR 0x0184UL
|
|
||||||
#define HW_PKI_CONTROL_REG_ADDR 0x01C0UL
|
|
||||||
#define HW_PKI_STATUS_REG_ADDR 0x01C4UL
|
|
||||||
#define HW_PKI_BUSY_REG_ADDR 0x01C8UL
|
|
||||||
#define HW_PKI_A_1025_REG_ADDR 0x01CCUL
|
|
||||||
#define HW_PKI_SDMA_CTL_REG_ADDR 0x01D0UL
|
|
||||||
#define HW_PKI_SDMA_OFFSET_REG_ADDR 0x01D4UL
|
|
||||||
#define HW_PKI_SDMA_POINTERS_REG_ADDR 0x01D8UL
|
|
||||||
#define HW_PKI_SDMA_DLENG_REG_ADDR 0x01DCUL
|
|
||||||
#define HW_PKI_SDMA_EXP_POINTERS_REG_ADDR 0x01E0UL
|
|
||||||
#define HW_PKI_SDMA_RES_POINTERS_REG_ADDR 0x01E4UL
|
|
||||||
#define HW_PKI_CLR_REG_ADDR 0x01E8UL
|
|
||||||
#define HW_PKI_SDMA_BUSY_REG_ADDR 0x01E8UL
|
|
||||||
#define HW_PKI_SDMA_FIRST_EXP_N_REG_ADDR 0x01ECUL
|
|
||||||
#define HW_PKI_SDMA_MUL_BY1_REG_ADDR 0x01F0UL
|
|
||||||
#define HW_PKI_SDMA_RMUL_SEL_REG_ADDR 0x01F4UL
|
|
||||||
#define HW_DES_KEY_0_REG_ADDR 0x0208UL
|
|
||||||
#define HW_DES_KEY_1_REG_ADDR 0x020CUL
|
|
||||||
#define HW_DES_KEY_2_REG_ADDR 0x0210UL
|
|
||||||
#define HW_DES_KEY_3_REG_ADDR 0x0214UL
|
|
||||||
#define HW_DES_KEY_4_REG_ADDR 0x0218UL
|
|
||||||
#define HW_DES_KEY_5_REG_ADDR 0x021CUL
|
|
||||||
#define HW_DES_CONTROL_0_REG_ADDR 0x0220UL
|
|
||||||
#define HW_DES_CONTROL_1_REG_ADDR 0x0224UL
|
|
||||||
#define HW_DES_IV_0_REG_ADDR 0x0228UL
|
|
||||||
#define HW_DES_IV_1_REG_ADDR 0x022CUL
|
|
||||||
#define HW_AES_KEY_0_ADDR_0_REG_ADDR 0x0400UL
|
|
||||||
#define HW_AES_KEY_0_ADDR_1_REG_ADDR 0x0404UL
|
|
||||||
#define HW_AES_KEY_0_ADDR_2_REG_ADDR 0x0408UL
|
|
||||||
#define HW_AES_KEY_0_ADDR_3_REG_ADDR 0x040cUL
|
|
||||||
#define HW_AES_KEY_0_ADDR_4_REG_ADDR 0x0410UL
|
|
||||||
#define HW_AES_KEY_0_ADDR_5_REG_ADDR 0x0414UL
|
|
||||||
#define HW_AES_KEY_0_ADDR_6_REG_ADDR 0x0418UL
|
|
||||||
#define HW_AES_KEY_0_ADDR_7_REG_ADDR 0x041cUL
|
|
||||||
#define HW_AES_KEY_0_REG_ADDR 0x0400UL
|
|
||||||
#define HW_AES_IV_0_ADDR_0_REG_ADDR 0x0440UL
|
|
||||||
#define HW_AES_IV_0_ADDR_1_REG_ADDR 0x0444UL
|
|
||||||
#define HW_AES_IV_0_ADDR_2_REG_ADDR 0x0448UL
|
|
||||||
#define HW_AES_IV_0_ADDR_3_REG_ADDR 0x044cUL
|
|
||||||
#define HW_AES_IV_0_REG_ADDR 0x0440UL
|
|
||||||
#define HW_AES_CTR1_ADDR_0_REG_ADDR 0x0460UL
|
|
||||||
#define HW_AES_CTR1_ADDR_1_REG_ADDR 0x0464UL
|
|
||||||
#define HW_AES_CTR1_ADDR_2_REG_ADDR 0x0468UL
|
|
||||||
#define HW_AES_CTR1_ADDR_3_REG_ADDR 0x046cUL
|
|
||||||
#define HW_AES_CTR1_REG_ADDR 0x0460UL
|
|
||||||
#define HW_AES_SK_REG_ADDR 0x0478UL
|
|
||||||
#define HW_AES_MAC_OK_REG_ADDR 0x0480UL
|
|
||||||
#define HW_AES_PREV_IV_0_ADDR_0_REG_ADDR 0x0490UL
|
|
||||||
#define HW_AES_PREV_IV_0_ADDR_1_REG_ADDR 0x0494UL
|
|
||||||
#define HW_AES_PREV_IV_0_ADDR_2_REG_ADDR 0x0498UL
|
|
||||||
#define HW_AES_PREV_IV_0_ADDR_3_REG_ADDR 0x049cUL
|
|
||||||
#define HW_AES_PREV_IV_0_REG_ADDR 0x0490UL
|
|
||||||
#define HW_AES_CONTROL_REG_ADDR 0x04C0UL
|
|
||||||
#define HW_HASH_H0_REG_ADDR 0x0640UL
|
|
||||||
#define HW_HASH_H1_REG_ADDR 0x0644UL
|
|
||||||
#define HW_HASH_H2_REG_ADDR 0x0648UL
|
|
||||||
#define HW_HASH_H3_REG_ADDR 0x064CUL
|
|
||||||
#define HW_HASH_H4_REG_ADDR 0x0650UL
|
|
||||||
#define HW_HASH_H5_REG_ADDR 0x0654UL
|
|
||||||
#define HW_HASH_H6_REG_ADDR 0x0658UL
|
|
||||||
#define HW_HASH_H7_REG_ADDR 0x065CUL
|
|
||||||
#define HW_HASH_H8_REG_ADDR 0x0660UL
|
|
||||||
#define HW_HASH_H9_REG_ADDR 0x0664UL
|
|
||||||
#define HW_HASH_H10_REG_ADDR 0x0668UL
|
|
||||||
#define HW_HASH_H11_REG_ADDR 0x066CUL
|
|
||||||
#define HW_HASH_H12_REG_ADDR 0x0670UL
|
|
||||||
#define HW_HASH_H13_REG_ADDR 0x0674UL
|
|
||||||
#define HW_HASH_H14_REG_ADDR 0x0678UL
|
|
||||||
#define HW_HASH_H15_REG_ADDR 0x067CUL
|
|
||||||
#define HW_HASH_CONTROL_REG_ADDR 0x07C0UL
|
|
||||||
#define HW_HASH_PAD_EN_REG_ADDR 0x07C4UL
|
|
||||||
#define HW_HASH_PAD_CFG_REG_ADDR 0x07C8UL
|
|
||||||
#define HW_HASH_CUR_LEN_0_REG_ADDR 0x07CCUL
|
|
||||||
#define HW_HASH_CUR_LEN_1_REG_ADDR 0x07D0UL
|
|
||||||
#define HW_HASH_CUR_LEN_2_REG_ADDR 0x07D4UL
|
|
||||||
#define HW_HASH_CUR_LEN_3_REG_ADDR 0x07D8UL
|
|
||||||
#define HW_HASH_PARAM_REG_ADDR 0x07DCUL
|
|
||||||
#define HW_HASH_INT_BUSY_REG_ADDR 0x07E0UL
|
|
||||||
#define HW_HASH_SW_RESET_REG_ADDR 0x07E4UL
|
|
||||||
#define HW_HASH_ENDIANESS_REG_ADDR 0x07E8UL
|
|
||||||
#define HW_HASH_DATA_REG_ADDR 0x07ECUL
|
|
||||||
#define HW_DRNG_CONTROL_REG_ADDR 0x0800UL
|
|
||||||
#define HW_DRNG_VALID_REG_ADDR 0x0804UL
|
|
||||||
#define HW_DRNG_DATA_REG_ADDR 0x0808UL
|
|
||||||
#define HW_RND_SRC_EN_REG_ADDR 0x080CUL
|
|
||||||
#define HW_AES_CLK_ENABLE_REG_ADDR 0x0810UL
|
|
||||||
#define HW_DES_CLK_ENABLE_REG_ADDR 0x0814UL
|
|
||||||
#define HW_HASH_CLK_ENABLE_REG_ADDR 0x0818UL
|
|
||||||
#define HW_PKI_CLK_ENABLE_REG_ADDR 0x081CUL
|
|
||||||
#define HW_CLK_STATUS_REG_ADDR 0x0824UL
|
|
||||||
#define HW_CLK_ENABLE_REG_ADDR 0x0828UL
|
|
||||||
#define HW_DRNG_SAMPLE_REG_ADDR 0x0850UL
|
|
||||||
#define HW_RND_SRC_CTL_REG_ADDR 0x0858UL
|
|
||||||
#define HW_CRYPTO_CTL_REG_ADDR 0x0900UL
|
|
||||||
#define HW_CRYPTO_STATUS_REG_ADDR 0x090CUL
|
|
||||||
#define HW_CRYPTO_BUSY_REG_ADDR 0x0910UL
|
|
||||||
#define HW_AES_BUSY_REG_ADDR 0x0914UL
|
|
||||||
#define HW_DES_BUSY_REG_ADDR 0x0918UL
|
|
||||||
#define HW_HASH_BUSY_REG_ADDR 0x091CUL
|
|
||||||
#define HW_CONTENT_REG_ADDR 0x0924UL
|
|
||||||
#define HW_VERSION_REG_ADDR 0x0928UL
|
|
||||||
#define HW_CONTEXT_ID_REG_ADDR 0x0930UL
|
|
||||||
#define HW_DIN_BUFFER_REG_ADDR 0x0C00UL
|
|
||||||
#define HW_DIN_MEM_DMA_BUSY_REG_ADDR 0x0c20UL
|
|
||||||
#define HW_SRC_LLI_MEM_ADDR_REG_ADDR 0x0c24UL
|
|
||||||
#define HW_SRC_LLI_WORD0_REG_ADDR 0x0C28UL
|
|
||||||
#define HW_SRC_LLI_WORD1_REG_ADDR 0x0C2CUL
|
|
||||||
#define HW_SRAM_SRC_ADDR_REG_ADDR 0x0c30UL
|
|
||||||
#define HW_DIN_SRAM_BYTES_LEN_REG_ADDR 0x0c34UL
|
|
||||||
#define HW_DIN_SRAM_DMA_BUSY_REG_ADDR 0x0C38UL
|
|
||||||
#define HW_WRITE_ALIGN_REG_ADDR 0x0C3CUL
|
|
||||||
#define HW_OLD_DATA_REG_ADDR 0x0C48UL
|
|
||||||
#define HW_WRITE_ALIGN_LAST_REG_ADDR 0x0C4CUL
|
|
||||||
#define HW_DOUT_BUFFER_REG_ADDR 0x0C00UL
|
|
||||||
#define HW_DST_LLI_WORD0_REG_ADDR 0x0D28UL
|
|
||||||
#define HW_DST_LLI_WORD1_REG_ADDR 0x0D2CUL
|
|
||||||
#define HW_DST_LLI_MEM_ADDR_REG_ADDR 0x0D24UL
|
|
||||||
#define HW_DOUT_MEM_DMA_BUSY_REG_ADDR 0x0D20UL
|
|
||||||
#define HW_SRAM_DEST_ADDR_REG_ADDR 0x0D30UL
|
|
||||||
#define HW_DOUT_SRAM_BYTES_LEN_REG_ADDR 0x0D34UL
|
|
||||||
#define HW_DOUT_SRAM_DMA_BUSY_REG_ADDR 0x0D38UL
|
|
||||||
#define HW_READ_ALIGN_REG_ADDR 0x0D3CUL
|
|
||||||
#define HW_READ_LAST_DATA_REG_ADDR 0x0D44UL
|
|
||||||
#define HW_RC4_THRU_CPU_REG_ADDR 0x0D4CUL
|
|
||||||
#define HW_AHB_SINGLE_REG_ADDR 0x0E00UL
|
|
||||||
#define HW_SRAM_DATA_REG_ADDR 0x0F00UL
|
|
||||||
#define HW_SRAM_ADDR_REG_ADDR 0x0F04UL
|
|
||||||
#define HW_SRAM_DATA_READY_REG_ADDR 0x0F08UL
|
|
||||||
#define HW_HOST_IRR_REG_ADDR 0x0A00UL
|
|
||||||
#define HW_HOST_IMR_REG_ADDR 0x0A04UL
|
|
||||||
#define HW_HOST_ICR_REG_ADDR 0x0A08UL
|
|
||||||
#define HW_HOST_SEP_SRAM_THRESHOLD_REG_ADDR 0x0A10UL
|
|
||||||
#define HW_HOST_SEP_BUSY_REG_ADDR 0x0A14UL
|
|
||||||
#define HW_HOST_SEP_LCS_REG_ADDR 0x0A18UL
|
|
||||||
#define HW_HOST_CC_SW_RST_REG_ADDR 0x0A40UL
|
|
||||||
#define HW_HOST_SEP_SW_RST_REG_ADDR 0x0A44UL
|
|
||||||
#define HW_HOST_FLOW_DMA_SW_INT0_REG_ADDR 0x0A80UL
|
|
||||||
#define HW_HOST_FLOW_DMA_SW_INT1_REG_ADDR 0x0A84UL
|
|
||||||
#define HW_HOST_FLOW_DMA_SW_INT2_REG_ADDR 0x0A88UL
|
|
||||||
#define HW_HOST_FLOW_DMA_SW_INT3_REG_ADDR 0x0A8cUL
|
|
||||||
#define HW_HOST_FLOW_DMA_SW_INT4_REG_ADDR 0x0A90UL
|
|
||||||
#define HW_HOST_FLOW_DMA_SW_INT5_REG_ADDR 0x0A94UL
|
|
||||||
#define HW_HOST_FLOW_DMA_SW_INT6_REG_ADDR 0x0A98UL
|
|
||||||
#define HW_HOST_FLOW_DMA_SW_INT7_REG_ADDR 0x0A9cUL
|
|
||||||
#define HW_HOST_SEP_HOST_GPR0_REG_ADDR 0x0B00UL
|
|
||||||
#define HW_HOST_SEP_HOST_GPR1_REG_ADDR 0x0B04UL
|
|
||||||
#define HW_HOST_SEP_HOST_GPR2_REG_ADDR 0x0B08UL
|
|
||||||
#define HW_HOST_SEP_HOST_GPR3_REG_ADDR 0x0B0CUL
|
|
||||||
#define HW_HOST_HOST_SEP_GPR0_REG_ADDR 0x0B80UL
|
|
||||||
#define HW_HOST_HOST_SEP_GPR1_REG_ADDR 0x0B84UL
|
|
||||||
#define HW_HOST_HOST_SEP_GPR2_REG_ADDR 0x0B88UL
|
|
||||||
#define HW_HOST_HOST_SEP_GPR3_REG_ADDR 0x0B8CUL
|
|
||||||
#define HW_HOST_HOST_ENDIAN_REG_ADDR 0x0B90UL
|
|
||||||
#define HW_HOST_HOST_COMM_CLK_EN_REG_ADDR 0x0B94UL
|
|
||||||
#define HW_CLR_SRAM_BUSY_REG_REG_ADDR 0x0F0CUL
|
|
||||||
#define HW_CC_SRAM_BASE_ADDRESS 0x5800UL
|
|
||||||
|
|
||||||
#endif /* ifndef HW_DEFS */
|
|
||||||
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