Core changes:
- Add PINCTRL_PINFUNCTION() macro and use it in several
drivers.
New drivers:
- New driver for the StarFive JH7110 SoC "sys" and "aon"
(always-on) pin controllers. (RISC-V.)
- New subdriver for the Qualcomm QDU1000/QRU1000 SoC pin
controller.
- New subdrivers for the Qualcomm SM8550 SoC and LPASS
pin controllers.
- New subdriver for the Qualcomm SA8775P SoC pin controller.
- New subdriver for the Qualcomm IPQ5332 SoC pin controller.
- New (trivial) support for Qualcomm PM8550 and PMR735D PMIC
pin control.
- New subdriver for the Mediatek MT7981 SoC pin controller.
Improvements:
- Several cleanups and refactorings to the Intel drivers.
- Add 4KOhm bias support to the Intel driver.
- Use the NOIRQ_SYSTEM_SLEEP_PM_OPS for the AT91 driver.
- Support general purpose clocks in the Qualcomm MSM8226 SoC.
- Several conversions to use the new I2C .probe_new() call.
- Massive clean-up of the Qualcomm Device Tree YAML schemas.
- Add VIN[45] pins, groups and functions to the Renesas
r8a77950 SoC driver.
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Merge tag 'pinctrl-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"Nothing special, notably a lot of new Qualcomm hardware is supported,
a RISC-V reference SoC and then some cleanups both in code and device
tree bindings.
Core changes:
- Add PINCTRL_PINFUNCTION() macro and use it in several drivers
New drivers:
- New driver for the StarFive JH7110 SoC "sys" and "aon" (always-on)
pin controllers. (RISC-V.)
- New subdriver for the Qualcomm QDU1000/QRU1000 SoC pin controller
- New subdrivers for the Qualcomm SM8550 SoC and LPASS pin
controllers
- New subdriver for the Qualcomm SA8775P SoC pin controller
- New subdriver for the Qualcomm IPQ5332 SoC pin controller
- New (trivial) support for Qualcomm PM8550 and PMR735D PMIC pin
control
- New subdriver for the Mediatek MT7981 SoC pin controller
Improvements:
- Several cleanups and refactorings to the Intel drivers
- Add 4KOhm bias support to the Intel driver
- Use the NOIRQ_SYSTEM_SLEEP_PM_OPS for the AT91 driver
- Support general purpose clocks in the Qualcomm MSM8226 SoC
- Several conversions to use the new I2C .probe_new() call
- Massive clean-up of the Qualcomm Device Tree YAML schemas
- Add VIN[45] pins, groups and functions to the Renesas r8a77950 SoC
driver"
* tag 'pinctrl-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (118 commits)
pinctrl: qcom: Add support for i2c specific pull feature
pinctrl: starfive: Add StarFive JH7110 aon controller driver
pinctrl: starfive: Add StarFive JH7110 sys controller driver
dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl
dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl
pinctrl: add mt7981 pinctrl driver
dt-bindings: pinctrl: add bindings for MT7981 SoC
dt-bindings: pinctrl: rockchip,pinctrl: mark gpio sub nodes of pinctrl as deprecated
pinctrl: qcom: Introduce IPQ5332 TLMM driver
dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
dt-bindings: pinctrl: qcom: lpass-lpi: correct GPIO name pattern
pinctrl: qcom: pinctrl-sm8550-lpass-lpi: add SM8550 LPASS
dt-bindings: pinctrl: qcom,sm8550-lpass-lpi-pinctrl: add SM8550 LPASS
pinctrl: at91: use devm_kasprintf() to avoid potential leaks
dt-bindings: pinctrl: qcom: correct gpio-ranges in examples
dt-bindings: pinctrl: qcom,msm8994: correct number of GPIOs
dt-bindings: pinctrl: qcom,sdx55: correct GPIO name pattern
dt-bindings: pinctrl: qcom,msm8953: correct GPIO name pattern
dt-bindings: pinctrl: qcom,sm6375: correct GPIO name pattern and example
dt-bindings: pinctrl: qcom,msm8909: correct GPIO name pattern and example
...
This commit is contained in:
Linus Torvalds
Коммит
d5176cdbf6
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@ -1,13 +1,13 @@
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|||
# SPDX-License-Identifier: GPL-2.0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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||||
---
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||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mm-pinctrl.yaml#
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||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8m-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
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title: Freescale IMX8MM IOMUX Controller
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title: Freescale IMX8M IOMUX Controller
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||||
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maintainers:
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- Anson Huang <Anson.Huang@nxp.com>
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||||
- Peng Fan <peng.fan@nxp.com>
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||||
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description:
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Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
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@ -15,7 +15,11 @@ description:
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properties:
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compatible:
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const: fsl,imx8mm-iomuxc
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enum:
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- fsl,imx8mm-iomuxc
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- fsl,imx8mn-iomuxc
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- fsl,imx8mp-iomuxc
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- fsl,imx8mq-iomuxc
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reg:
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maxItems: 1
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||||
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@ -34,9 +38,10 @@ patternProperties:
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|||
each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
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mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
|
||||
be found in <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last
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||||
integer CONFIG is the pad setting value like pull-up on this pin. Please
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||||
refer to i.MX8M Mini Reference Manual for detailed CONFIG settings.
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be found in <arch/arm64/boot/dts/freescale/imx8m[m,n,p,q]-pinfunc.h>.
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The last integer CONFIG is the pad setting value like pull-up on this
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||||
pin. Please refer to i.MX8M Mini/Nano/Plus/Quad Reference Manual for
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detailed CONFIG settings.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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items:
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@ -51,7 +56,8 @@ patternProperties:
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- description: |
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||||
"input_val" indicates the select input value to be applied.
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- description: |
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"pad_setting" indicates the pad configuration value to be applied.
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"pad_setting" indicates the pad configuration value to be
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||||
applied.
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||||
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required:
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- fsl,pins
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@ -1,84 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
|
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---
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||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mn-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale IMX8MN IOMUX Controller
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maintainers:
|
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- Anson Huang <Anson.Huang@nxp.com>
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|
||||
description:
|
||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
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for common binding part and usage.
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properties:
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compatible:
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const: fsl,imx8mn-iomuxc
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reg:
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maxItems: 1
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# Client device subnode's properties
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patternProperties:
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'grp$':
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type: object
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description:
|
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Pinctrl node's client devices use subnodes for desired pin configuration.
|
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Client device subnodes use below standard properties.
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properties:
|
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fsl,pins:
|
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description:
|
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each entry consists of 6 integers and represents the mux and config
|
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
|
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mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
|
||||
be found in <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last
|
||||
integer CONFIG is the pad setting value like pull-up on this pin. Please
|
||||
refer to i.MX8M Nano Reference Manual for detailed CONFIG settings.
|
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
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items:
|
||||
items:
|
||||
- description: |
|
||||
"mux_reg" indicates the offset of mux register.
|
||||
- description: |
|
||||
"conf_reg" indicates the offset of pad configuration register.
|
||||
- description: |
|
||||
"input_reg" indicates the offset of select input register.
|
||||
- description: |
|
||||
"mux_val" indicates the mux value to be applied.
|
||||
- description: |
|
||||
"input_val" indicates the select input value to be applied.
|
||||
- description: |
|
||||
"pad_setting" indicates the pad configuration value to be applied.
|
||||
|
||||
required:
|
||||
- fsl,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
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# Pinmux controller node
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- |
|
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iomuxc: pinctrl@30330000 {
|
||||
compatible = "fsl,imx8mn-iomuxc";
|
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reg = <0x30330000 0x10000>;
|
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|
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pinctrl_uart2: uart2grp {
|
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fsl,pins =
|
||||
<0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
|
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<0x240 0x4A8 0x000 0x0 0x0 0x140>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,84 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale IMX8MP IOMUX Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description:
|
||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
|
||||
for common binding part and usage.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mp-iomuxc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
# Client device subnode's properties
|
||||
patternProperties:
|
||||
'grp$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
fsl,pins:
|
||||
description:
|
||||
each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
|
||||
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
|
||||
be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
|
||||
integer CONFIG is the pad setting value like pull-up on this pin. Please
|
||||
refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
items:
|
||||
items:
|
||||
- description: |
|
||||
"mux_reg" indicates the offset of mux register.
|
||||
- description: |
|
||||
"conf_reg" indicates the offset of pad configuration register.
|
||||
- description: |
|
||||
"input_reg" indicates the offset of select input register.
|
||||
- description: |
|
||||
"mux_val" indicates the mux value to be applied.
|
||||
- description: |
|
||||
"input_val" indicates the select input value to be applied.
|
||||
- description: |
|
||||
"pad_setting" indicates the pad configuration value to be applied.
|
||||
|
||||
required:
|
||||
- fsl,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
iomuxc: pinctrl@30330000 {
|
||||
compatible = "fsl,imx8mp-iomuxc";
|
||||
reg = <0x30330000 0x10000>;
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins =
|
||||
<0x228 0x488 0x5F0 0x0 0x6 0x49>,
|
||||
<0x228 0x488 0x000 0x0 0x0 0x49>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -1,84 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mq-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale IMX8MQ IOMUX Controller
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
description:
|
||||
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
|
||||
for common binding part and usage.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: fsl,imx8mq-iomuxc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
# Client device subnode's properties
|
||||
patternProperties:
|
||||
'grp$':
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
|
||||
properties:
|
||||
fsl,pins:
|
||||
description:
|
||||
each entry consists of 6 integers and represents the mux and config
|
||||
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
|
||||
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
|
||||
be found in <arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h>. The last
|
||||
integer CONFIG is the pad setting value like pull-up on this pin. Please
|
||||
refer to i.MX8M Quad Reference Manual for detailed CONFIG settings.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-matrix
|
||||
items:
|
||||
items:
|
||||
- description: |
|
||||
"mux_reg" indicates the offset of mux register.
|
||||
- description: |
|
||||
"conf_reg" indicates the offset of pad configuration register.
|
||||
- description: |
|
||||
"input_reg" indicates the offset of select input register.
|
||||
- description: |
|
||||
"mux_val" indicates the mux value to be applied.
|
||||
- description: |
|
||||
"input_val" indicates the select input value to be applied.
|
||||
- description: |
|
||||
"pad_setting" indicates the pad configuration value to be applied.
|
||||
|
||||
required:
|
||||
- fsl,pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
iomuxc: pinctrl@30330000 {
|
||||
compatible = "fsl,imx8mq-iomuxc";
|
||||
reg = <0x30330000 0x10000>;
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins =
|
||||
<0x234 0x49C 0x4F4 0x0 0x0 0x49>,
|
||||
<0x238 0x4A0 0x4F4 0x0 0x0 0x49>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -70,11 +70,11 @@ allOf:
|
|||
- $ref: "pinctrl.yaml#"
|
||||
|
||||
patternProperties:
|
||||
'-[0-9]+$':
|
||||
'pins$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
patternProperties:
|
||||
'pins':
|
||||
'(^pins|pins?$)':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description: |
|
||||
|
|
@ -158,7 +158,7 @@ examples:
|
|||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
i2c0_pins_a: i2c0-0 {
|
||||
i2c0_pins_a: i2c0-pins {
|
||||
pins1 {
|
||||
pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
|
||||
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
|
||||
|
|
@ -166,7 +166,7 @@ examples:
|
|||
};
|
||||
};
|
||||
|
||||
i2c1_pins_a: i2c1-0 {
|
||||
i2c1_pins_a: i2c1-pins {
|
||||
pins {
|
||||
pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
|
||||
<MT8135_PIN_196_SCL1__FUNC_SCL1>;
|
||||
|
|
@ -174,7 +174,7 @@ examples:
|
|||
};
|
||||
};
|
||||
|
||||
i2c2_pins_a: i2c2-0 {
|
||||
i2c2_pins_a: i2c2-pins {
|
||||
pins1 {
|
||||
pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
|
||||
bias-pull-down;
|
||||
|
|
@ -186,7 +186,7 @@ examples:
|
|||
};
|
||||
};
|
||||
|
||||
i2c3_pins_a: i2c3-0 {
|
||||
i2c3_pins_a: i2c3-pins {
|
||||
pins1 {
|
||||
pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
|
||||
<MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
|
||||
|
|
|
|||
|
|
@ -61,11 +61,11 @@ then:
|
|||
- "#interrupt-cells"
|
||||
|
||||
patternProperties:
|
||||
'-[0-9]+$':
|
||||
'-pins(-[a-z]+)?$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
patternProperties:
|
||||
'mux':
|
||||
'^mux(-|$)':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description: |
|
||||
|
|
@ -244,7 +244,7 @@ patternProperties:
|
|||
groups:
|
||||
enum: [wf0_2g, wf0_5g]
|
||||
|
||||
'conf':
|
||||
'^conf(-|$)':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description: |
|
||||
|
|
@ -348,7 +348,7 @@ examples:
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
pinctrl_eth_default: eth-0 {
|
||||
pinctrl_eth_default: eth-pins {
|
||||
mux-mdio {
|
||||
groups = "mdc_mdio";
|
||||
function = "eth";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,475 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek MT7981 Pin Controller
|
||||
|
||||
maintainers:
|
||||
- Daniel Golle <daniel@makrotopia.org>
|
||||
|
||||
description:
|
||||
The MediaTek's MT7981 Pin controller is used to control SoC pins.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- mediatek,mt7981-pinctrl
|
||||
|
||||
reg:
|
||||
minItems: 9
|
||||
maxItems: 9
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: gpio
|
||||
- const: iocfg_rt
|
||||
- const: iocfg_rm
|
||||
- const: iocfg_rb
|
||||
- const: iocfg_lb
|
||||
- const: iocfg_bl
|
||||
- const: iocfg_tm
|
||||
- const: iocfg_tl
|
||||
- const: eint
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
description: >
|
||||
Number of cells in GPIO specifier. Since the generic GPIO binding is used,
|
||||
the amount of cells must be specified as 2. See the below mentioned gpio
|
||||
binding representation for description of particular cells.
|
||||
|
||||
gpio-ranges:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
description: GPIO valid number range.
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
allOf:
|
||||
- $ref: pinctrl.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- gpio-controller
|
||||
- "#gpio-cells"
|
||||
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
'^.*mux.*$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description: |
|
||||
pinmux configuration nodes.
|
||||
|
||||
The following table shows the effective values of "group", "function"
|
||||
properties and chip pinout pins
|
||||
|
||||
groups function pins (in pin#)
|
||||
---------------------------------------------------------------------
|
||||
"wa_aice1" "wa_aice" 0, 1
|
||||
"wa_aice2" "wa_aice" 0, 1
|
||||
"wm_uart_0" "uart" 0, 1
|
||||
"dfd" "dfd" 0, 1, 4, 5
|
||||
"watchdog" "watchdog" 2
|
||||
"pcie_pereset" "pcie" 3
|
||||
"jtag" "jtag" 4, 5, 6, 7, 8
|
||||
"wm_jtag_0" "jtag" 4, 5, 6, 7, 8
|
||||
"wo0_jtag_0" "jtag" 9, 10, 11, 12, 13
|
||||
"uart2_0" "uart" 4, 5, 6, 7
|
||||
"gbe_led0" "led" 8
|
||||
"pta_ext_0" "pta" 4, 5, 6
|
||||
"pwm2" "pwm" 7
|
||||
"net_wo0_uart_txd_0" "uart" 8
|
||||
"spi1_0" "spi" 4, 5, 6, 7
|
||||
"i2c0_0" "i2c" 6, 7
|
||||
"dfd_ntrst" "dfd" 8
|
||||
"wm_aice1" "wa_aice" 9, 10
|
||||
"pwm0_0" "pwm" 13
|
||||
"pwm0_1" "pwm" 15
|
||||
"pwm1_0" "pwm" 14
|
||||
"pwm1_1" "pwm" 15
|
||||
"net_wo0_uart_txd_1" "uart" 14
|
||||
"net_wo0_uart_txd_2" "uart" 15
|
||||
"gbe_led1" "led" 13
|
||||
"pcm" "pcm" 9, 10, 11, 12, 13, 25
|
||||
"watchdog1" "watchdog" 13
|
||||
"udi" "udi" 9, 10, 11, 12, 13
|
||||
"drv_vbus" "usb" 14
|
||||
"emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25
|
||||
"snfi" "flash" 16, 17, 18, 19, 20, 21
|
||||
"spi0" "spi" 16, 17, 18, 19
|
||||
"spi0_wp_hold" "spi" 20, 21
|
||||
"spi1_1" "spi" 22, 23, 24, 25
|
||||
"spi2" "spi" 26, 27, 28, 29
|
||||
"spi2_wp_hold" "spi" 30, 31
|
||||
"uart1_0" "uart" 16, 17, 18, 19
|
||||
"uart1_1" "uart" 26, 27, 28, 29
|
||||
"uart2_1" "uart" 22, 23, 24, 25
|
||||
"pta_ext_1" "pta" 22, 23, 24
|
||||
"wm_aurt_1" "uart" 20, 21
|
||||
"wm_aurt_2" "uart" 30, 31
|
||||
"wm_jtag_1" "jtag" 20, 21, 22, 23, 24
|
||||
"wo0_jtag_1" "jtag" 25, 26, 27, 28, 29
|
||||
"wa_aice3" "wa_aice" 28, 20
|
||||
"wm_aice2" "wa_aice" 30, 31
|
||||
"i2c0_1" "i2c" 30, 31
|
||||
"u2_phy_i2c" "i2c" 30, 31
|
||||
"uart0" "uart" 32, 33
|
||||
"sgmii1_phy_i2c" "i2c" 32, 33
|
||||
"u3_phy_i2c" "i2c" 32, 33
|
||||
"sgmii0_phy_i2c" "i2c" 32, 33
|
||||
"pcie_clk" "pcie" 34
|
||||
"pcie_wake" "pcie" 35
|
||||
"i2c0_2" "i2c" 36, 37
|
||||
"smi_mdc_mdio" "eth" 36, 37
|
||||
"gbe_ext_mdc_mdio" "eth" 36, 37
|
||||
"wf0_mode1" "eth" 40, 41, 42, 43, 44, 45, 46, 47, 48,
|
||||
49, 50, 51, 52, 53, 54, 55, 56
|
||||
|
||||
"wf0_mode3" "eth" 45, 46, 47, 48, 49, 51
|
||||
"wf2g_led0" "led" 30
|
||||
"wf2g_led1" "led" 34
|
||||
"wf5g_led0" "led" 31
|
||||
"wf5g_led1" "led" 35
|
||||
"mt7531_int" "eth" 38
|
||||
"ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 21, 22
|
||||
23, 24, 25, 34, 35
|
||||
|
||||
$ref: /schemas/pinctrl/pinmux-node.yaml
|
||||
properties:
|
||||
function:
|
||||
description:
|
||||
A string containing the name of the function to mux to the group.
|
||||
enum: [wa_aice, dfd, jtag, pta, pcm, udi, usb, ant, eth, i2c, led,
|
||||
pwm, spi, uart, watchdog, flash, pcie]
|
||||
groups:
|
||||
description:
|
||||
An array of strings. Each string contains the name of a group.
|
||||
|
||||
required:
|
||||
- function
|
||||
- groups
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: wa_aice
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [wa_aice1, wa_aice2, wm_aice1_1, wa_aice3, wm_aice1_2]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: dfd
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [dfd, dfd_ntrst]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: jtag
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [jtag, wm_jtag_0, wo0_jtag_0, wo0_jtag_1, wm_jtag_1]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pta
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pta_ext_0, pta_ext_1]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcm
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pcm]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: udi
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [udi]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: usb
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [drv_vbus]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: ant
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [ant_sel]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: eth
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [smi_mdc_mdio, gbe_ext_mdc_mdio, wf0_mode1, wf0_mode3,
|
||||
mt7531_int]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: i2c
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [i2c0_0, i2c0_1, u2_phy_i2c, sgmii1_phy_i2c, u3_phy_i2c,
|
||||
sgmii0_phy_i2c, i2c0_2]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: led
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_led0, wf5g_led1]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pwm
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
items:
|
||||
enum: [pwm2, pwm0_0, pwm0_1, pwm1_0, pwm1_1]
|
||||
maxItems: 3
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spi
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
items:
|
||||
enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2, spi2_wp_hold]
|
||||
maxItems: 4
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uart
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
items:
|
||||
enum: [wm_uart_0, uart2_0, net_wo0_uart_txd_0,
|
||||
net_wo0_uart_txd_1, net_wo0_uart_txd_2, uart1_0,
|
||||
uart1_1, uart2_1, wm_aurt_1, wm_aurt_2, uart0]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: watchdog
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [watchdog]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: flash
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
items:
|
||||
enum: [emmc_45, snfi]
|
||||
maxItems: 1
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcie
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
items:
|
||||
enum: [pcie_clk, pcie_wake, pcie_pereset]
|
||||
maxItems: 3
|
||||
|
||||
'^.*conf.*$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description: pinconf configuration nodes.
|
||||
$ref: /schemas/pinctrl/pincfg-node.yaml
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
An array of strings. Each string contains the name of a pin.
|
||||
items:
|
||||
enum: [GPIO_WPS, GPIO_RESET, SYS_WATCHDOG, PCIE_PERESET_N,
|
||||
JTAG_JTDO, JTAG_JTDI, JTAG_JTMS, JTAG_JTCLK, JTAG_JTRST_N,
|
||||
WO_JTAG_JTDO, WO_JTAG_JTDI, WO_JTAG_JTMS, WO_JTAG_JTCLK,
|
||||
WO_JTAG_JTRST_N, USB_VBUS, PWM0, SPI0_CLK, SPI0_MOSI,
|
||||
SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI,
|
||||
SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS,
|
||||
SPI2_HOLD, SPI2_WP, UART0_RXD, UART0_TXD, PCIE_CLK_REQ,
|
||||
PCIE_WAKE_N, SMI_MDC, SMI_MDIO, GBE_INT, GBE_RESET,
|
||||
WF_DIG_RESETB, WF_CBA_RESETB, WF_XO_REQ, WF_TOP_CLK,
|
||||
WF_TOP_DATA, WF_HB1, WF_HB2, WF_HB3, WF_HB4, WF_HB0,
|
||||
WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_HB8, WF_HB9, WF_HB10]
|
||||
maxItems: 57
|
||||
|
||||
bias-disable: true
|
||||
|
||||
bias-pull-up:
|
||||
oneOf:
|
||||
- type: boolean
|
||||
description: normal pull up.
|
||||
- enum: [100, 101, 102, 103]
|
||||
description: >
|
||||
PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
|
||||
dt-bindings/pinctrl/mt65xx.h.
|
||||
|
||||
bias-pull-down:
|
||||
oneOf:
|
||||
- type: boolean
|
||||
description: normal pull down.
|
||||
- enum: [100, 101, 102, 103]
|
||||
description: >
|
||||
PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
|
||||
dt-bindings/pinctrl/mt65xx.h.
|
||||
|
||||
input-enable: true
|
||||
|
||||
input-disable: true
|
||||
|
||||
output-enable: true
|
||||
|
||||
output-low: true
|
||||
|
||||
output-high: true
|
||||
|
||||
input-schmitt-enable: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
|
||||
mediatek,pull-up-adv:
|
||||
description: |
|
||||
Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
|
||||
Pull up setings for 2 pull resistors, R0 and R1. Valid arguments
|
||||
are described as below:
|
||||
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
|
||||
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
|
||||
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
|
||||
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
|
||||
mediatek,pull-down-adv:
|
||||
description: |
|
||||
Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
|
||||
Pull down setings for 2 pull resistors, R0 and R1. Valid arguments
|
||||
are described as below:
|
||||
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
|
||||
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
|
||||
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
|
||||
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/mt65xx.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
pio: pinctrl@11d00000 {
|
||||
compatible = "mediatek,mt7981-pinctrl";
|
||||
reg = <0 0x11d00000 0 0x1000>,
|
||||
<0 0x11c00000 0 0x1000>,
|
||||
<0 0x11c10000 0 0x1000>,
|
||||
<0 0x11d20000 0 0x1000>,
|
||||
<0 0x11e00000 0 0x1000>,
|
||||
<0 0x11e20000 0 0x1000>,
|
||||
<0 0x11f00000 0 0x1000>,
|
||||
<0 0x11f10000 0 0x1000>,
|
||||
<0 0x1000b000 0 0x1000>;
|
||||
reg-names = "gpio", "iocfg_rt", "iocfg_rm",
|
||||
"iocfg_rb", "iocfg_lb", "iocfg_bl",
|
||||
"iocfg_tm", "iocfg_tl", "eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 56>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
mdio_pins: mdio-pins {
|
||||
mux {
|
||||
function = "eth";
|
||||
groups = "smi_mdc_mdio";
|
||||
};
|
||||
};
|
||||
|
||||
spi0_flash_pins: spi0-pins {
|
||||
mux {
|
||||
function = "spi";
|
||||
groups = "spi0", "spi0_wp_hold";
|
||||
};
|
||||
|
||||
conf-pu {
|
||||
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
|
||||
drive-strength = <MTK_DRIVE_8mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
|
||||
};
|
||||
|
||||
conf-pd {
|
||||
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
|
||||
drive-strength = <MTK_DRIVE_8mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie_pins: pcie-pins {
|
||||
mux {
|
||||
function = "pcie";
|
||||
groups = "pcie_clk", "pcie_wake", "pcie_pereset";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
|
|
@ -67,11 +67,11 @@ required:
|
|||
- gpio-ranges
|
||||
|
||||
patternProperties:
|
||||
'-[0-9]+$':
|
||||
'-pins(-[a-z]+)?$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
patternProperties:
|
||||
'pins':
|
||||
'^pins':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description: |
|
||||
|
|
@ -210,7 +210,7 @@ examples:
|
|||
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
i2c0_pins_a: i2c-0 {
|
||||
i2c0_pins_a: i2c0-pins {
|
||||
pins1 {
|
||||
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
|
||||
<PINMUX_GPIO49__FUNC_SDA5>;
|
||||
|
|
@ -219,7 +219,7 @@ examples:
|
|||
};
|
||||
};
|
||||
|
||||
i2c1_pins_a: i2c-1 {
|
||||
i2c1_pins_a: i2c1-pins {
|
||||
pins {
|
||||
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
|
||||
<PINMUX_GPIO51__FUNC_SDA3>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,197 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Mediatek MT8365 Pin Controller
|
||||
|
||||
maintainers:
|
||||
- Zhiyong Tao <zhiyong.tao@mediatek.com>
|
||||
- Bernhard Rosenkränzer <bero@baylibre.com>
|
||||
|
||||
description: |
|
||||
The MediaTek's MT8365 Pin controller is used to control SoC pins.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,mt8365-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
mediatek,pctl-regmap:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
description: |
|
||||
Should be phandles of the syscfg node.
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
"#gpio-cells":
|
||||
const: 2
|
||||
description: |
|
||||
Number of cells in GPIO specifier. Since the generic GPIO
|
||||
binding is used, the amount of cells must be specified as 2. See the below
|
||||
mentioned gpio binding representation for description of particular cells.
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
"#interrupt-cells":
|
||||
const: 2
|
||||
|
||||
patternProperties:
|
||||
"-pins$":
|
||||
type: object
|
||||
additionalProperties: false
|
||||
patternProperties:
|
||||
"pins$":
|
||||
type: object
|
||||
additionalProperties: false
|
||||
description: |
|
||||
A pinctrl node should contain at least one subnode representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to muxer
|
||||
configuration, pullups, drive strength, input enable/disable and input
|
||||
schmitt.
|
||||
$ref: /schemas/pinctrl/pincfg-node.yaml
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
description:
|
||||
integer array, represents gpio pin number and mux setting.
|
||||
Supported pin number and mux varies for different SoCs, and are
|
||||
defined as macros in <soc>-pinfunc.h directly.
|
||||
|
||||
bias-disable: true
|
||||
|
||||
bias-pull-up:
|
||||
description: |
|
||||
Besides generic pinconfig options, it can be used as the pull up
|
||||
settings for 2 pull resistors, R0 and R1. User can configure those
|
||||
special pins.
|
||||
|
||||
bias-pull-down: true
|
||||
|
||||
input-enable: true
|
||||
|
||||
input-disable: true
|
||||
|
||||
output-low: true
|
||||
|
||||
output-high: true
|
||||
|
||||
input-schmitt-enable: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
mediatek,drive-strength-adv:
|
||||
description: |
|
||||
Describe the specific driving setup property.
|
||||
For I2C pins, the existing generic driving setup can only support
|
||||
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
|
||||
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
|
||||
driving setup, the existing generic setup will be disabled.
|
||||
The specific driving setup is controlled by E1E0EN.
|
||||
When E1=0/E0=0, the strength is 0.125mA.
|
||||
When E1=0/E0=1, the strength is 0.25mA.
|
||||
When E1=1/E0=0, the strength is 0.5mA.
|
||||
When E1=1/E0=1, the strength is 1mA.
|
||||
EN is used to enable or disable the specific driving setup.
|
||||
Valid arguments are described as below:
|
||||
0: (E1, E0, EN) = (0, 0, 0)
|
||||
1: (E1, E0, EN) = (0, 0, 1)
|
||||
2: (E1, E0, EN) = (0, 1, 0)
|
||||
3: (E1, E0, EN) = (0, 1, 1)
|
||||
4: (E1, E0, EN) = (1, 0, 0)
|
||||
5: (E1, E0, EN) = (1, 0, 1)
|
||||
6: (E1, E0, EN) = (1, 1, 0)
|
||||
7: (E1, E0, EN) = (1, 1, 1)
|
||||
So the valid arguments are from 0 to 7.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3, 4, 5, 6, 7]
|
||||
|
||||
mediatek,pull-up-adv:
|
||||
description: |
|
||||
Pull up setings for 2 pull resistors, R0 and R1. User can
|
||||
configure those special pins. Valid arguments are described as below:
|
||||
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
|
||||
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
|
||||
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
|
||||
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
|
||||
mediatek,pull-down-adv:
|
||||
description: |
|
||||
Pull down settings for 2 pull resistors, R0 and R1. User can
|
||||
configure those special pins. Valid arguments are described as below:
|
||||
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
|
||||
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
|
||||
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
|
||||
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [0, 1, 2, 3]
|
||||
|
||||
mediatek,tdsel:
|
||||
description: |
|
||||
An integer describing the steps for output level shifter duty
|
||||
cycle when asserted (high pulse width adjustment). Valid arguments
|
||||
are from 0 to 15.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
mediatek,rdsel:
|
||||
description: |
|
||||
An integer describing the steps for input level shifter duty cycle
|
||||
when asserted (high pulse width adjustment). Valid arguments are
|
||||
from 0 to 63.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
required:
|
||||
- pinmux
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- gpio-controller
|
||||
- "#gpio-cells"
|
||||
|
||||
allOf:
|
||||
- $ref: pinctrl.yaml#
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pio: pinctrl@1000b000 {
|
||||
compatible = "mediatek,mt8365-pinctrl";
|
||||
reg = <0 0x1000b000 0 0x1000>;
|
||||
mediatek,pctl-regmap = <&syscfg_pctl>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
pio-pins {
|
||||
pins {
|
||||
pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>, <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;
|
||||
mediatek,pull-up-adv = <3>;
|
||||
mediatek,drive-strength-adv = <00>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm IPQ5332 TLMM pin controller
|
||||
|
||||
maintainers:
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
|
||||
description: |
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,ipq5332-tlmm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 27
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 53
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-ipq5332-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-ipq5332-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-ipq5332-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
pattern: "^gpio([0-9]|[1-4][0-9]|5[0-2])$"
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
|
||||
enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
|
||||
atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec,
|
||||
audio_sec0, audio_sec1, blsp0_i2c, blsp0_spi, blsp0_uart0,
|
||||
blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1,
|
||||
blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1,
|
||||
blsp2_spi, blsp2_spi0, blsp2_spi1, core_voltage, cri_trng0,
|
||||
cri_trng1, cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out,
|
||||
gcc_plltest, gcc_tlmm, gpio, lock_det, mac0, mac1, mdc0, mdc1,
|
||||
mdio0, mdio1, pc, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake,
|
||||
pcie2_clk, pcie2_wake, pll_test, prng_rosc0, prng_rosc1,
|
||||
prng_rosc2, prng_rosc3, pta, pwm0, pwm1, pwm2, pwm3,
|
||||
qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
|
||||
qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
|
||||
qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
|
||||
qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
|
||||
qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
|
||||
qdss_tracedata_b, qspi_data, qspi_clk, qspi_cs, resout, rx0,
|
||||
rx1, sdc_data, sdc_clk, sdc_cmd, tsens_max, wci_txd, wci_rxd,
|
||||
wsi_clk, wsi_clk3, wsi_data, wsi_data3, wsis_reset, xfem ]
|
||||
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
bias-disable: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
tlmm: pinctrl@1000000 {
|
||||
compatible = "qcom,ipq5332-tlmm";
|
||||
reg = <0x01000000 0x300000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <0x2>;
|
||||
gpio-ranges = <&tlmm 0 0 53>;
|
||||
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <0x2>;
|
||||
|
||||
serial0-state {
|
||||
pins = "gpio18", "gpio19";
|
||||
function = "blsp0_uart0";
|
||||
drive-strength = <8>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
|
@ -19,7 +19,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -20,7 +20,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -22,7 +22,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -20,7 +20,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
'#interrupt-cells': true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -20,7 +20,9 @@ properties:
|
|||
description: Specifies the base address and size of the TLMM register space
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
@ -54,7 +56,7 @@ $defs:
|
|||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-6])$"
|
||||
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
|
@ -66,8 +68,8 @@ $defs:
|
|||
enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
|
||||
blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_spi1,
|
||||
blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
|
||||
blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1, sdc3,
|
||||
wlan ]
|
||||
blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1,
|
||||
gp0_clk, gp1_clk, sdc3, wlan ]
|
||||
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
|
|
|
|||
|
|
@ -20,7 +20,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -22,7 +22,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
@ -61,7 +63,7 @@ $defs:
|
|||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-7])$"
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
|
||||
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
|
||||
sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1,
|
||||
qdsd_data2, qdsd_data3 ]
|
||||
|
|
@ -125,7 +127,7 @@ examples:
|
|||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 117>;
|
||||
gpio-ranges = <&tlmm 0 0 113>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
|
|
|
|||
|
|
@ -20,7 +20,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -19,7 +19,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
@ -51,7 +53,7 @@ $defs:
|
|||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[01])$"
|
||||
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
|
||||
sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0,
|
||||
qdsd_data1, qdsd_data2, qdsd_data3 ]
|
||||
|
|
|
|||
|
|
@ -20,7 +20,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -20,7 +20,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -20,7 +20,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -22,7 +22,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
@ -32,10 +34,10 @@ properties:
|
|||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 75
|
||||
maxItems: 73
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 150
|
||||
maxItems: 146
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
|
|
@ -61,7 +63,7 @@ $defs:
|
|||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$"
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-5])$"
|
||||
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
|
||||
sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ]
|
||||
minItems: 1
|
||||
|
|
|
|||
|
|
@ -20,7 +20,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -20,7 +20,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -40,6 +40,10 @@ properties:
|
|||
- qcom,pm8350b-gpio
|
||||
- qcom,pm8350c-gpio
|
||||
- qcom,pm8450-gpio
|
||||
- qcom,pm8550-gpio
|
||||
- qcom,pm8550b-gpio
|
||||
- qcom,pm8550ve-gpio
|
||||
- qcom,pm8550vs-gpio
|
||||
- qcom,pm8916-gpio
|
||||
- qcom,pm8917-gpio
|
||||
- qcom,pm8921-gpio
|
||||
|
|
@ -52,10 +56,12 @@ properties:
|
|||
- qcom,pmi8994-gpio
|
||||
- qcom,pmi8998-gpio
|
||||
- qcom,pmk8350-gpio
|
||||
- qcom,pmk8550-gpio
|
||||
- qcom,pmm8155au-gpio
|
||||
- qcom,pmp8074-gpio
|
||||
- qcom,pmr735a-gpio
|
||||
- qcom,pmr735b-gpio
|
||||
- qcom,pmr735d-gpio
|
||||
- qcom,pms405-gpio
|
||||
- qcom,pmx55-gpio
|
||||
- qcom,pmx65-gpio
|
||||
|
|
@ -111,6 +117,7 @@ allOf:
|
|||
enum:
|
||||
- qcom,pm8008-gpio
|
||||
- qcom,pmi8950-gpio
|
||||
- qcom,pmr735d-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
|
|
@ -146,6 +153,8 @@ allOf:
|
|||
enum:
|
||||
- qcom,pm8018-gpio
|
||||
- qcom,pm8019-gpio
|
||||
- qcom,pm8550vs-gpio
|
||||
- qcom,pmk8550-gpio
|
||||
then:
|
||||
properties:
|
||||
gpio-line-names:
|
||||
|
|
@ -162,6 +171,7 @@ allOf:
|
|||
enum:
|
||||
- qcom,pm8226-gpio
|
||||
- qcom,pm8350b-gpio
|
||||
- qcom,pm8550ve-gpio
|
||||
- qcom,pm8950-gpio
|
||||
then:
|
||||
properties:
|
||||
|
|
@ -236,6 +246,8 @@ allOf:
|
|||
- qcom,pm8038-gpio
|
||||
- qcom,pm8150b-gpio
|
||||
- qcom,pm8150l-gpio
|
||||
- qcom,pm8550-gpio
|
||||
- qcom,pm8550b-gpio
|
||||
- qcom,pmc8180c-gpio
|
||||
- qcom,pmp8074-gpio
|
||||
- qcom,pms405-gpio
|
||||
|
|
@ -411,6 +423,10 @@ $defs:
|
|||
- gpio1-gpio8 for pm8350b
|
||||
- gpio1-gpio9 for pm8350c
|
||||
- gpio1-gpio4 for pm8450
|
||||
- gpio1-gpio12 for pm8550
|
||||
- gpio1-gpio12 for pm8550b
|
||||
- gpio1-gpio8 for pm8550ve
|
||||
- gpio1-gpio6 for pm8550vs
|
||||
- gpio1-gpio38 for pm8917
|
||||
- gpio1-gpio44 for pm8921
|
||||
- gpio1-gpio36 for pm8941
|
||||
|
|
@ -421,10 +437,12 @@ $defs:
|
|||
- gpio1-gpio2 for pmi8950
|
||||
- gpio1-gpio10 for pmi8994
|
||||
- gpio1-gpio4 for pmk8350
|
||||
- gpio1-gpio6 for pmk8550
|
||||
- gpio1-gpio10 for pmm8155au
|
||||
- gpio1-gpio12 for pmp8074 (holes on gpio1 and gpio12)
|
||||
- gpio1-gpio4 for pmr735a
|
||||
- gpio1-gpio4 for pmr735b
|
||||
- gpio1-gpio2 for pmr735d
|
||||
- gpio1-gpio12 for pms405 (holes on gpio1, gpio9
|
||||
and gpio10)
|
||||
- gpio1-gpio11 for pmx55 (holes on gpio3, gpio7, gpio10
|
||||
|
|
|
|||
|
|
@ -74,7 +74,7 @@ patternProperties:
|
|||
oneOf:
|
||||
- $ref: "#/$defs/qcom-pmic-mpp-state"
|
||||
- patternProperties:
|
||||
"mpp":
|
||||
'-pins$':
|
||||
$ref: "#/$defs/qcom-pmic-mpp-state"
|
||||
additionalProperties: false
|
||||
|
||||
|
|
@ -179,7 +179,7 @@ examples:
|
|||
};
|
||||
|
||||
default-state {
|
||||
gpio-mpp {
|
||||
gpio-pins {
|
||||
pins = "mpp1", "mpp2", "mpp3", "mpp4";
|
||||
function = "digital";
|
||||
input-enable;
|
||||
|
|
|
|||
|
|
@ -19,7 +19,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -26,7 +26,9 @@ properties:
|
|||
- const: north
|
||||
- const: east
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -0,0 +1,134 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,qdu1000-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. QDU1000/QRU1000 TLMM block
|
||||
|
||||
maintainers:
|
||||
- Melody Olvera <quic_molvera@quicinc.com>
|
||||
|
||||
description: |
|
||||
Top Level Mode Multiplexer pin controller found in the QDU1000 and
|
||||
QRU1000 SoCs.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,qdu1000-tlmm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 76
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 151
|
||||
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-qdu1000-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-qdu1000-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-qdu1000-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|150)$"
|
||||
- enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
enum: [ atest_char, atest_usb, char_exec, CMO_PRI, cmu_rng,
|
||||
dbg_out_clk, ddr_bist, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4,
|
||||
ddr_pxi5, ddr_pxi6, ddr_pxi7, eth012_int_n, eth345_int_n,
|
||||
gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_pps_in, hardsync_pps_in,
|
||||
intr_c, jitter_bist_ref, pcie_clkreqn, phase_flag, pll_bist,
|
||||
pll_clk, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable,
|
||||
qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
|
||||
qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss,
|
||||
qlink3_enable, qlink3_request, qlink3_wmss, qlink4_enable,
|
||||
qlink4_request, qlink4_wmss, qlink5_enable, qlink5_request,
|
||||
qlink5_wmss, qlink6_enable, qlink6_request, qlink6_wmss,
|
||||
qlink7_enable, qlink7_request, qlink7_wmss, qspi_clk, qspi_cs,
|
||||
qspi0, qspi1, qspi2, qspi3, qup00, qup01, qup02, qup03, qup04,
|
||||
qup05, qup06, qup07, qup08, qup10, qup11, qup12, qup13, qup14,
|
||||
qup15, qup16, qup17, qup20, qup21, qup22, SI5518_INT, smb_alert,
|
||||
smb_clk, smb_dat, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
|
||||
tgu_ch4, tgu_ch5, tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1,
|
||||
tmess_prng2, tmess_prng3, tod_pps_in, tsense_pwm1, tsense_pwm2,
|
||||
usb2phy_ac, usb_con_det, usb_dfp_en, usb_phy, vfr_0, vfr_1,
|
||||
vsense_trigger ]
|
||||
|
||||
bias-disable: true
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pinctrl@f000000 {
|
||||
compatible = "qcom,qdu1000-tlmm";
|
||||
reg = <0xf000000 0x1000000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 151>;
|
||||
wakeup-parent = <&pdc>;
|
||||
|
||||
uart0-default-state {
|
||||
pins = "gpio6", "gpio7", "gpio8", "gpio9";
|
||||
function = "qup00";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sa8775p-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. SA8775P TLMM block
|
||||
|
||||
maintainers:
|
||||
- Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
|
||||
|
||||
description: |
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SA8775P SoC.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sa8775p-tlmm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 74
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 148
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sa8775p-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sa8775p-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sa8775p-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-7])$"
|
||||
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, ufs_reset ]
|
||||
minItems: 1
|
||||
maxItems: 16
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
|
||||
enum: [ atest_char, atest_usb2, audio_ref, cam_mclk, cci_async, cci_i2c,
|
||||
cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
|
||||
cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9,
|
||||
cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
|
||||
ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, edp0_hot,
|
||||
edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot,
|
||||
edp3_lcd, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3,
|
||||
emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0,
|
||||
emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio,
|
||||
emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3,
|
||||
gcc_gp4, gcc_gp5, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c,
|
||||
jitter_bist, mdp0_vsync0, mdp0_vsync1, mdp0_vsync2, mdp0_vsync3,
|
||||
mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, mdp0_vsync7, mdp0_vsync8,
|
||||
mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
|
||||
mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
|
||||
mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0,
|
||||
mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, mi2s_mclk1,
|
||||
pcie0_clkreq, pcie1_clkreq, phase_flag, pll_bist, pll_clk,
|
||||
prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
|
||||
qdss_gpio, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
|
||||
qup0_se5, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
|
||||
qup1_se5, qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3,
|
||||
qup2_se4, qup2_se5, qup2_se6, qup3_se0, sailss_emac0,
|
||||
sailss_ospi, sail_top, sgmii_phy, tb_trig, tgu_ch0, tgu_ch1,
|
||||
tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5, tsense_pwm1, tsense_pwm2,
|
||||
tsense_pwm3, tsense_pwm4, usb2phy_ac, vsense_trigger ]
|
||||
|
||||
bias-disable: true
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
tlmm: pinctrl@f000000 {
|
||||
compatible = "qcom,sa8775p-tlmm";
|
||||
reg = <0xf000000 0x1000000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 148>;
|
||||
|
||||
qup-uart10-state {
|
||||
pins = "gpio46", "gpio47";
|
||||
function = "qup1_se3";
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -26,7 +26,9 @@ properties:
|
|||
- const: north
|
||||
- const: south
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ $defs:
|
|||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9])$"
|
||||
- pattern: "^gpio([0-9]|1[0-4])$"
|
||||
minItems: 1
|
||||
maxItems: 15
|
||||
|
||||
|
|
|
|||
|
|
@ -28,7 +28,9 @@ properties:
|
|||
- const: east
|
||||
- const: south
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
'#interrupt-cells': true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ $defs:
|
|||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
pattern: "^gpio([0-1]|1[0-8])$"
|
||||
pattern: "^gpio([0-9]|1[0-8])$"
|
||||
|
||||
function:
|
||||
enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
|
||||
|
|
@ -94,14 +94,12 @@ $defs:
|
|||
2: Lower Slew rate (slower edges)
|
||||
3: Reserved (No adjustments)
|
||||
|
||||
bias-bus-hold: true
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-disable: true
|
||||
|
||||
input-enable: true
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
|
|
@ -136,7 +134,7 @@ examples:
|
|||
clock-names = "core", "audio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&lpi_tlmm 0 0 18>;
|
||||
gpio-ranges = <&lpi_tlmm 0 0 19>;
|
||||
|
||||
dmic01-state {
|
||||
dmic01-clk-pins {
|
||||
|
|
|
|||
|
|
@ -22,7 +22,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -31,7 +31,9 @@ properties:
|
|||
- const: center
|
||||
- const: north
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -22,7 +22,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -23,7 +23,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
@ -48,6 +50,10 @@ patternProperties:
|
|||
$ref: "#/$defs/qcom-sdm845-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
"-hog(-[0-9]+)?$":
|
||||
required:
|
||||
- gpio-hog
|
||||
|
||||
$defs:
|
||||
qcom-sdm845-tlmm-state:
|
||||
type: object
|
||||
|
|
@ -117,6 +123,7 @@ additionalProperties: false
|
|||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
pinctrl@3400000 {
|
||||
|
|
@ -130,6 +137,12 @@ examples:
|
|||
gpio-ranges = <&tlmm 0 0 151>;
|
||||
wakeup-parent = <&pdc_intc>;
|
||||
|
||||
ap-suspend-l-hog {
|
||||
gpio-hog;
|
||||
gpios = <126 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
};
|
||||
|
||||
cci0-default-state {
|
||||
pins = "gpio17", "gpio18";
|
||||
function = "cci_i2c";
|
||||
|
|
|
|||
|
|
@ -20,7 +20,9 @@ properties:
|
|||
description: Specifies the base address and size of the TLMM register space
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
@ -53,7 +55,7 @@ $defs:
|
|||
List of gpio pins affected by the properties specified in this subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
|
||||
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
|
|
|||
|
|
@ -19,7 +19,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -26,7 +26,9 @@ properties:
|
|||
- const: south
|
||||
- const: east
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -27,7 +27,9 @@ properties:
|
|||
- const: south
|
||||
- const: east
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -22,11 +22,21 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
minItems: 9
|
||||
maxItems: 9
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
gpio-reserved-ranges: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 78
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 156
|
||||
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
|
@ -61,7 +71,7 @@ $defs:
|
|||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-7])$"
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$"
|
||||
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
|
@ -118,7 +128,16 @@ examples:
|
|||
pinctrl@f100000 {
|
||||
compatible = "qcom,sm6350-tlmm";
|
||||
reg = <0x0f100000 0x300000>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
|
|
|||
|
|
@ -22,7 +22,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
@ -61,7 +63,7 @@ $defs:
|
|||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-6])$"
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$"
|
||||
- enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk,
|
||||
sdc2_cmd, sdc2_data ]
|
||||
minItems: 1
|
||||
|
|
@ -132,7 +134,7 @@ examples:
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 157>;
|
||||
gpio-ranges = <&tlmm 0 0 157>; /* GPIOs + ufs_reset */
|
||||
|
||||
gpio-wo-subnode-state {
|
||||
pins = "gpio1";
|
||||
|
|
|
|||
|
|
@ -27,7 +27,9 @@ properties:
|
|||
- const: north
|
||||
- const: south
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ $defs:
|
|||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9])$"
|
||||
- pattern: "^gpio([0-9]|1[0-3])$"
|
||||
minItems: 1
|
||||
maxItems: 14
|
||||
|
||||
|
|
|
|||
|
|
@ -25,7 +25,9 @@ properties:
|
|||
- const: south
|
||||
- const: north
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
@ -129,6 +131,6 @@ examples:
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 180>;
|
||||
gpio-ranges = <&tlmm 0 0 181>; /* GPIOs + ufs_reset */
|
||||
wakeup-parent = <&pdc>;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -22,11 +22,20 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
gpio-reserved-ranges: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 102
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 203
|
||||
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
|
@ -61,7 +70,7 @@ $defs:
|
|||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-3])$"
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-2])$"
|
||||
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
|
@ -100,6 +109,7 @@ $defs:
|
|||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
drive-strength: true
|
||||
input-disable: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
|
@ -120,7 +130,7 @@ examples:
|
|||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 203>;
|
||||
gpio-ranges = <&tlmm 0 0 204>; /* GPIOs + ufs_reset */
|
||||
|
||||
gpio-wo-subnode-state {
|
||||
pins = "gpio1";
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ $defs:
|
|||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
pattern: "^gpio([0-9]|[1-2][0-9])$"
|
||||
pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
|
||||
|
||||
function:
|
||||
enum: [ swr_tx_clk, swr_tx_data, swr_rx_clk, swr_rx_data,
|
||||
|
|
@ -96,14 +96,12 @@ $defs:
|
|||
2: Lower Slew rate (slower edges)
|
||||
3: Reserved (No adjustments)
|
||||
|
||||
bias-bus-hold: true
|
||||
bias-pull-down: true
|
||||
|
||||
bias-pull-up: true
|
||||
|
||||
bias-disable: true
|
||||
|
||||
input-enable: true
|
||||
output-high: true
|
||||
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
|
|
|
|||
|
|
@ -22,7 +22,9 @@ properties:
|
|||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
|
@ -32,7 +34,7 @@ properties:
|
|||
maxItems: 105
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 209
|
||||
maxItems: 210
|
||||
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
|
|
|
|||
|
|
@ -0,0 +1,148 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm SM8550 SoC LPASS LPI TLMM
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
|
||||
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
|
||||
(LPASS) Low Power Island (LPI) of Qualcomm SM8550 SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8550-lpass-lpi-pinctrl
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: LPASS LPI TLMM Control and Status registers
|
||||
- description: LPASS LPI pins SLEW registers
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: LPASS Core voting clock
|
||||
- description: LPASS Audio voting clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: core
|
||||
- const: audio
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
"#gpio-cells":
|
||||
description: Specifying the pin number and flags, as defined in
|
||||
include/dt-bindings/gpio/gpio.h
|
||||
const: 2
|
||||
|
||||
gpio-ranges:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sm8550-lpass-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sm8550-lpass-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sm8550-lpass-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: /schemas/pinctrl/pincfg-node.yaml
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
|
||||
|
||||
function:
|
||||
enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
|
||||
dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,
|
||||
ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,
|
||||
i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
|
||||
i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, i2s4_clk,
|
||||
i2s4_data, i2s4_ws, slimbus_clk, slimbus_data, swr_rx_clk,
|
||||
swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk,
|
||||
wsa_swr_data, wsa2_swr_clk, wsa2_swr_data ]
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
|
||||
drive-strength:
|
||||
enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
default: 2
|
||||
description:
|
||||
Selects the drive strength for the specified pins, in mA.
|
||||
|
||||
slew-rate:
|
||||
enum: [0, 1, 2, 3]
|
||||
default: 0
|
||||
description: |
|
||||
0: No adjustments
|
||||
1: Higher Slew rate (faster edges)
|
||||
2: Lower Slew rate (slower edges)
|
||||
3: Reserved (No adjustments)
|
||||
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
bias-disable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
- $ref: pinctrl.yaml#
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- gpio-controller
|
||||
- "#gpio-cells"
|
||||
- gpio-ranges
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
|
||||
|
||||
lpass_tlmm: pinctrl@6e80000 {
|
||||
compatible = "qcom,sm8550-lpass-lpi-pinctrl";
|
||||
reg = <0x06e80000 0x20000>,
|
||||
<0x0725a000 0x10000>;
|
||||
|
||||
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
|
||||
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
|
||||
clock-names = "core", "audio";
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&lpass_tlmm 0 0 23>;
|
||||
|
||||
tx-swr-sleep-clk-state {
|
||||
pins = "gpio0";
|
||||
function = "swr_tx_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-tlmm.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. SM8550 TLMM block
|
||||
|
||||
maintainers:
|
||||
- Abel Vesa <abel.vesa@linaro.org>
|
||||
|
||||
description:
|
||||
Top Level Mode Multiplexer pin controller in Qualcomm SM8550 SoC.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,sm8550-tlmm
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts: true
|
||||
interrupt-controller: true
|
||||
"#interrupt-cells": true
|
||||
gpio-controller: true
|
||||
|
||||
gpio-reserved-ranges:
|
||||
minItems: 1
|
||||
maxItems: 105
|
||||
|
||||
gpio-line-names:
|
||||
maxItems: 210
|
||||
|
||||
"#gpio-cells": true
|
||||
gpio-ranges: true
|
||||
wakeup-parent: true
|
||||
|
||||
patternProperties:
|
||||
"-state$":
|
||||
oneOf:
|
||||
- $ref: "#/$defs/qcom-sm8550-tlmm-state"
|
||||
- patternProperties:
|
||||
"-pins$":
|
||||
$ref: "#/$defs/qcom-sm8550-tlmm-state"
|
||||
additionalProperties: false
|
||||
|
||||
$defs:
|
||||
qcom-sm8550-tlmm-state:
|
||||
type: object
|
||||
description:
|
||||
Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
Client device subnodes use below standard properties.
|
||||
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
|
||||
|
||||
properties:
|
||||
pins:
|
||||
description:
|
||||
List of gpio pins affected by the properties specified in this
|
||||
subnode.
|
||||
items:
|
||||
oneOf:
|
||||
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
|
||||
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
|
||||
minItems: 1
|
||||
maxItems: 36
|
||||
|
||||
function:
|
||||
description:
|
||||
Specify the alternative function to be configured for the specified
|
||||
pins.
|
||||
enum: [ aon_cci, aoss_cti, atest_char, atest_usb,
|
||||
audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk,
|
||||
cam_aon_mclk4, cam_mclk, cci_async_in, cci_i2c_scl,
|
||||
cci_i2c_sda, cci_timer, cmu_rng, coex_uart1_rx,
|
||||
coex_uart1_tx, coex_uart2_rx, coex_uart2_tx,
|
||||
cri_trng, dbg_out_clk, ddr_bist_complete,
|
||||
ddr_bist_fail, ddr_bist_start, ddr_bist_stop,
|
||||
ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, dp_hot,
|
||||
gcc_gp1, gcc_gp2, gcc_gp3, gpio, i2chub0_se0,
|
||||
i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4,
|
||||
i2chub0_se5, i2chub0_se6, i2chub0_se7, i2chub0_se8,
|
||||
i2chub0_se9, i2s0_data0, i2s0_data1, i2s0_sck,
|
||||
i2s0_ws, i2s1_data0, i2s1_data1, i2s1_sck, i2s1_ws,
|
||||
ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0_out,
|
||||
mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,
|
||||
mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2,
|
||||
pcie0_clk_req_n, pcie1_clk_req_n, phase_flag,
|
||||
pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
|
||||
prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio,
|
||||
qlink0_enable, qlink0_request, qlink0_wmss,
|
||||
qlink1_enable, qlink1_request, qlink1_wmss,
|
||||
qlink2_enable, qlink2_request, qlink2_wmss,
|
||||
qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs,
|
||||
qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
|
||||
qup1_se5, qup1_se6, qup1_se7, qup2_se0,
|
||||
qup2_se0_l0_mira, qup2_se0_l0_mirb, qup2_se0_l1_mira,
|
||||
qup2_se0_l1_mirb, qup2_se0_l2_mira, qup2_se0_l2_mirb,
|
||||
qup2_se0_l3_mira, qup2_se0_l3_mirb, qup2_se1,
|
||||
qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6,
|
||||
qup2_se7, sd_write_protect, sdc40, sdc41, sdc42,
|
||||
sdc43, sdc4_clk, sdc4_cmd, tb_trig_sdc2, tb_trig_sdc4,
|
||||
tgu_ch0_trigout, tgu_ch1_trigout, tgu_ch2_trigout,
|
||||
tgu_ch3_trigout, tmess_prng0, tmess_prng1, tmess_prng2,
|
||||
tmess_prng3, tsense_pwm1, tsense_pwm2, tsense_pwm3,
|
||||
uim0_clk, uim0_data, uim0_present, uim0_reset,
|
||||
uim1_clk, uim1_data, uim1_present, uim1_reset,
|
||||
usb1_hs, usb_phy, vfr_0, vfr_1, vsense_trigger_mirnat ]
|
||||
|
||||
bias-disable: true
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
drive-strength: true
|
||||
input-enable: true
|
||||
output-high: true
|
||||
output-low: true
|
||||
|
||||
required:
|
||||
- pins
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
tlmm: pinctrl@f100000 {
|
||||
compatible = "qcom,sm8550-tlmm";
|
||||
reg = <0x0f100000 0x300000>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&tlmm 0 0 211>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gpio-wo-state {
|
||||
pins = "gpio1";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
uart-w-state {
|
||||
rx-pins {
|
||||
pins = "gpio26";
|
||||
function = "qup2_se7";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
tx-pins {
|
||||
pins = "gpio27";
|
||||
function = "qup2_se7";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -16,8 +16,9 @@ description:
|
|||
properties:
|
||||
interrupts:
|
||||
description:
|
||||
Specifies the TLMM summary IRQ
|
||||
maxItems: 1
|
||||
TLMM summary IRQ and dirconn interrupts.
|
||||
minItems: 1
|
||||
maxItems: 9
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
|
|
|
|||
|
|
@ -29,47 +29,609 @@ patternProperties:
|
|||
$ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
groups:
|
||||
description: The pin group to select.
|
||||
enum: [
|
||||
# common
|
||||
i2c, spi, wdt,
|
||||
|
||||
# For MT7620 SoC
|
||||
ephy, mdio, nd_sd, pa, pcie, rgmii1, rgmii2, spi refclk,
|
||||
uartf, uartlite, wled,
|
||||
|
||||
# For MT7628 and MT7688 SoCs
|
||||
gpio, i2s, p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an,
|
||||
p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn, perst, pwm0,
|
||||
pwm1, refclk, sdmode, spi cs1, spis, uart0, uart1, uart2,
|
||||
wled_an, wled_kn,
|
||||
]
|
||||
|
||||
function:
|
||||
description: The mux function to select.
|
||||
enum: [
|
||||
# common
|
||||
gpio, i2c, refclk, spi,
|
||||
description:
|
||||
A string containing the name of the function to mux to the group.
|
||||
anyOf:
|
||||
- description: For MT7620 SoC
|
||||
enum: [ephy, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, mdio, nand, pa,
|
||||
pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf, refclk,
|
||||
rgmii1, rgmii2, sd, spi, spi refclk, uartf, uartlite, wdt refclk,
|
||||
wdt rst, wled]
|
||||
|
||||
# For MT7620 SoC
|
||||
ephy, gpio i2s, gpio uartf, i2s uartf, mdio, nand, pa,
|
||||
pcie refclk, pcie rst, pcm gpio, pcm i2s, pcm uartf,
|
||||
rgmii1, rgmii2, sd, spi refclk, uartf, uartlite, wdt refclk,
|
||||
wdt rst, wled,
|
||||
- description: For MT7628 and MT7688 SoCs
|
||||
enum: [antenna, debug, gpio, i2c, i2s, jtag, p0led_an, p0led_kn,
|
||||
p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn,
|
||||
p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, pwm_uart2,
|
||||
refclk, rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi, spi cs1,
|
||||
spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an, wled_kn, -]
|
||||
|
||||
# For MT7628 and MT7688 SoCs
|
||||
antenna, debug, i2s, jtag, p0led_an, p0led_kn,
|
||||
p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn,
|
||||
p4led_an, p4led_kn, pcie, pcm, perst, pwm, pwm0, pwm1, pwm_uart2,
|
||||
rsvd, sdxc, sdxc d5 d4, sdxc d6, sdxc d7, spi cs1,
|
||||
spis, sw_r, uart0, uart1, uart2, utif, wdt, wled_an, wled_kn, -,
|
||||
]
|
||||
groups:
|
||||
description:
|
||||
An array of strings. Each string contains the name of a group.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- groups
|
||||
- function
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: antenna
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [i2s]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: debug
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [i2c]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: ephy
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [ephy]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: gpio
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
anyOf:
|
||||
- description: For MT7620 SoC
|
||||
enum: [ephy, i2c, mdio, nd_sd, pa, pcie, rgmii1, rgmii2,
|
||||
spi, spi refclk, uartf, uartlite, wdt, wled]
|
||||
|
||||
- description: For MT7628 and MT7688 SoCs
|
||||
enum: [gpio, i2c, i2s, p0led_an, p0led_kn, p1led_an,
|
||||
p1led_kn, p2led_an, p2led_kn, p3led_an, p3led_kn,
|
||||
p4led_an, p4led_kn, perst, pwm0, pwm1, refclk,
|
||||
sdmode, spi, spi cs1, spis, uart0, uart1, uart2,
|
||||
wdt, wled_an, wled_kn]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: gpio i2s
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: gpio uartf
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: i2c
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [i2c]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: i2s
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [i2s]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: i2s uartf
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: jtag
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [p0led_an, p0led_kn, p1led_an, p1led_kn, p2led_an,
|
||||
p2led_kn, p3led_an, p3led_kn, p4led_an, p4led_kn,
|
||||
sdmode]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: mdio
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [mdio]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: nand
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [nd_sd]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: p0led_an
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [p0led_an]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: p0led_kn
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [p0led_kn]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: p1led_an
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [p1led_an]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: p1led_kn
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [p1led_kn]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: p2led_an
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [p2led_an]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: p2led_kn
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [p2led_kn]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: p3led_an
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [p3led_an]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: p3led_kn
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [p3led_kn]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: p4led_an
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [p4led_an]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: p4led_kn
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [p4led_kn]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pa
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pa]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcie
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [gpio]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcie refclk
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pcie]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcie rst
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pcie]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcm
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [i2s]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcm gpio
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcm i2s
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcm uartf
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: perst
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [perst]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pwm
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uart1, uart2]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pwm0
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pwm0]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pwm1
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pwm1]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pwm_uart2
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [spis]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: refclk
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
anyOf:
|
||||
- description: For MT7620 SoC
|
||||
enum: [mdio]
|
||||
|
||||
- description: For MT7628 and MT7688 SoCs
|
||||
enum: [gpio, refclk, spi cs1]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: rgmii1
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [rgmii1]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: rgmii2
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [rgmii2]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: rsvd
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [p0led_an, p0led_kn, wled_an, wled_kn]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: sd
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [nd_sd]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: sdxc
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [sdmode]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: sdxc d5 d4
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uart2]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: sdxc d6
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pwm1]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: sdxc d7
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pwm0]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spi
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [spi]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spi cs1
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [spi cs1]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spi refclk
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [spi refclk]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spis
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [spis]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: sw_r
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uart1]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uart0
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uart0]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uart1
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uart1]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uart2
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uart2]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uartf
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uartlite
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartlite]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: utif
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [p1led_an, p1led_kn, p2led_an, p2led_kn, p3led_an,
|
||||
p3led_kn, p4led_an, p4led_kn, pwm0, pwm1, sdmode, spis]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: wdt
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [wdt]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: wdt refclk
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [wdt]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: wdt rst
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [wdt]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: wled
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [wled]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: wled_an
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [wled_an]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: wled_kn
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [wled_kn]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: "-"
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [i2c, spi cs1, uart0]
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -83,7 +645,6 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
pinctrl {
|
||||
compatible = "ralink,mt7620-pinctrl";
|
||||
|
|
|
|||
|
|
@ -29,21 +29,213 @@ patternProperties:
|
|||
$ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
groups:
|
||||
description: The pin group to select.
|
||||
enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi, uart1,
|
||||
uart2, uart3, wdt]
|
||||
|
||||
function:
|
||||
description: The mux function to select.
|
||||
description:
|
||||
A string containing the name of the function to mux to the group.
|
||||
enum: [gpio, i2c, i2s, jtag, mdio, nand1, nand2, pcie refclk,
|
||||
pcie rst, pcm, rgmii1, rgmii2, sdhci, spdif2, spdif3, spi,
|
||||
uart1, uart2, uart3, wdt refclk, wdt rst]
|
||||
|
||||
groups:
|
||||
description:
|
||||
An array of strings. Each string contains the name of a group.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- groups
|
||||
- function
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: gpio
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [i2c, jtag, mdio, pcie, rgmii1, rgmii2, sdhci, spi,
|
||||
uart1, uart2, uart3, wdt]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: i2c
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [i2c]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: i2s
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uart3]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: jtag
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [jtag]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: mdio
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [mdio]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: nand1
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [spi]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: nand2
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [sdhci]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcie refclk
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pcie]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcie rst
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pcie]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcm
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uart2]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: rgmii1
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [rgmii1]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: rgmii2
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [rgmii2]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: sdhci
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [sdhci]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spdif2
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uart2]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spdif3
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uart3]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spi
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [spi]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uart1
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uart1]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uart2
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uart2]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uart3
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uart3]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: wdt refclk
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [wdt]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: wdt rst
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [wdt]
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -57,7 +249,6 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
pinctrl {
|
||||
compatible = "ralink,mt7621-pinctrl";
|
||||
|
|
|
|||
|
|
@ -29,18 +29,93 @@ patternProperties:
|
|||
$ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
groups:
|
||||
description: The pin group to select.
|
||||
enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci]
|
||||
|
||||
function:
|
||||
description: The mux function to select.
|
||||
description:
|
||||
A string containing the name of the function to mux to the group.
|
||||
enum: [gpio, i2c, spi, uartlite, jtag, mdio, sdram, pci]
|
||||
|
||||
groups:
|
||||
description:
|
||||
An array of strings. Each string contains the name of a group.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- groups
|
||||
- function
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: gpio
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [i2c, spi, uartlite, jtag, mdio, sdram, pci]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: i2c
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [i2c]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spi
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [spi]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uartlite
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartlite]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: jtag
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [jtag]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: mdio
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [mdio]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: sdram
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [sdram]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pci
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pci]
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -54,7 +129,6 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
pinctrl {
|
||||
compatible = "ralink,rt2880-pinctrl";
|
||||
|
|
|
|||
|
|
@ -30,38 +30,225 @@ patternProperties:
|
|||
$ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
groups:
|
||||
description: The pin group to select.
|
||||
enum: [
|
||||
# common
|
||||
i2c, jtag, led, mdio, rgmii, spi, spi_cs1, uartf, uartlite,
|
||||
|
||||
# For RT3050, RT3052 and RT3350 SoCs
|
||||
sdram,
|
||||
|
||||
# For RT3352 SoC
|
||||
lna, pa
|
||||
]
|
||||
|
||||
function:
|
||||
description: The mux function to select.
|
||||
enum: [
|
||||
# common
|
||||
gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led, mdio,
|
||||
pcm gpio, pcm i2s, pcm uartf, rgmii, spi, spi_cs1, uartf,
|
||||
uartlite, wdg_cs1,
|
||||
description:
|
||||
A string containing the name of the function to mux to the group.
|
||||
anyOf:
|
||||
- description: For RT3050, RT3052 and RT3350 SoCs
|
||||
enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, mdio,
|
||||
pcm gpio, pcm i2s, pcm uartf, rgmii, sdram, spi, uartf,
|
||||
uartlite]
|
||||
|
||||
# For RT3050, RT3052 and RT3350 SoCs
|
||||
sdram,
|
||||
- description: For RT3352 SoC
|
||||
enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led,
|
||||
lna, mdio, pa, pcm gpio, pcm i2s, pcm uartf, rgmii, spi,
|
||||
spi_cs1, uartf, uartlite, wdg_cs1]
|
||||
|
||||
# For RT3352 SoC
|
||||
lna, pa
|
||||
]
|
||||
- description: For RT5350 SoC
|
||||
enum: [gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag, led,
|
||||
pcm gpio, pcm i2s, pcm uartf, spi, spi_cs1, uartf,
|
||||
uartlite, wdg_cs1]
|
||||
|
||||
groups:
|
||||
description:
|
||||
An array of strings. Each string contains the name of a group.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- groups
|
||||
- function
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: gpio
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
anyOf:
|
||||
- description: For RT3050, RT3052 and RT3350 SoCs
|
||||
enum: [i2c, jtag, mdio, rgmii, sdram, spi, uartf,
|
||||
uartlite]
|
||||
|
||||
- description: For RT3352 SoC
|
||||
enum: [i2c, jtag, led, lna, mdio, pa, rgmii, spi, spi_cs1,
|
||||
uartf, uartlite]
|
||||
|
||||
- description: For RT5350 SoC
|
||||
enum: [i2c, jtag, led, spi, spi_cs1, uartf, uartlite]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: gpio i2s
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: gpio uartf
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: i2c
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [i2c]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: i2s uartf
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: jtag
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [jtag]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: led
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [led]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: lna
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [lna]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: mdio
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [mdio]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pa
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pa]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcm gpio
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcm i2s
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcm uartf
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: rgmii
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [rgmii]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: sdram
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [sdram]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spi
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [spi]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spi_cs1
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [spi_cs1]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uartf
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uartlite
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartlite]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: wdg_cs1
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [spi_cs1]
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -75,7 +262,6 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
pinctrl {
|
||||
compatible = "ralink,rt305x-pinctrl";
|
||||
|
|
|
|||
|
|
@ -29,21 +29,213 @@ patternProperties:
|
|||
$ref: pinmux-node.yaml#
|
||||
|
||||
properties:
|
||||
groups:
|
||||
description: The pin group to select.
|
||||
enum: [ge1, ge2, i2c, jtag, lna a, lna g, mdio, pci, spi, uartf,
|
||||
uartlite]
|
||||
|
||||
function:
|
||||
description: The mux function to select.
|
||||
description:
|
||||
A string containing the name of the function to mux to the group.
|
||||
enum: [ge1, ge2, gpio, gpio i2s, gpio uartf, i2c, i2s uartf, jtag,
|
||||
lna a, lna g, mdio, pci-dev, pci-fnc, pci-host1, pci-host2,
|
||||
pcm gpio, pcm i2s, pcm uartf, spi, uartf, uartlite]
|
||||
|
||||
groups:
|
||||
description:
|
||||
An array of strings. Each string contains the name of a group.
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- groups
|
||||
- function
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: ge1
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [ge1]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: ge2
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [ge2]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: gpio
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [ge1, ge2, i2c, jtag, lna a, lna g, mdio, pci, spi,
|
||||
uartf, uartlite]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: gpio i2s
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: gpio uartf
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: i2c
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [i2c]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: i2s uartf
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: jtag
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [jtag]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: lna a
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [lna a]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: lna g
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [lna g]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: mdio
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [mdio]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pci-dev
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pci]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pci-fnc
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pci]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pci-host1
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pci]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pci-host2
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [pci]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcm gpio
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcm i2s
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: pcm uartf
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spi
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [spi]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uartf
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartf]
|
||||
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uartlite
|
||||
then:
|
||||
properties:
|
||||
groups:
|
||||
enum: [uartlite]
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
|
@ -57,7 +249,6 @@ required:
|
|||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Pinmux controller node
|
||||
- |
|
||||
pinctrl {
|
||||
compatible = "ralink,rt3883-pinctrl";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,86 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-poeg.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/G2L Port Output Enable for GPT (POEG)
|
||||
|
||||
maintainers:
|
||||
- Biju Das <biju.das.jz@bp.renesas.com>
|
||||
|
||||
description: |
|
||||
The output pins(GTIOCxA and GTIOCxB) of the general PWM timer (GPT) can be
|
||||
disabled by using the port output enabling function for the GPT (POEG).
|
||||
Specifically, either of the following ways can be used.
|
||||
* Input level detection of the GTETRGA to GTETRGD pins.
|
||||
* Output-disable request from the GPT.
|
||||
* SSF bit setting(ie, by setting POEGGn.SSF to 1)
|
||||
|
||||
The state of the GTIOCxA and the GTIOCxB pins when the output is disabled,
|
||||
are controlled by the GPT module.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r9a07g044-poeg # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-poeg # RZ/V2L
|
||||
- const: renesas,rzg2l-poeg
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
renesas,gpt:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: phandle to gpt instance that serves the pwm operation.
|
||||
|
||||
renesas,poeg-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
enum: [ 0, 1, 2, 3 ]
|
||||
description: |
|
||||
POEG group index. Valid values are:
|
||||
<0> : POEG group A
|
||||
<1> : POEG group B
|
||||
<2> : POEG group C
|
||||
<3> : POEG group D
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- power-domains
|
||||
- resets
|
||||
- renesas,poeg-id
|
||||
- renesas,gpt
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/r9a07g044-cpg.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
poeggd: poeg@10049400 {
|
||||
compatible = "renesas,r9a07g044-poeg", "renesas,rzg2l-poeg";
|
||||
reg = <0x10049400 0x400>;
|
||||
interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD R9A07G044_POEG_D_CLKP>;
|
||||
power-domains = <&cpg>;
|
||||
resets = <&cpg R9A07G044_POEG_D_RST>;
|
||||
renesas,poeg-id = <3>;
|
||||
renesas,gpt = <&gpt>;
|
||||
};
|
||||
|
|
@ -76,15 +76,13 @@ allOf:
|
|||
required:
|
||||
- compatible
|
||||
- rockchip,grf
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- ranges
|
||||
|
||||
patternProperties:
|
||||
"gpio@[0-9a-f]+$":
|
||||
type: object
|
||||
|
||||
$ref: "/schemas/gpio/rockchip,gpio-bank.yaml#"
|
||||
deprecated: true
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,124 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: StarFive JH7110 AON Pin Controller
|
||||
|
||||
description: |
|
||||
Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
|
||||
|
||||
Out of the SoC's many pins only the ones named PAD_RGPIO0 to PAD_RGPIO3
|
||||
can be multiplexed and have configurable bias, drive strength,
|
||||
schmitt trigger etc.
|
||||
Some peripherals such as PWM have their I/O go through the 4 "GPIOs".
|
||||
|
||||
maintainers:
|
||||
- Jianlong Huang <jianlong.huang@starfivetech.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: starfive,jh7110-aon-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
const: 2
|
||||
|
||||
patternProperties:
|
||||
'-[0-9]+$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
description: |
|
||||
A pinctrl node should contain at least one subnode representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to
|
||||
muxer configuration, bias, input enable/disable, input schmitt
|
||||
trigger enable/disable, slew-rate and drive strength.
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/pincfg-node.yaml
|
||||
- $ref: /schemas/pinctrl/pinmux-node.yaml
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
description: |
|
||||
The list of GPIOs and their mux settings that properties in the
|
||||
node apply to. This should be set using the GPIOMUX macro.
|
||||
|
||||
bias-disable: true
|
||||
|
||||
bias-pull-up:
|
||||
type: boolean
|
||||
|
||||
bias-pull-down:
|
||||
type: boolean
|
||||
|
||||
drive-strength:
|
||||
enum: [ 2, 4, 8, 12 ]
|
||||
|
||||
input-enable: true
|
||||
|
||||
input-disable: true
|
||||
|
||||
input-schmitt-enable: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
slew-rate:
|
||||
maximum: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pinctrl@17020000 {
|
||||
compatible = "starfive,jh7110-aon-pinctrl";
|
||||
reg = <0x17020000 0x10000>;
|
||||
resets = <&aoncrg 2>;
|
||||
interrupts = <85>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
pwm-0 {
|
||||
pwm-pins {
|
||||
pinmux = <0xff030802>;
|
||||
bias-disable;
|
||||
drive-strength = <12>;
|
||||
input-disable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,142 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: StarFive JH7110 SYS Pin Controller
|
||||
|
||||
description: |
|
||||
Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
|
||||
|
||||
Out of the SoC's many pins only the ones named PAD_GPIO0 to PAD_GPIO63
|
||||
can be multiplexed and have configurable bias, drive strength,
|
||||
schmitt trigger etc.
|
||||
Some peripherals have their I/O go through the 64 "GPIOs". This also
|
||||
includes a number of other UARTs, I2Cs, SPIs, PWMs etc.
|
||||
All these peripherals are connected to all 64 GPIOs such that
|
||||
any GPIO can be set up to be controlled by any of the peripherals.
|
||||
|
||||
maintainers:
|
||||
- Jianlong Huang <jianlong.huang@starfivetech.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: starfive,jh7110-sys-pinctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
|
||||
gpio-controller: true
|
||||
|
||||
'#gpio-cells':
|
||||
const: 2
|
||||
|
||||
patternProperties:
|
||||
'-[0-9]+$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
patternProperties:
|
||||
'-pins$':
|
||||
type: object
|
||||
description: |
|
||||
A pinctrl node should contain at least one subnode representing the
|
||||
pinctrl groups available on the machine. Each subnode will list the
|
||||
pins it needs, and how they should be configured, with regard to
|
||||
muxer configuration, bias, input enable/disable, input schmitt
|
||||
trigger enable/disable, slew-rate and drive strength.
|
||||
allOf:
|
||||
- $ref: /schemas/pinctrl/pincfg-node.yaml
|
||||
- $ref: /schemas/pinctrl/pinmux-node.yaml
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
pinmux:
|
||||
description: |
|
||||
The list of GPIOs and their mux settings that properties in the
|
||||
node apply to. This should be set using the GPIOMUX or PINMUX
|
||||
macros.
|
||||
|
||||
bias-disable: true
|
||||
|
||||
bias-pull-up:
|
||||
type: boolean
|
||||
|
||||
bias-pull-down:
|
||||
type: boolean
|
||||
|
||||
drive-strength:
|
||||
enum: [ 2, 4, 8, 12 ]
|
||||
|
||||
input-enable: true
|
||||
|
||||
input-disable: true
|
||||
|
||||
input-schmitt-enable: true
|
||||
|
||||
input-schmitt-disable: true
|
||||
|
||||
slew-rate:
|
||||
maximum: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- gpio-controller
|
||||
- '#gpio-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pinctrl@13040000 {
|
||||
compatible = "starfive,jh7110-sys-pinctrl";
|
||||
reg = <0x13040000 0x10000>;
|
||||
clocks = <&syscrg 112>;
|
||||
resets = <&syscrg 2>;
|
||||
interrupts = <86>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
uart0-0 {
|
||||
tx-pins {
|
||||
pinmux = <0xff140005>;
|
||||
bias-disable;
|
||||
drive-strength = <12>;
|
||||
input-disable;
|
||||
input-schmitt-disable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
|
||||
rx-pins {
|
||||
pinmux = <0x0E000406>;
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
input-enable;
|
||||
input-schmitt-enable;
|
||||
slew-rate = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -19824,13 +19824,15 @@ F: Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml
|
|||
F: drivers/clk/starfive/clk-starfive-jh7100*
|
||||
F: include/dt-bindings/clock/starfive-jh7100*.h
|
||||
|
||||
STARFIVE JH7100 PINCTRL DRIVER
|
||||
STARFIVE JH71X0 PINCTRL DRIVERS
|
||||
M: Emil Renner Berthing <kernel@esmil.dk>
|
||||
M: Jianlong Huang <jianlong.huang@starfivetech.com>
|
||||
L: linux-gpio@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
|
||||
F: drivers/pinctrl/starfive/
|
||||
F: Documentation/devicetree/bindings/pinctrl/starfive,jh71*.yaml
|
||||
F: drivers/pinctrl/starfive/pinctrl-starfive-jh71*
|
||||
F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
|
||||
F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h
|
||||
|
||||
STARFIVE JH7100 RESET CONTROLLER DRIVER
|
||||
M: Emil Renner Berthing <kernel@esmil.dk>
|
||||
|
|
|
|||
|
|
@ -980,11 +980,6 @@ static int of_gpiochip_add_pin_range(struct gpio_chip *chip)
|
|||
if (!np)
|
||||
return 0;
|
||||
|
||||
if (!of_property_read_bool(np, "gpio-ranges") &&
|
||||
chip->of_gpio_ranges_fallback) {
|
||||
return chip->of_gpio_ranges_fallback(chip, np);
|
||||
}
|
||||
|
||||
group_names = of_find_property(np, group_names_propname, NULL);
|
||||
|
||||
for (;; index++) {
|
||||
|
|
|
|||
|
|
@ -532,6 +532,14 @@ static void gpiochip_free_valid_mask(struct gpio_chip *gc)
|
|||
|
||||
static int gpiochip_add_pin_ranges(struct gpio_chip *gc)
|
||||
{
|
||||
/*
|
||||
* Device Tree platforms are supposed to use "gpio-ranges"
|
||||
* property. This check ensures that the ->add_pin_ranges()
|
||||
* won't be called for them.
|
||||
*/
|
||||
if (device_property_present(&gc->gpiodev->dev, "gpio-ranges"))
|
||||
return 0;
|
||||
|
||||
if (gc->add_pin_ranges)
|
||||
return gc->add_pin_ranges(gc);
|
||||
|
||||
|
|
|
|||
|
|
@ -172,7 +172,7 @@ config PINCTRL_DA9062
|
|||
|
||||
config PINCTRL_DIGICOLOR
|
||||
bool
|
||||
depends on OF && (ARCH_DIGICOLOR || COMPILE_TEST)
|
||||
depends on ARCH_DIGICOLOR || COMPILE_TEST
|
||||
select PINMUX
|
||||
select GENERIC_PINCONF
|
||||
|
||||
|
|
|
|||
|
|
@ -358,13 +358,11 @@ static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835_of_gpio_ranges_fallback(struct gpio_chip *gc,
|
||||
struct device_node *np)
|
||||
static int bcm2835_add_pin_ranges_fallback(struct gpio_chip *gc)
|
||||
{
|
||||
struct device_node *np = dev_of_node(gc->parent);
|
||||
struct pinctrl_dev *pctldev = of_pinctrl_get(np);
|
||||
|
||||
of_node_put(np);
|
||||
|
||||
if (!pctldev)
|
||||
return 0;
|
||||
|
||||
|
|
@ -388,7 +386,7 @@ static const struct gpio_chip bcm2835_gpio_chip = {
|
|||
.base = -1,
|
||||
.ngpio = BCM2835_NUM_GPIOS,
|
||||
.can_sleep = false,
|
||||
.of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
|
||||
.add_pin_ranges = bcm2835_add_pin_ranges_fallback,
|
||||
};
|
||||
|
||||
static const struct gpio_chip bcm2711_gpio_chip = {
|
||||
|
|
@ -405,7 +403,7 @@ static const struct gpio_chip bcm2711_gpio_chip = {
|
|||
.base = -1,
|
||||
.ngpio = BCM2711_NUM_GPIOS,
|
||||
.can_sleep = false,
|
||||
.of_gpio_ranges_fallback = bcm2835_of_gpio_ranges_fallback,
|
||||
.add_pin_ranges = bcm2835_add_pin_ranges_fallback,
|
||||
};
|
||||
|
||||
static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
|
||||
|
|
|
|||
|
|
@ -269,9 +269,9 @@ static int mxs_pinconf_group_set(struct pinctrl_dev *pctldev,
|
|||
for (n = 0; n < num_configs; n++) {
|
||||
config = configs[n];
|
||||
|
||||
ma = CONFIG_TO_MA(config);
|
||||
vol = CONFIG_TO_VOL(config);
|
||||
pull = CONFIG_TO_PULL(config);
|
||||
ma = PIN_CONFIG_TO_MA(config);
|
||||
vol = PIN_CONFIG_TO_VOL(config);
|
||||
pull = PIN_CONFIG_TO_PULL(config);
|
||||
|
||||
for (i = 0; i < g->npins; i++) {
|
||||
bank = PINID_TO_BANK(g->pins[i]);
|
||||
|
|
|
|||
|
|
@ -44,9 +44,9 @@
|
|||
#define VOL_SHIFT 3
|
||||
#define MA_PRESENT (1 << 2)
|
||||
#define MA_SHIFT 0
|
||||
#define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
|
||||
#define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
|
||||
#define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
|
||||
#define PIN_CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1)
|
||||
#define PIN_CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1)
|
||||
#define PIN_CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3)
|
||||
|
||||
struct mxs_function {
|
||||
const char *name;
|
||||
|
|
|
|||
|
|
@ -34,25 +34,11 @@
|
|||
.gpio_base = (g), \
|
||||
}
|
||||
|
||||
#define ADL_COMMUNITY(b, s, e, g, v) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = ADL_##v##_PAD_OWN, \
|
||||
.padcfglock_offset = ADL_##v##_PADCFGLOCK, \
|
||||
.hostown_offset = ADL_##v##_HOSTSW_OWN, \
|
||||
.is_offset = ADL_##v##_GPI_IS, \
|
||||
.ie_offset = ADL_##v##_GPI_IE, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
|
||||
#define ADL_N_COMMUNITY(b, s, e, g) \
|
||||
ADL_COMMUNITY(b, s, e, g, N)
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, ADL_N)
|
||||
|
||||
#define ADL_S_COMMUNITY(b, s, e, g) \
|
||||
ADL_COMMUNITY(b, s, e, g, S)
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, ADL_S)
|
||||
|
||||
/* Alder Lake-N */
|
||||
static const struct pinctrl_pin_desc adln_pins[] = {
|
||||
|
|
|
|||
|
|
@ -637,18 +637,18 @@ static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return vg->soc->functions[selector].name;
|
||||
return vg->soc->functions[selector].func.name;
|
||||
}
|
||||
|
||||
static int byt_get_function_groups(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector,
|
||||
const char * const **groups,
|
||||
unsigned int *num_groups)
|
||||
unsigned int *ngroups)
|
||||
{
|
||||
struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*groups = vg->soc->functions[selector].groups;
|
||||
*num_groups = vg->soc->functions[selector].ngroups;
|
||||
*groups = vg->soc->functions[selector].func.groups;
|
||||
*ngroups = vg->soc->functions[selector].func.ngroups;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -722,7 +722,7 @@ static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
|
|||
|
||||
if (group.modes)
|
||||
byt_set_group_mixed_mux(vg, group, group.modes);
|
||||
else if (!strcmp(func.name, "gpio"))
|
||||
else if (!strcmp(func.func.name, "gpio"))
|
||||
byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
|
||||
else
|
||||
byt_set_group_simple_mux(vg, group, group.mode);
|
||||
|
|
|
|||
|
|
@ -20,17 +20,8 @@
|
|||
#define BXT_GPI_IS 0x100
|
||||
#define BXT_GPI_IE 0x110
|
||||
|
||||
#define BXT_COMMUNITY(s, e) \
|
||||
{ \
|
||||
.padown_offset = BXT_PAD_OWN, \
|
||||
.padcfglock_offset = BXT_PADCFGLOCK, \
|
||||
.hostown_offset = BXT_HOSTSW_OWN, \
|
||||
.is_offset = BXT_GPI_IS, \
|
||||
.ie_offset = BXT_GPI_IE, \
|
||||
.gpp_size = 32, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
}
|
||||
#define BXT_COMMUNITY(b, s, e) \
|
||||
INTEL_COMMUNITY_SIZE(b, s, e, 32, 4, BXT)
|
||||
|
||||
/* BXT */
|
||||
static const struct pinctrl_pin_desc bxt_north_pins[] = {
|
||||
|
|
@ -172,7 +163,7 @@ static const struct intel_function bxt_north_functions[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community bxt_north_communities[] = {
|
||||
BXT_COMMUNITY(0, 82),
|
||||
BXT_COMMUNITY(0, 0, 82),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data bxt_north_soc_data = {
|
||||
|
|
@ -289,7 +280,7 @@ static const struct intel_function bxt_northwest_functions[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community bxt_northwest_communities[] = {
|
||||
BXT_COMMUNITY(0, 71),
|
||||
BXT_COMMUNITY(0, 0, 71),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data bxt_northwest_soc_data = {
|
||||
|
|
@ -396,7 +387,7 @@ static const struct intel_function bxt_west_functions[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community bxt_west_communities[] = {
|
||||
BXT_COMMUNITY(0, 41),
|
||||
BXT_COMMUNITY(0, 0, 41),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data bxt_west_soc_data = {
|
||||
|
|
@ -472,7 +463,7 @@ static const struct intel_function bxt_southwest_functions[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community bxt_southwest_communities[] = {
|
||||
BXT_COMMUNITY(0, 30),
|
||||
BXT_COMMUNITY(0, 0, 30),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data bxt_southwest_soc_data = {
|
||||
|
|
@ -511,7 +502,7 @@ static const struct pinctrl_pin_desc bxt_south_pins[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community bxt_south_communities[] = {
|
||||
BXT_COMMUNITY(0, 19),
|
||||
BXT_COMMUNITY(0, 0, 19),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data bxt_south_soc_data = {
|
||||
|
|
@ -650,7 +641,7 @@ static const struct intel_function apl_north_functions[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community apl_north_communities[] = {
|
||||
BXT_COMMUNITY(0, 77),
|
||||
BXT_COMMUNITY(0, 0, 77),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data apl_north_soc_data = {
|
||||
|
|
@ -770,7 +761,7 @@ static const struct intel_function apl_northwest_functions[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community apl_northwest_communities[] = {
|
||||
BXT_COMMUNITY(0, 76),
|
||||
BXT_COMMUNITY(0, 0, 76),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data apl_northwest_soc_data = {
|
||||
|
|
@ -880,7 +871,7 @@ static const struct intel_function apl_west_functions[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community apl_west_communities[] = {
|
||||
BXT_COMMUNITY(0, 46),
|
||||
BXT_COMMUNITY(0, 0, 46),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data apl_west_soc_data = {
|
||||
|
|
@ -972,7 +963,7 @@ static const struct intel_function apl_southwest_functions[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community apl_southwest_communities[] = {
|
||||
BXT_COMMUNITY(0, 42),
|
||||
BXT_COMMUNITY(0, 0, 42),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data apl_southwest_soc_data = {
|
||||
|
|
|
|||
|
|
@ -15,12 +15,17 @@
|
|||
|
||||
#include "pinctrl-intel.h"
|
||||
|
||||
#define CNL_PAD_OWN 0x020
|
||||
#define CNL_PADCFGLOCK 0x080
|
||||
#define CNL_LP_PAD_OWN 0x020
|
||||
#define CNL_LP_PADCFGLOCK 0x080
|
||||
#define CNL_LP_HOSTSW_OWN 0x0b0
|
||||
#define CNL_LP_GPI_IS 0x100
|
||||
#define CNL_LP_GPI_IE 0x120
|
||||
|
||||
#define CNL_H_PAD_OWN 0x020
|
||||
#define CNL_H_PADCFGLOCK 0x080
|
||||
#define CNL_H_HOSTSW_OWN 0x0c0
|
||||
#define CNL_GPI_IS 0x100
|
||||
#define CNL_GPI_IE 0x120
|
||||
#define CNL_H_GPI_IS 0x100
|
||||
#define CNL_H_GPI_IE 0x120
|
||||
|
||||
#define CNL_GPP(r, s, e, g) \
|
||||
{ \
|
||||
|
|
@ -30,25 +35,11 @@
|
|||
.gpio_base = (g), \
|
||||
}
|
||||
|
||||
#define CNL_COMMUNITY(b, s, e, g, v) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = CNL_PAD_OWN, \
|
||||
.padcfglock_offset = CNL_PADCFGLOCK, \
|
||||
.hostown_offset = CNL_##v##_HOSTSW_OWN, \
|
||||
.is_offset = CNL_GPI_IS, \
|
||||
.ie_offset = CNL_GPI_IE, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
|
||||
#define CNL_LP_COMMUNITY(b, s, e, g) \
|
||||
CNL_COMMUNITY(b, s, e, g, LP)
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_LP)
|
||||
|
||||
#define CNL_H_COMMUNITY(b, s, e, g) \
|
||||
CNL_COMMUNITY(b, s, e, g, H)
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, CNL_H)
|
||||
|
||||
/* Cannon Lake-H */
|
||||
static const struct pinctrl_pin_desc cnlh_pins[] = {
|
||||
|
|
|
|||
|
|
@ -28,18 +28,7 @@
|
|||
}
|
||||
|
||||
#define CDF_COMMUNITY(b, s, e, g) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = CDF_PAD_OWN, \
|
||||
.padcfglock_offset = CDF_PADCFGLOCK, \
|
||||
.hostown_offset = CDF_HOSTSW_OWN, \
|
||||
.is_offset = CDF_GPI_IS, \
|
||||
.ie_offset = CDF_GPI_IE, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, CDF)
|
||||
|
||||
/* Cedar Fork PCH */
|
||||
static const struct pinctrl_pin_desc cdf_pins[] = {
|
||||
|
|
|
|||
|
|
@ -694,7 +694,7 @@ static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return pctrl->soc->functions[function].name;
|
||||
return pctrl->soc->functions[function].func.name;
|
||||
}
|
||||
|
||||
static int chv_get_function_groups(struct pinctrl_dev *pctldev,
|
||||
|
|
@ -704,8 +704,8 @@ static int chv_get_function_groups(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*groups = pctrl->soc->functions[function].groups;
|
||||
*ngroups = pctrl->soc->functions[function].ngroups;
|
||||
*groups = pctrl->soc->functions[function].func.groups;
|
||||
*ngroups = pctrl->soc->functions[function].func.ngroups;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -28,18 +28,7 @@
|
|||
}
|
||||
|
||||
#define DNV_COMMUNITY(b, s, e, g) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = DNV_PAD_OWN, \
|
||||
.padcfglock_offset = DNV_PADCFGLOCK, \
|
||||
.hostown_offset = DNV_HOSTSW_OWN, \
|
||||
.is_offset = DNV_GPI_IS, \
|
||||
.ie_offset = DNV_GPI_IE, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, DNV)
|
||||
|
||||
/* Denverton */
|
||||
static const struct pinctrl_pin_desc dnv_pins[] = {
|
||||
|
|
|
|||
|
|
@ -27,18 +27,8 @@
|
|||
.size = ((e) - (s) + 1), \
|
||||
}
|
||||
|
||||
#define EHL_COMMUNITY(s, e, g) \
|
||||
{ \
|
||||
.padown_offset = EHL_PAD_OWN, \
|
||||
.padcfglock_offset = EHL_PADCFGLOCK, \
|
||||
.hostown_offset = EHL_HOSTSW_OWN, \
|
||||
.is_offset = EHL_GPI_IS, \
|
||||
.ie_offset = EHL_GPI_IE, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
#define EHL_COMMUNITY(b, s, e, g) \
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, EHL)
|
||||
|
||||
/* Elkhart Lake */
|
||||
static const struct pinctrl_pin_desc ehl_community0_pins[] = {
|
||||
|
|
@ -121,7 +111,7 @@ static const struct intel_padgroup ehl_community0_gpps[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community ehl_community0[] = {
|
||||
EHL_COMMUNITY(0, 66, ehl_community0_gpps),
|
||||
EHL_COMMUNITY(0, 0, 66, ehl_community0_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data ehl_community0_soc_data = {
|
||||
|
|
@ -262,7 +252,7 @@ static const struct intel_padgroup ehl_community1_gpps[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community ehl_community1[] = {
|
||||
EHL_COMMUNITY(0, 112, ehl_community1_gpps),
|
||||
EHL_COMMUNITY(0, 0, 112, ehl_community1_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data ehl_community1_soc_data = {
|
||||
|
|
@ -335,7 +325,7 @@ static const struct intel_padgroup ehl_community3_gpps[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community ehl_community3[] = {
|
||||
EHL_COMMUNITY(0, 46, ehl_community3_gpps),
|
||||
EHL_COMMUNITY(0, 0, 46, ehl_community3_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data ehl_community3_soc_data = {
|
||||
|
|
@ -441,7 +431,7 @@ static const struct intel_padgroup ehl_community4_gpps[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community ehl_community4[] = {
|
||||
EHL_COMMUNITY(0, 79, ehl_community4_gpps),
|
||||
EHL_COMMUNITY(0, 0, 79, ehl_community4_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data ehl_community4_soc_data = {
|
||||
|
|
@ -469,7 +459,7 @@ static const struct intel_padgroup ehl_community5_gpps[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community ehl_community5[] = {
|
||||
EHL_COMMUNITY(0, 7, ehl_community5_gpps),
|
||||
EHL_COMMUNITY(0, 0, 7, ehl_community5_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data ehl_community5_soc_data = {
|
||||
|
|
|
|||
|
|
@ -28,18 +28,7 @@
|
|||
}
|
||||
|
||||
#define EBG_COMMUNITY(b, s, e, g) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = EBG_PAD_OWN, \
|
||||
.padcfglock_offset = EBG_PADCFGLOCK, \
|
||||
.hostown_offset = EBG_HOSTSW_OWN, \
|
||||
.is_offset = EBG_GPI_IS, \
|
||||
.ie_offset = EBG_GPI_IE, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, EBG)
|
||||
|
||||
/* Emmitsburg */
|
||||
static const struct pinctrl_pin_desc ebg_pins[] = {
|
||||
|
|
|
|||
|
|
@ -20,17 +20,8 @@
|
|||
#define GLK_GPI_IS 0x100
|
||||
#define GLK_GPI_IE 0x110
|
||||
|
||||
#define GLK_COMMUNITY(s, e) \
|
||||
{ \
|
||||
.padown_offset = GLK_PAD_OWN, \
|
||||
.padcfglock_offset = GLK_PADCFGLOCK, \
|
||||
.hostown_offset = GLK_HOSTSW_OWN, \
|
||||
.is_offset = GLK_GPI_IS, \
|
||||
.ie_offset = GLK_GPI_IE, \
|
||||
.gpp_size = 32, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
}
|
||||
#define GLK_COMMUNITY(b, s, e) \
|
||||
INTEL_COMMUNITY_SIZE(b, s, e, 32, 4, GLK)
|
||||
|
||||
/* GLK */
|
||||
static const struct pinctrl_pin_desc glk_northwest_pins[] = {
|
||||
|
|
@ -173,7 +164,7 @@ static const struct intel_function glk_northwest_functions[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community glk_northwest_communities[] = {
|
||||
GLK_COMMUNITY(0, 79),
|
||||
GLK_COMMUNITY(0, 0, 79),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data glk_northwest_soc_data = {
|
||||
|
|
@ -306,7 +297,7 @@ static const struct intel_function glk_north_functions[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community glk_north_communities[] = {
|
||||
GLK_COMMUNITY(0, 79),
|
||||
GLK_COMMUNITY(0, 0, 79),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data glk_north_soc_data = {
|
||||
|
|
@ -345,7 +336,7 @@ static const struct pinctrl_pin_desc glk_audio_pins[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community glk_audio_communities[] = {
|
||||
GLK_COMMUNITY(0, 19),
|
||||
GLK_COMMUNITY(0, 0, 19),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data glk_audio_soc_data = {
|
||||
|
|
@ -427,7 +418,7 @@ static const struct intel_function glk_scc_functions[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community glk_scc_communities[] = {
|
||||
GLK_COMMUNITY(0, 34),
|
||||
GLK_COMMUNITY(0, 0, 34),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data glk_scc_soc_data = {
|
||||
|
|
|
|||
|
|
@ -15,12 +15,17 @@
|
|||
|
||||
#include "pinctrl-intel.h"
|
||||
|
||||
#define ICL_PAD_OWN 0x020
|
||||
#define ICL_PADCFGLOCK 0x080
|
||||
#define ICL_HOSTSW_OWN 0x0b0
|
||||
#define ICL_GPI_IS 0x100
|
||||
#define ICL_LP_GPI_IE 0x110
|
||||
#define ICL_N_GPI_IE 0x120
|
||||
#define ICL_LP_PAD_OWN 0x020
|
||||
#define ICL_LP_PADCFGLOCK 0x080
|
||||
#define ICL_LP_HOSTSW_OWN 0x0b0
|
||||
#define ICL_LP_GPI_IS 0x100
|
||||
#define ICL_LP_GPI_IE 0x110
|
||||
|
||||
#define ICL_N_PAD_OWN 0x020
|
||||
#define ICL_N_PADCFGLOCK 0x080
|
||||
#define ICL_N_HOSTSW_OWN 0x0b0
|
||||
#define ICL_N_GPI_IS 0x100
|
||||
#define ICL_N_GPI_IE 0x120
|
||||
|
||||
#define ICL_GPP(r, s, e, g) \
|
||||
{ \
|
||||
|
|
@ -30,25 +35,11 @@
|
|||
.gpio_base = (g), \
|
||||
}
|
||||
|
||||
#define ICL_COMMUNITY(b, s, e, g, v) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = ICL_PAD_OWN, \
|
||||
.padcfglock_offset = ICL_PADCFGLOCK, \
|
||||
.hostown_offset = ICL_HOSTSW_OWN, \
|
||||
.is_offset = ICL_GPI_IS, \
|
||||
.ie_offset = ICL_##v##_GPI_IE, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
|
||||
#define ICL_LP_COMMUNITY(b, s, e, g) \
|
||||
ICL_COMMUNITY(b, s, e, g, LP)
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_LP)
|
||||
|
||||
#define ICL_N_COMMUNITY(b, s, e, g) \
|
||||
ICL_COMMUNITY(b, s, e, g, N)
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_N)
|
||||
|
||||
/* Ice Lake-LP */
|
||||
static const struct pinctrl_pin_desc icllp_pins[] = {
|
||||
|
|
|
|||
|
|
@ -81,13 +81,16 @@
|
|||
#define PADCFG1_TERM_MASK GENMASK(12, 10)
|
||||
#define PADCFG1_TERM_20K BIT(2)
|
||||
#define PADCFG1_TERM_5K BIT(1)
|
||||
#define PADCFG1_TERM_4K (BIT(2) | BIT(1))
|
||||
#define PADCFG1_TERM_1K BIT(0)
|
||||
#define PADCFG1_TERM_952 (BIT(2) | BIT(0))
|
||||
#define PADCFG1_TERM_833 (BIT(1) | BIT(0))
|
||||
#define PADCFG1_TERM_800 (BIT(2) | BIT(1) | BIT(0))
|
||||
|
||||
#define PADCFG2 0x008
|
||||
#define PADCFG2_DEBEN BIT(0)
|
||||
#define PADCFG2_DEBOUNCE_SHIFT 1
|
||||
#define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
|
||||
#define PADCFG2_DEBEN BIT(0)
|
||||
|
||||
#define DEBOUNCE_PERIOD_NSEC 31250
|
||||
|
||||
|
|
@ -369,7 +372,7 @@ static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return pctrl->soc->functions[function].name;
|
||||
return pctrl->soc->functions[function].func.name;
|
||||
}
|
||||
|
||||
static int intel_get_function_groups(struct pinctrl_dev *pctldev,
|
||||
|
|
@ -379,8 +382,8 @@ static int intel_get_function_groups(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*groups = pctrl->soc->functions[function].groups;
|
||||
*ngroups = pctrl->soc->functions[function].ngroups;
|
||||
*groups = pctrl->soc->functions[function].func.groups;
|
||||
*ngroups = pctrl->soc->functions[function].func.ngroups;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -574,6 +577,9 @@ static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
|
|||
case PADCFG1_TERM_1K:
|
||||
*arg = 1000;
|
||||
break;
|
||||
case PADCFG1_TERM_4K:
|
||||
*arg = 4000;
|
||||
break;
|
||||
case PADCFG1_TERM_5K:
|
||||
*arg = 5000;
|
||||
break;
|
||||
|
|
@ -599,6 +605,9 @@ static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
|
|||
return -EINVAL;
|
||||
*arg = 1000;
|
||||
break;
|
||||
case PADCFG1_TERM_4K:
|
||||
*arg = 4000;
|
||||
break;
|
||||
case PADCFG1_TERM_5K:
|
||||
*arg = 5000;
|
||||
break;
|
||||
|
|
@ -691,21 +700,17 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
|
|||
raw_spin_lock_irqsave(&pctrl->lock, flags);
|
||||
|
||||
value = readl(padcfg1);
|
||||
value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
|
||||
|
||||
/* Set default strength value in case none is given */
|
||||
if (arg == 1)
|
||||
arg = 5000;
|
||||
|
||||
switch (param) {
|
||||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
value &= ~PADCFG1_TERM_MASK;
|
||||
|
||||
value |= PADCFG1_TERM_UP;
|
||||
|
||||
/* Set default strength value in case none is given */
|
||||
if (arg == 1)
|
||||
arg = 5000;
|
||||
|
||||
switch (arg) {
|
||||
case 20000:
|
||||
value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
|
||||
|
|
@ -713,6 +718,9 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
|
|||
case 5000:
|
||||
value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
|
||||
break;
|
||||
case 4000:
|
||||
value |= PADCFG1_TERM_4K << PADCFG1_TERM_SHIFT;
|
||||
break;
|
||||
case 1000:
|
||||
value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
|
||||
break;
|
||||
|
|
@ -721,42 +729,46 @@ static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
|
|||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
value |= PADCFG1_TERM_UP;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
switch (arg) {
|
||||
case 20000:
|
||||
value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
|
||||
break;
|
||||
case 5000:
|
||||
value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
|
||||
break;
|
||||
case 4000:
|
||||
value |= PADCFG1_TERM_4K << PADCFG1_TERM_SHIFT;
|
||||
break;
|
||||
case 1000:
|
||||
if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
|
||||
break;
|
||||
case 833:
|
||||
if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
|
||||
|
||||
/* Set default strength value in case none is given */
|
||||
if (arg == 1)
|
||||
arg = 5000;
|
||||
|
||||
switch (arg) {
|
||||
case 20000:
|
||||
value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
|
||||
break;
|
||||
case 5000:
|
||||
value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
|
||||
break;
|
||||
case 1000:
|
||||
if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
|
||||
break;
|
||||
case 833:
|
||||
if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
}
|
||||
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -1215,13 +1227,8 @@ static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
|
|||
/* Only interrupts that are enabled */
|
||||
pending &= enabled;
|
||||
|
||||
for_each_set_bit(gpp_offset, &pending, padgrp->size) {
|
||||
unsigned int irq;
|
||||
|
||||
irq = irq_find_mapping(gc->irq.domain,
|
||||
padgrp->gpio_base + gpp_offset);
|
||||
generic_handle_irq(irq);
|
||||
}
|
||||
for_each_set_bit(gpp_offset, &pending, padgrp->size)
|
||||
generic_handle_domain_irq(gc->irq.domain, padgrp->gpio_base + gpp_offset);
|
||||
|
||||
ret += pending ? 1 : 0;
|
||||
}
|
||||
|
|
@ -1399,7 +1406,7 @@ static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
|
|||
for (i = 0; i < ngpps; i++) {
|
||||
gpps[i] = community->gpps[i];
|
||||
|
||||
if (gpps[i].size > 32)
|
||||
if (gpps[i].size > INTEL_PINCTRL_MAX_GPP_SIZE)
|
||||
return -EINVAL;
|
||||
|
||||
/* Special treatment for GPIO base */
|
||||
|
|
@ -1417,7 +1424,7 @@ static int intel_pinctrl_add_padgroups_by_gpps(struct intel_pinctrl *pctrl,
|
|||
}
|
||||
|
||||
gpps[i].padown_num = padown_num;
|
||||
padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
|
||||
padown_num += DIV_ROUND_UP(gpps[i].size * 4, INTEL_PINCTRL_MAX_GPP_SIZE);
|
||||
}
|
||||
|
||||
community->gpps = gpps;
|
||||
|
|
@ -1433,7 +1440,7 @@ static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
|
|||
unsigned int padown_num = 0;
|
||||
size_t i, ngpps = DIV_ROUND_UP(npins, community->gpp_size);
|
||||
|
||||
if (community->gpp_size > 32)
|
||||
if (community->gpp_size > INTEL_PINCTRL_MAX_GPP_SIZE)
|
||||
return -EINVAL;
|
||||
|
||||
gpps = devm_kcalloc(pctrl->dev, ngpps, sizeof(*gpps), GFP_KERNEL);
|
||||
|
|
@ -1451,14 +1458,7 @@ static int intel_pinctrl_add_padgroups_by_size(struct intel_pinctrl *pctrl,
|
|||
gpps[i].gpio_base = gpps[i].base;
|
||||
gpps[i].padown_num = padown_num;
|
||||
|
||||
/*
|
||||
* In older hardware the number of padown registers per
|
||||
* group is fixed regardless of the group size.
|
||||
*/
|
||||
if (community->gpp_num_padown_regs)
|
||||
padown_num += community->gpp_num_padown_regs;
|
||||
else
|
||||
padown_num += DIV_ROUND_UP(gpps[i].size * 4, 32);
|
||||
padown_num += community->gpp_num_padown_regs;
|
||||
}
|
||||
|
||||
community->ngpps = ngpps;
|
||||
|
|
|
|||
|
|
@ -36,21 +36,19 @@ struct intel_pingroup {
|
|||
|
||||
/**
|
||||
* struct intel_function - Description about a function
|
||||
* @name: Name of the function
|
||||
* @groups: An array of groups for this function
|
||||
* @ngroups: Number of groups in @groups
|
||||
* @func: Generic data of the pin function (name and groups of pins)
|
||||
*/
|
||||
struct intel_function {
|
||||
const char *name;
|
||||
const char * const *groups;
|
||||
size_t ngroups;
|
||||
struct pinfunction func;
|
||||
};
|
||||
|
||||
#define INTEL_PINCTRL_MAX_GPP_SIZE 32
|
||||
|
||||
/**
|
||||
* struct intel_padgroup - Hardware pad group information
|
||||
* @reg_num: GPI_IS register number
|
||||
* @base: Starting pin of this group
|
||||
* @size: Size of this group (maximum is 32).
|
||||
* @size: Size of this group (maximum is %INTEL_PINCTRL_MAX_GPP_SIZE).
|
||||
* @gpio_base: Starting GPIO base of this group
|
||||
* @padown_num: PAD_OWN register number (assigned by the core driver)
|
||||
*
|
||||
|
|
@ -96,8 +94,7 @@ enum {
|
|||
* @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
|
||||
* HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL.
|
||||
* @gpp_num_padown_regs: Number of pad registers each pad group consumes at
|
||||
* minimum. Use %0 if the number of registers can be
|
||||
* determined by the size of the group.
|
||||
* minimum. Used when @gpps is %NULL.
|
||||
* @gpps: Pad groups if the controller has variable size pad groups
|
||||
* @ngpps: Number of pad groups in this community
|
||||
* @pad_map: Optional non-linear mapping of the pads
|
||||
|
|
@ -106,11 +103,13 @@ enum {
|
|||
* @regs: Community specific common registers (reserved for core driver)
|
||||
* @pad_regs: Community specific pad registers (reserved for core driver)
|
||||
*
|
||||
* In some of Intel GPIO host controllers this driver supports each pad group
|
||||
* In older Intel GPIO host controllers, this driver supports, each pad group
|
||||
* is of equal size (except the last one). In that case the driver can just
|
||||
* fill in @gpp_size field and let the core driver to handle the rest. If
|
||||
* the controller has pad groups of variable size the client driver can
|
||||
* pass custom @gpps and @ngpps instead.
|
||||
* fill in @gpp_size and @gpp_num_padown_regs fields and let the core driver
|
||||
* to handle the rest.
|
||||
*
|
||||
* In newer Intel GPIO host controllers each pad group is of variable size,
|
||||
* so the client driver can pass custom @gpps and @ngpps instead.
|
||||
*/
|
||||
struct intel_community {
|
||||
unsigned int barno;
|
||||
|
|
@ -143,6 +142,28 @@ struct intel_community {
|
|||
#define PINCTRL_FEATURE_BLINK BIT(4)
|
||||
#define PINCTRL_FEATURE_EXP BIT(5)
|
||||
|
||||
#define __INTEL_COMMUNITY(b, s, e, g, n, gs, gn, soc) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = soc ## _PAD_OWN, \
|
||||
.padcfglock_offset = soc ## _PADCFGLOCK, \
|
||||
.hostown_offset = soc ## _HOSTSW_OWN, \
|
||||
.is_offset = soc ## _GPI_IS, \
|
||||
.ie_offset = soc ## _GPI_IE, \
|
||||
.gpp_size = (gs), \
|
||||
.gpp_num_padown_regs = (gn), \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = (n), \
|
||||
}
|
||||
|
||||
#define INTEL_COMMUNITY_GPPS(b, s, e, g, soc) \
|
||||
__INTEL_COMMUNITY(b, s, e, g, ARRAY_SIZE(g), 0, 0, soc)
|
||||
|
||||
#define INTEL_COMMUNITY_SIZE(b, s, e, gs, gn, soc) \
|
||||
__INTEL_COMMUNITY(b, s, e, NULL, 0, gs, gn, soc)
|
||||
|
||||
/**
|
||||
* PIN_GROUP - Declare a pin group
|
||||
* @n: Name of the group
|
||||
|
|
@ -158,11 +179,9 @@ struct intel_community {
|
|||
.modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)), \
|
||||
}
|
||||
|
||||
#define FUNCTION(n, g) \
|
||||
{ \
|
||||
.name = (n), \
|
||||
.groups = (g), \
|
||||
.ngroups = ARRAY_SIZE((g)), \
|
||||
#define FUNCTION(n, g) \
|
||||
{ \
|
||||
.func = PINCTRL_PINFUNCTION((n), (g), ARRAY_SIZE(g)), \
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -29,18 +29,7 @@
|
|||
}
|
||||
|
||||
#define JSL_COMMUNITY(b, s, e, g) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = JSL_PAD_OWN, \
|
||||
.padcfglock_offset = JSL_PADCFGLOCK, \
|
||||
.hostown_offset = JSL_HOSTSW_OWN, \
|
||||
.is_offset = JSL_GPI_IS, \
|
||||
.ie_offset = JSL_GPI_IE, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, JSL)
|
||||
|
||||
/* Jasper Lake */
|
||||
static const struct pinctrl_pin_desc jsl_pins[] = {
|
||||
|
|
|
|||
|
|
@ -29,18 +29,7 @@
|
|||
}
|
||||
|
||||
#define LKF_COMMUNITY(b, s, e, g) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = LKF_PAD_OWN, \
|
||||
.padcfglock_offset = LKF_PADCFGLOCK, \
|
||||
.hostown_offset = LKF_HOSTSW_OWN, \
|
||||
.is_offset = LKF_GPI_IS, \
|
||||
.ie_offset = LKF_GPI_IE, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, LKF)
|
||||
|
||||
/* Lakefield */
|
||||
static const struct pinctrl_pin_desc lkf_pins[] = {
|
||||
|
|
|
|||
|
|
@ -21,17 +21,7 @@
|
|||
#define LBG_GPI_IE 0x110
|
||||
|
||||
#define LBG_COMMUNITY(b, s, e) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = LBG_PAD_OWN, \
|
||||
.padcfglock_offset = LBG_PADCFGLOCK, \
|
||||
.hostown_offset = LBG_HOSTSW_OWN, \
|
||||
.is_offset = LBG_GPI_IS, \
|
||||
.ie_offset = LBG_GPI_IE, \
|
||||
.gpp_size = 24, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
}
|
||||
INTEL_COMMUNITY_SIZE(b, s, e, 24, 3, LBG)
|
||||
|
||||
/* Lewisburg */
|
||||
static const struct pinctrl_pin_desc lbg_pins[] = {
|
||||
|
|
|
|||
|
|
@ -341,18 +341,18 @@ static const char *lp_get_function_name(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return lg->soc->functions[selector].name;
|
||||
return lg->soc->functions[selector].func.name;
|
||||
}
|
||||
|
||||
static int lp_get_function_groups(struct pinctrl_dev *pctldev,
|
||||
unsigned int selector,
|
||||
const char * const **groups,
|
||||
unsigned int *num_groups)
|
||||
unsigned int *ngroups)
|
||||
{
|
||||
struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*groups = lg->soc->functions[selector].groups;
|
||||
*num_groups = lg->soc->functions[selector].ngroups;
|
||||
*groups = lg->soc->functions[selector].func.groups;
|
||||
*ngroups = lg->soc->functions[selector].func.ngroups;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -576,7 +576,7 @@ static const char *mrfld_get_function_name(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return mp->functions[function].name;
|
||||
return mp->functions[function].func.name;
|
||||
}
|
||||
|
||||
static int mrfld_get_function_groups(struct pinctrl_dev *pctldev,
|
||||
|
|
@ -586,8 +586,8 @@ static int mrfld_get_function_groups(struct pinctrl_dev *pctldev,
|
|||
{
|
||||
struct mrfld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*groups = mp->functions[function].groups;
|
||||
*ngroups = mp->functions[function].ngroups;
|
||||
*groups = mp->functions[function].func.groups;
|
||||
*ngroups = mp->functions[function].func.ngroups;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -14,11 +14,11 @@
|
|||
|
||||
#include "pinctrl-intel.h"
|
||||
|
||||
#define MTL_PAD_OWN 0x0b0
|
||||
#define MTL_PADCFGLOCK 0x110
|
||||
#define MTL_HOSTSW_OWN 0x140
|
||||
#define MTL_GPI_IS 0x200
|
||||
#define MTL_GPI_IE 0x210
|
||||
#define MTL_P_PAD_OWN 0x0b0
|
||||
#define MTL_P_PADCFGLOCK 0x110
|
||||
#define MTL_P_HOSTSW_OWN 0x140
|
||||
#define MTL_P_GPI_IS 0x200
|
||||
#define MTL_P_GPI_IE 0x210
|
||||
|
||||
#define MTL_GPP(r, s, e, g) \
|
||||
{ \
|
||||
|
|
@ -29,18 +29,7 @@
|
|||
}
|
||||
|
||||
#define MTL_COMMUNITY(b, s, e, g) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = MTL_PAD_OWN, \
|
||||
.padcfglock_offset = MTL_PADCFGLOCK, \
|
||||
.hostown_offset = MTL_HOSTSW_OWN, \
|
||||
.is_offset = MTL_GPI_IS, \
|
||||
.ie_offset = MTL_GPI_IE, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_P)
|
||||
|
||||
/* Meteor Lake-P */
|
||||
static const struct pinctrl_pin_desc mtlp_pins[] = {
|
||||
|
|
|
|||
|
|
@ -530,7 +530,7 @@ static const char *mofld_get_function_name(struct pinctrl_dev *pctldev, unsigned
|
|||
{
|
||||
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
return mp->functions[function].name;
|
||||
return mp->functions[function].func.name;
|
||||
}
|
||||
|
||||
static int mofld_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
|
||||
|
|
@ -538,8 +538,8 @@ static int mofld_get_function_groups(struct pinctrl_dev *pctldev, unsigned int f
|
|||
{
|
||||
struct mofld_pinctrl *mp = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
*groups = mp->functions[function].groups;
|
||||
*ngroups = mp->functions[function].ngroups;
|
||||
*groups = mp->functions[function].func.groups;
|
||||
*ngroups = mp->functions[function].func.ngroups;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -15,31 +15,17 @@
|
|||
|
||||
#include "pinctrl-intel.h"
|
||||
|
||||
#define SPT_PAD_OWN 0x020
|
||||
#define SPT_H_PAD_OWN 0x020
|
||||
#define SPT_H_PADCFGLOCK 0x090
|
||||
#define SPT_H_HOSTSW_OWN 0x0d0
|
||||
#define SPT_H_GPI_IS 0x100
|
||||
#define SPT_H_GPI_IE 0x120
|
||||
|
||||
#define SPT_LP_PAD_OWN 0x020
|
||||
#define SPT_LP_PADCFGLOCK 0x0a0
|
||||
#define SPT_HOSTSW_OWN 0x0d0
|
||||
#define SPT_GPI_IS 0x100
|
||||
#define SPT_GPI_IE 0x120
|
||||
|
||||
#define SPT_COMMUNITY(b, s, e, g, n, v, gs, gn) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = SPT_PAD_OWN, \
|
||||
.padcfglock_offset = SPT_##v##_PADCFGLOCK, \
|
||||
.hostown_offset = SPT_HOSTSW_OWN, \
|
||||
.is_offset = SPT_GPI_IS, \
|
||||
.ie_offset = SPT_GPI_IE, \
|
||||
.gpp_size = (gs), \
|
||||
.gpp_num_padown_regs = (gn), \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = (n), \
|
||||
}
|
||||
|
||||
#define SPT_LP_COMMUNITY(b, s, e) \
|
||||
SPT_COMMUNITY(b, s, e, NULL, 0, LP, 24, 4)
|
||||
#define SPT_LP_HOSTSW_OWN 0x0d0
|
||||
#define SPT_LP_GPI_IS 0x100
|
||||
#define SPT_LP_GPI_IE 0x120
|
||||
|
||||
#define SPT_H_GPP(r, s, e, g) \
|
||||
{ \
|
||||
|
|
@ -50,7 +36,10 @@
|
|||
}
|
||||
|
||||
#define SPT_H_COMMUNITY(b, s, e, g) \
|
||||
SPT_COMMUNITY(b, s, e, g, ARRAY_SIZE(g), H, 0, 0)
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, SPT_H)
|
||||
|
||||
#define SPT_LP_COMMUNITY(b, s, e) \
|
||||
INTEL_COMMUNITY_SIZE(b, s, e, 24, 4, SPT_LP)
|
||||
|
||||
/* Sunrisepoint-LP */
|
||||
static const struct pinctrl_pin_desc sptlp_pins[] = {
|
||||
|
|
|
|||
|
|
@ -15,13 +15,17 @@
|
|||
|
||||
#include "pinctrl-intel.h"
|
||||
|
||||
#define TGL_PAD_OWN 0x020
|
||||
#define TGL_LP_PAD_OWN 0x020
|
||||
#define TGL_LP_PADCFGLOCK 0x080
|
||||
#define TGL_H_PADCFGLOCK 0x090
|
||||
#define TGL_LP_HOSTSW_OWN 0x0b0
|
||||
#define TGL_LP_GPI_IS 0x100
|
||||
#define TGL_LP_GPI_IE 0x120
|
||||
|
||||
#define TGL_H_PAD_OWN 0x020
|
||||
#define TGL_H_PADCFGLOCK 0x090
|
||||
#define TGL_H_HOSTSW_OWN 0x0c0
|
||||
#define TGL_GPI_IS 0x100
|
||||
#define TGL_GPI_IE 0x120
|
||||
#define TGL_H_GPI_IS 0x100
|
||||
#define TGL_H_GPI_IE 0x120
|
||||
|
||||
#define TGL_GPP(r, s, e, g) \
|
||||
{ \
|
||||
|
|
@ -31,25 +35,11 @@
|
|||
.gpio_base = (g), \
|
||||
}
|
||||
|
||||
#define TGL_COMMUNITY(b, s, e, g, v) \
|
||||
{ \
|
||||
.barno = (b), \
|
||||
.padown_offset = TGL_PAD_OWN, \
|
||||
.padcfglock_offset = TGL_##v##_PADCFGLOCK, \
|
||||
.hostown_offset = TGL_##v##_HOSTSW_OWN, \
|
||||
.is_offset = TGL_GPI_IS, \
|
||||
.ie_offset = TGL_GPI_IE, \
|
||||
.pin_base = (s), \
|
||||
.npins = ((e) - (s) + 1), \
|
||||
.gpps = (g), \
|
||||
.ngpps = ARRAY_SIZE(g), \
|
||||
}
|
||||
|
||||
#define TGL_LP_COMMUNITY(b, s, e, g) \
|
||||
TGL_COMMUNITY(b, s, e, g, LP)
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_LP)
|
||||
|
||||
#define TGL_H_COMMUNITY(b, s, e, g) \
|
||||
TGL_COMMUNITY(b, s, e, g, H)
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_H)
|
||||
|
||||
/* Tiger Lake-LP */
|
||||
static const struct pinctrl_pin_desc tgllp_pins[] = {
|
||||
|
|
|
|||
|
|
@ -127,6 +127,11 @@ config PINCTRL_MT7622
|
|||
default ARM64 && ARCH_MEDIATEK
|
||||
select PINCTRL_MTK_MOORE
|
||||
|
||||
config PINCTRL_MT7981
|
||||
bool "Mediatek MT7981 pin control"
|
||||
depends on OF
|
||||
select PINCTRL_MTK_MOORE
|
||||
|
||||
config PINCTRL_MT7986
|
||||
bool "Mediatek MT7986 pin control"
|
||||
depends on OF
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o
|
|||
obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
|
||||
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
|
||||
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
|
||||
obj-$(CONFIG_PINCTRL_MT7981) += pinctrl-mt7981.o
|
||||
obj-$(CONFIG_PINCTRL_MT7986) += pinctrl-mt7986.o
|
||||
obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o
|
||||
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
|
||||
|
|
|
|||
|
|
@ -574,7 +574,6 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
|
|||
chip->set_config = mtk_gpio_set_config;
|
||||
chip->base = -1;
|
||||
chip->ngpio = hw->soc->npins;
|
||||
chip->of_gpio_n_cells = 2;
|
||||
|
||||
ret = gpiochip_add_data(chip, hw);
|
||||
if (ret < 0)
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -906,7 +906,6 @@ static const struct gpio_chip mtk_gpio_chip = {
|
|||
.set = mtk_gpio_set,
|
||||
.to_irq = mtk_gpio_to_irq,
|
||||
.set_config = mtk_gpio_set_config,
|
||||
.of_gpio_n_cells = 2,
|
||||
};
|
||||
|
||||
static int mtk_eint_suspend(struct device *device)
|
||||
|
|
|
|||
|
|
@ -640,7 +640,7 @@ static int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int
|
|||
ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
|
||||
unsigned int gpio, char *buf, unsigned int buf_len)
|
||||
{
|
||||
int pinmux, pullup, pullen, len = 0, r1 = -1, r0 = -1, rsel = -1;
|
||||
int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1, rsel = -1;
|
||||
const struct mtk_pin_desc *desc;
|
||||
u32 try_all_type = 0;
|
||||
|
||||
|
|
@ -717,7 +717,7 @@ static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
|
|||
unsigned int gpio)
|
||||
{
|
||||
struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
|
||||
char buf[PIN_DBG_BUF_SZ];
|
||||
char buf[PIN_DBG_BUF_SZ] = { 0 };
|
||||
|
||||
(void)mtk_pctrl_show_one_pin(hw, gpio, buf, PIN_DBG_BUF_SZ);
|
||||
|
||||
|
|
@ -987,7 +987,6 @@ static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
|
|||
chip->set_config = mtk_gpio_set_config;
|
||||
chip->base = -1;
|
||||
chip->ngpio = hw->soc->npins;
|
||||
chip->of_gpio_n_cells = 2;
|
||||
|
||||
ret = gpiochip_add_data(chip, hw);
|
||||
if (ret < 0)
|
||||
|
|
|
|||
|
|
@ -446,8 +446,6 @@ out:
|
|||
return ret;
|
||||
}
|
||||
|
||||
#include <linux/seq_file.h>
|
||||
|
||||
static void abx500_gpio_dbg_show_one(struct seq_file *s,
|
||||
struct pinctrl_dev *pctldev,
|
||||
struct gpio_chip *chip,
|
||||
|
|
|
|||
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