gpio: langwell: add Intel Merrifield support
This patch implements a better way to handle multiple SoC's and adds Intel Merrifield support to gpio-langwell. It was based on previous work from Ning Li <ning.li@intel.com> Signed-off-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: Fei Yang <fei.yang@intel.com> Signed-off-by: Ning Li <ning.li@intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
David Cohen
Linus Walleij
Родитель
70b5341138
Коммит
d56d6b3d7d
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@ -37,6 +37,9 @@
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#include <linux/pm_runtime.h>
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#include <linux/irqdomain.h>
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#define LNW_IRQ_TYPE_EDGE (1 << 0)
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#define LNW_IRQ_TYPE_LEVEL (1 << 1)
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/*
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* Langwell chip has 64 pins and thus there are 2 32bit registers to control
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* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
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@ -62,6 +65,16 @@ enum GPIO_REG {
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GAFR, /* alt function */
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};
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/* langwell gpio driver data */
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struct lnw_gpio_ddata {
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u16 ngpio; /* number of gpio pins */
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u32 gplr_offset; /* offset of first GPLR register from base */
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u32 flis_base; /* base address of FLIS registers */
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u32 flis_len; /* length of FLIS registers */
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u32 (*get_flis_offset)(int gpio);
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u32 chip_irq_type; /* chip interrupt type */
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};
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struct lnw_gpio {
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struct gpio_chip chip;
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void __iomem *reg_base;
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@ -227,13 +240,71 @@ static struct irq_chip lnw_irqchip = {
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.irq_set_type = lnw_irq_type,
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};
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static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb), .driver_data = 96 },
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7), .driver_data = 96 },
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{ 0, }
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static const struct lnw_gpio_ddata gpio_lincroft = {
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.ngpio = 64,
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};
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static const struct lnw_gpio_ddata gpio_penwell_aon = {
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.ngpio = 96,
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.chip_irq_type = LNW_IRQ_TYPE_EDGE,
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};
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static const struct lnw_gpio_ddata gpio_penwell_core = {
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.ngpio = 96,
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.chip_irq_type = LNW_IRQ_TYPE_EDGE,
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};
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static const struct lnw_gpio_ddata gpio_cloverview_aon = {
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.ngpio = 96,
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.chip_irq_type = LNW_IRQ_TYPE_EDGE | LNW_IRQ_TYPE_LEVEL,
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};
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static const struct lnw_gpio_ddata gpio_cloverview_core = {
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.ngpio = 96,
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.chip_irq_type = LNW_IRQ_TYPE_EDGE,
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};
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static const struct lnw_gpio_ddata gpio_tangier = {
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.ngpio = 192,
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.gplr_offset = 4,
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.flis_base = 0xff0c0000,
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.flis_len = 0x8000,
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.get_flis_offset = NULL,
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.chip_irq_type = LNW_IRQ_TYPE_EDGE,
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};
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static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = {
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{
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/* Lincroft */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
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.driver_data = (kernel_ulong_t)&gpio_lincroft,
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},
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{
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/* Penwell AON */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
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.driver_data = (kernel_ulong_t)&gpio_penwell_aon,
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},
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{
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/* Penwell Core */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
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.driver_data = (kernel_ulong_t)&gpio_penwell_core,
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},
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{
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/* Cloverview Aon */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
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.driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
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},
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{
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/* Cloverview Core */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
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.driver_data = (kernel_ulong_t)&gpio_cloverview_core,
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},
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{
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/* Tangier */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1199),
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.driver_data = (kernel_ulong_t)&gpio_tangier,
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},
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{ 0 }
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};
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MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
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@ -316,7 +387,7 @@ static int lnw_gpio_probe(struct pci_dev *pdev,
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u32 gpio_base;
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u32 irq_base;
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int retval;
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int ngpio = id->driver_data;
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struct lnw_gpio_ddata *ddata = (struct lnw_gpio_ddata *)id->driver_data;
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retval = pcim_enable_device(pdev);
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if (retval)
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@ -351,14 +422,14 @@ static int lnw_gpio_probe(struct pci_dev *pdev,
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lnw->chip.set = lnw_gpio_set;
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lnw->chip.to_irq = lnw_gpio_to_irq;
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lnw->chip.base = gpio_base;
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lnw->chip.ngpio = ngpio;
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lnw->chip.ngpio = ddata->ngpio;
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lnw->chip.can_sleep = 0;
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lnw->pdev = pdev;
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spin_lock_init(&lnw->lock);
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lnw->domain = irq_domain_add_simple(pdev->dev.of_node, ngpio, irq_base,
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&lnw_gpio_irq_ops, lnw);
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lnw->domain = irq_domain_add_simple(pdev->dev.of_node, ddata->ngpio,
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irq_base, &lnw_gpio_irq_ops, lnw);
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if (!lnw->domain)
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return -ENOMEM;
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