clk: zynq: trivial warning fix
Fix the below warning WARNING: Missing a blank line after declarations + int enable = !!(fclk_enable & BIT(i - fclk0)); + zynq_clk_register_fclk(i, clk_output_name[i], Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Link: https://lore.kernel.org/r/20220222130903.17235-2-shubhrajyoti.datta@xilinx.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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@ -349,6 +349,7 @@ static void __init zynq_clk_setup(struct device_node *np)
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/* Peripheral clocks */
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for (i = fclk0; i <= fclk3; i++) {
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int enable = !!(fclk_enable & BIT(i - fclk0));
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zynq_clk_register_fclk(i, clk_output_name[i],
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SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
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periph_parents, enable);
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