irqchip/dw-apb-ictl: Refactor priot to introducing hierarchical irq domains
Add the required abstractions that will help introducing hierarchical domain support to the dw-apb-ictl driver. No functional change. Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> [maz: commit message, some cleanups] Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Haoyu Lv <lvhaoyu@huawei.com> Link: https://lore.kernel.org/r/20200924071754.4509-3-thunder.leizhen@huawei.com
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d59f7d1598
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@ -26,7 +26,7 @@
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#define APB_INT_FINALSTATUS_H 0x34
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#define APB_INT_FINALSTATUS_H 0x34
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#define APB_INT_BASE_OFFSET 0x04
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#define APB_INT_BASE_OFFSET 0x04
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static void dw_apb_ictl_handler(struct irq_desc *desc)
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static void dw_apb_ictl_handle_irq_cascaded(struct irq_desc *desc)
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{
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{
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struct irq_domain *d = irq_desc_get_handler_data(desc);
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struct irq_domain *d = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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@ -43,7 +43,7 @@ static void dw_apb_ictl_handler(struct irq_desc *desc)
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u32 virq = irq_find_mapping(d, gc->irq_base + hwirq);
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u32 virq = irq_find_mapping(d, gc->irq_base + hwirq);
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generic_handle_irq(virq);
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generic_handle_irq(virq);
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stat &= ~(1 << hwirq);
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stat &= ~BIT(hwirq);
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}
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}
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}
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}
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@ -68,17 +68,20 @@ static void dw_apb_ictl_resume(struct irq_data *d)
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static int __init dw_apb_ictl_init(struct device_node *np,
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static int __init dw_apb_ictl_init(struct device_node *np,
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struct device_node *parent)
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struct device_node *parent)
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{
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{
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const struct irq_domain_ops *domain_ops;
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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struct resource r;
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struct resource r;
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struct irq_domain *domain;
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struct irq_domain *domain;
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struct irq_chip_generic *gc;
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struct irq_chip_generic *gc;
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void __iomem *iobase;
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void __iomem *iobase;
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int ret, nrirqs, irq, i;
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int ret, nrirqs, parent_irq, i;
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u32 reg;
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u32 reg;
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domain_ops = &irq_generic_chip_ops;
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/* Map the parent interrupt for the chained handler */
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/* Map the parent interrupt for the chained handler */
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irq = irq_of_parse_and_map(np, 0);
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parent_irq = irq_of_parse_and_map(np, 0);
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if (irq <= 0) {
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if (parent_irq <= 0) {
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pr_err("%pOF: unable to parse irq\n", np);
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pr_err("%pOF: unable to parse irq\n", np);
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return -EINVAL;
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return -EINVAL;
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}
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}
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@ -120,8 +123,7 @@ static int __init dw_apb_ictl_init(struct device_node *np,
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else
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else
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nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L));
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nrirqs = fls(readl_relaxed(iobase + APB_INT_ENABLE_L));
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domain = irq_domain_add_linear(np, nrirqs,
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domain = irq_domain_add_linear(np, nrirqs, domain_ops, NULL);
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&irq_generic_chip_ops, NULL);
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if (!domain) {
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if (!domain) {
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pr_err("%pOF: unable to add irq domain\n", np);
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pr_err("%pOF: unable to add irq domain\n", np);
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ret = -ENOMEM;
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ret = -ENOMEM;
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@ -146,7 +148,8 @@ static int __init dw_apb_ictl_init(struct device_node *np,
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gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume;
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gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume;
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}
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}
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irq_set_chained_handler_and_data(irq, dw_apb_ictl_handler, domain);
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irq_set_chained_handler_and_data(parent_irq,
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dw_apb_ictl_handle_irq_cascaded, domain);
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return 0;
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return 0;
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