Renesas ARM DT updates for v5.15 (take two)
- Pin control, ADC, and CANFD support for the RZ/G2L SoC, - Add interrupt-names properties to the Renesas RZ/A and RZ/G2L I2C Bus Interface. -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQQ9qaHoIs/1I4cXmEiKwlD9ZEnxcAUCYRZA2gAKCRCKwlD9ZEnx cP+wAP48/ypbNOcvVxg1l7HuR0R+k3OtpSSUNmUBJhOAIYqQ2wD/Ta8Oq5jn5kLX c9+OIXtlRNkHiALWVPPkzZDXW9d+5AM= =XzWX -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAmEaz9wACgkQmmx57+YA GNllmxAAmYFQ71HJlJ04t42aZrcr30ccoCHtbTHzbVN26dGCTxYeyk2YmtCENC+Z dcMTAi+hnyFNgMebzd3Ic9C9tOPkkrAqkh/NE5ULIHOeqSrFMPltvfWecjKi6J0S v4AgpOQD2H5CxqDHHSkC4cU6EHMfDpetkdNQ9XM41n+l3EWkA407J7h9RiWsuAJL Wui8HnCqvOL0YYUSAsCVBo7yVyV296NIIeUWJ9RBztc9zKH3CEAc2y6Kbgt+QUqF VqbFF0FlnJZYxOs6cdeWVeSux9FkQQm/3x7AOb+VLLFTui2aCf4lXPpniUtarevs +6M/ZkBumWh3T7rc2T1Rybcv8b81MFzxJwZrcEWXN+BtoKYqfzCIQaBNCExrVGmp 3/ovQet2dAIBNfeW0J7vCVG+RdWKCKSUn+bpxJtWiwzfpKRwcPApl0uZAhDgQJND 5OO42lIEcidDwpgou46/YE5bD3/ZGCYN5qODxZPt2q0Xhy5kCf4cWmM7zU75TyeQ uDcxsKbBMIFo6Xw0Y2h1ywKnF+VqRyGb4FgkoLxAD5nWClTDAxxqUvIW/d89iqLc 2jU1qJi/xqqJTXd5KlUnO7OMyBHr0DqEBEwbRejoH/WzozeCrcFQEyLev9r0iLEq Xy/YKTjvcQP2vDh/WZ6R0/toHk6pzdPRfBeP4+ncncY7XI+xVvw= =91R9 -----END PGP SIGNATURE----- Merge tag 'renesas-arm-dt-for-v5.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt Renesas ARM DT updates for v5.15 (take two) - Pin control, ADC, and CANFD support for the RZ/G2L SoC, - Add interrupt-names properties to the Renesas RZ/A and RZ/G2L I2C Bus Interface. * tag 'renesas-arm-dt-for-v5.15-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: dt-bindings: i2c: renesas,riic: Make interrupt-names required arm64: dts: renesas: r9a07g044: Add I2C interrupt-names ARM: dts: rza: Add I2C interrupt-names dt-bindings: i2c: renesas,riic: Add interrupt-names arm64: dts: renesas: r9a07g044: Add CANFD node arm64: dts: renesas: r9a07g044: Add ADC node arm64: dts: renesas: r9a07g044: Add pinctrl node dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock Link: https://lore.kernel.org/r/cover.1628849623.git.geert+renesas@glider.be Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Коммит
d5aa024586
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@ -27,14 +27,25 @@ properties:
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interrupts:
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items:
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- description: Transmit End Interrupt (TEI)
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- description: Receive Data Full Interrupt (RI)
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- description: Transmit Data Empty Interrupt (TI)
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- description: Stop Condition Detection Interrupt (SPI)
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- description: Start Condition Detection Interrupt (STI)
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- description: NACK Reception Interrupt (NAKI)
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- description: Arbitration-Lost Interrupt (ALI)
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- description: Timeout Interrupt (TMOI)
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- description: Transmit End Interrupt
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- description: Receive Data Full Interrupt
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- description: Transmit Data Empty Interrupt
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- description: Stop Condition Detection Interrupt
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- description: Start Condition Detection Interrupt
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- description: NACK Reception Interrupt
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- description: Arbitration-Lost Interrupt
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- description: Timeout Interrupt
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interrupt-names:
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items:
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- const: tei
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- const: ri
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- const: ti
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- const: spi
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- const: sti
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- const: naki
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- const: ali
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- const: tmoi
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clock-frequency:
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description:
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@ -51,6 +62,7 @@ required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- clock-frequency
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- power-domains
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@ -85,6 +97,8 @@ examples:
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tei", "ri", "ti", "spi", "sti", "naki", "ali",
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"tmoi";
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clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
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clock-frequency = <100000>;
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power-domains = <&cpg_clocks>;
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@ -608,6 +608,8 @@
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<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tei", "ri", "ti", "spi", "sti",
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"naki", "ali", "tmoi";
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clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
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clock-frequency = <100000>;
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power-domains = <&cpg_clocks>;
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@ -627,6 +629,8 @@
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<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tei", "ri", "ti", "spi", "sti",
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"naki", "ali", "tmoi";
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clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
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clock-frequency = <100000>;
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power-domains = <&cpg_clocks>;
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@ -646,6 +650,8 @@
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<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tei", "ri", "ti", "spi", "sti",
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"naki", "ali", "tmoi";
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clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
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clock-frequency = <100000>;
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power-domains = <&cpg_clocks>;
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@ -665,6 +671,8 @@
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<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tei", "ri", "ti", "spi", "sti",
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"naki", "ali", "tmoi";
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clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
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clock-frequency = <100000>;
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power-domains = <&cpg_clocks>;
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@ -236,6 +236,8 @@
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<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tei", "ri", "ti", "spi", "sti",
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"naki", "ali", "tmoi";
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clocks = <&cpg CPG_MOD 87>;
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power-domains = <&cpg>;
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clock-frequency = <100000>;
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@ -255,6 +257,8 @@
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tei", "ri", "ti", "spi", "sti",
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"naki", "ali", "tmoi";
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clocks = <&cpg CPG_MOD 86>;
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power-domains = <&cpg>;
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clock-frequency = <100000>;
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@ -274,6 +278,8 @@
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<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tei", "ri", "ti", "spi", "sti",
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"naki", "ali", "tmoi";
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clocks = <&cpg CPG_MOD 85>;
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power-domains = <&cpg>;
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clock-frequency = <100000>;
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@ -293,6 +299,8 @@
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<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tei", "ri", "ti", "spi", "sti",
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"naki", "ali", "tmoi";
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clocks = <&cpg CPG_MOD 84>;
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power-domains = <&cpg>;
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clock-frequency = <100000>;
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@ -13,6 +13,13 @@
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#address-cells = <2>;
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#size-cells = <2>;
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/* External CAN clock - to be overridden by boards that provide it */
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can_clk: can {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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};
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/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
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extal_clk: extal {
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compatible = "fixed-clock";
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@ -89,6 +96,40 @@
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status = "disabled";
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};
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canfd: can@10050000 {
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compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
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reg = <0 0x10050000 0 0x8000>;
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interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "g_err", "g_recc",
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"ch0_err", "ch0_rec", "ch0_trx",
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"ch1_err", "ch1_rec", "ch1_trx";
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clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
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<&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
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<&can_clk>;
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clock-names = "fck", "canfd", "can_clk";
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assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
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assigned-clock-rates = <50000000>;
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resets = <&cpg R9A07G044_CANFD_RSTP_N>,
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<&cpg R9A07G044_CANFD_RSTC_N>;
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reset-names = "rstp_n", "rstc_n";
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power-domains = <&cpg>;
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status = "disabled";
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channel0 {
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status = "disabled";
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};
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channel1 {
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status = "disabled";
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};
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};
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i2c0: i2c@10058000 {
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#address-cells = <1>;
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#size-cells = <0>;
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@ -102,6 +143,8 @@
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<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tei", "ri", "ti", "spi", "sti",
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"naki", "ali", "tmoi";
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clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
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clock-frequency = <100000>;
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resets = <&cpg R9A07G044_I2C0_MRST>;
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@ -122,6 +165,8 @@
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<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tei", "ri", "ti", "spi", "sti",
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"naki", "ali", "tmoi";
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clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
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clock-frequency = <100000>;
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resets = <&cpg R9A07G044_I2C1_MRST>;
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@ -142,6 +187,8 @@
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<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tei", "ri", "ti", "spi", "sti",
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"naki", "ali", "tmoi";
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clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
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clock-frequency = <100000>;
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resets = <&cpg R9A07G044_I2C2_MRST>;
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@ -162,6 +209,8 @@
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<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tei", "ri", "ti", "spi", "sti",
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"naki", "ali", "tmoi";
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clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
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clock-frequency = <100000>;
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resets = <&cpg R9A07G044_I2C3_MRST>;
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status = "disabled";
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};
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adc: adc@10059000 {
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compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
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reg = <0 0x10059000 0 0x400>;
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interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
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clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
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<&cpg CPG_MOD R9A07G044_ADC_PCLK>;
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clock-names = "adclk", "pclk";
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resets = <&cpg R9A07G044_ADC_PRESETN>,
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<&cpg R9A07G044_ADC_ADRST_N>;
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reset-names = "presetn", "adrst-n";
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power-domains = <&cpg>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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channel@0 {
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reg = <0>;
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};
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channel@1 {
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reg = <1>;
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};
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channel@2 {
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reg = <2>;
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};
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channel@3 {
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reg = <3>;
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};
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channel@4 {
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reg = <4>;
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};
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channel@5 {
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reg = <5>;
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};
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channel@6 {
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reg = <6>;
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};
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channel@7 {
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reg = <7>;
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};
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};
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cpg: clock-controller@11010000 {
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compatible = "renesas,r9a07g044-cpg";
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reg = <0 0x11010000 0 0x10000>;
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@ -191,6 +282,19 @@
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status = "disabled";
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};
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pinctrl: pin-controller@11030000 {
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compatible = "renesas,r9a07g044-pinctrl";
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reg = <0 0x11030000 0 0x10000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 392>;
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clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_GPIO_RSTN>,
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<&cpg R9A07G044_GPIO_PORT_RESETN>,
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<&cpg R9A07G044_GPIO_SPARE_RESETN>;
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};
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gic: interrupt-controller@11900000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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@ -30,6 +30,7 @@
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#define R9A07G044_CLK_P2 19
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#define R9A07G044_CLK_AT 20
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#define R9A07G044_OSCCLK 21
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#define R9A07G044_CLK_P0_DIV2 22
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/* R9A07G044 Module Clocks */
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#define R9A07G044_CA55_SCLK 0
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