Merge tag 'drm-intel-fixes-2017-07-27' of git://anongit.freedesktop.org/git/drm-intel into drm-fixes
i915 fixes for -rc3 Bit more than usual since we missed -rc2. 4x cc: stable, 2 gvt patches, but all fairly minor stuff. Last minute rebase was to add a few missing cc: stable, I did prep the pull this morning already and made sure CI approves. * tag 'drm-intel-fixes-2017-07-27' of git://anongit.freedesktop.org/git/drm-intel: drm/i915: Fix bad comparison in skl_compute_plane_wm. drm/i915: Force CPU synchronisation even if userspace requests ASYNC drm/i915: Only skip updating execobject.offset after error drm/i915: Only mark the execobject as pinned on success drm/i915: Remove assertion from raw __i915_vma_unpin() drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence drm/i915: Fix scaler init during CRTC HW state readout drm/i915/selftests: Fix an error handling path in 'mock_gem_device()' drm/i915: Unbreak gpu reset vs. modeset locking drm/i915: Fix cursor updates on some platforms drm/i915: Fix user ptr check size in eb_relocate_vma() drm/i915/gvt: Extend KBL platform support in GVT-g drm/i915/gvt: Fix the vblank timer close issue after shutdown VMs in reverse
This commit is contained in:
Dave Airlie
Коммит
d5bcd1113b
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@ -323,27 +323,27 @@ void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
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{
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struct intel_gvt_irq *irq = &gvt->irq;
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struct intel_vgpu *vgpu;
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bool have_enabled_pipe = false;
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int pipe, id;
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if (WARN_ON(!mutex_is_locked(&gvt->lock)))
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return;
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hrtimer_cancel(&irq->vblank_timer.timer);
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for_each_active_vgpu(gvt, vgpu, id) {
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for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
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have_enabled_pipe =
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pipe_is_enabled(vgpu, pipe);
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if (have_enabled_pipe)
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break;
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if (pipe_is_enabled(vgpu, pipe))
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goto out;
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}
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}
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if (have_enabled_pipe)
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hrtimer_start(&irq->vblank_timer.timer,
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ktime_add_ns(ktime_get(), irq->vblank_timer.period),
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HRTIMER_MODE_ABS);
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/* all the pipes are disabled */
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hrtimer_cancel(&irq->vblank_timer.timer);
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return;
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out:
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hrtimer_start(&irq->vblank_timer.timer,
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ktime_add_ns(ktime_get(), irq->vblank_timer.period),
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HRTIMER_MODE_ABS);
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}
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static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
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@ -114,7 +114,7 @@ i915_clflush_notify(struct i915_sw_fence *fence,
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return NOTIFY_DONE;
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}
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void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
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bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
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unsigned int flags)
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{
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struct clflush *clflush;
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@ -128,7 +128,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
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*/
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if (!i915_gem_object_has_struct_page(obj)) {
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obj->cache_dirty = false;
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return;
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return false;
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}
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/* If the GPU is snooping the contents of the CPU cache,
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@ -140,7 +140,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
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* tracking.
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*/
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if (!(flags & I915_CLFLUSH_FORCE) && obj->cache_coherent)
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return;
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return false;
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trace_i915_gem_object_clflush(obj);
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@ -179,4 +179,5 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
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}
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obj->cache_dirty = false;
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return true;
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}
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@ -28,7 +28,7 @@
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struct drm_i915_private;
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struct drm_i915_gem_object;
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void i915_gem_clflush_object(struct drm_i915_gem_object *obj,
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bool i915_gem_clflush_object(struct drm_i915_gem_object *obj,
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unsigned int flags);
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#define I915_CLFLUSH_FORCE BIT(0)
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#define I915_CLFLUSH_SYNC BIT(1)
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@ -560,9 +560,6 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb,
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eb->args->flags |= __EXEC_HAS_RELOC;
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}
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entry->flags |= __EXEC_OBJECT_HAS_PIN;
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GEM_BUG_ON(eb_vma_misplaced(entry, vma));
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if (unlikely(entry->flags & EXEC_OBJECT_NEEDS_FENCE)) {
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err = i915_vma_get_fence(vma);
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if (unlikely(err)) {
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@ -574,6 +571,9 @@ static int eb_reserve_vma(const struct i915_execbuffer *eb,
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entry->flags |= __EXEC_OBJECT_HAS_FENCE;
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}
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entry->flags |= __EXEC_OBJECT_HAS_PIN;
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GEM_BUG_ON(eb_vma_misplaced(entry, vma));
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return 0;
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}
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@ -1458,7 +1458,7 @@ static int eb_relocate_vma(struct i915_execbuffer *eb, struct i915_vma *vma)
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* to read. However, if the array is not writable the user loses
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* the updated relocation values.
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*/
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if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(urelocs))))
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if (unlikely(!access_ok(VERIFY_READ, urelocs, remain*sizeof(*urelocs))))
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return -EFAULT;
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do {
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@ -1775,7 +1775,7 @@ out:
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}
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}
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return err ?: have_copy;
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return err;
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}
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static int eb_relocate(struct i915_execbuffer *eb)
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@ -1825,7 +1825,7 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
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int err;
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for (i = 0; i < count; i++) {
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const struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
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struct drm_i915_gem_exec_object2 *entry = &eb->exec[i];
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struct i915_vma *vma = exec_to_vma(entry);
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struct drm_i915_gem_object *obj = vma->obj;
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@ -1841,12 +1841,14 @@ static int eb_move_to_gpu(struct i915_execbuffer *eb)
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eb->request->capture_list = capture;
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}
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if (unlikely(obj->cache_dirty && !obj->cache_coherent)) {
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if (i915_gem_clflush_object(obj, 0))
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entry->flags &= ~EXEC_OBJECT_ASYNC;
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}
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if (entry->flags & EXEC_OBJECT_ASYNC)
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goto skip_flushes;
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if (unlikely(obj->cache_dirty && !obj->cache_coherent))
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i915_gem_clflush_object(obj, 0);
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err = i915_gem_request_await_object
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(eb->request, obj, entry->flags & EXEC_OBJECT_WRITE);
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if (err)
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@ -2209,7 +2211,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
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goto err_unlock;
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err = eb_relocate(&eb);
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if (err)
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if (err) {
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/*
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* If the user expects the execobject.offset and
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* reloc.presumed_offset to be an exact match,
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@ -2218,8 +2220,8 @@ i915_gem_do_execbuffer(struct drm_device *dev,
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* relocation.
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*/
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args->flags &= ~__EXEC_HAS_RELOC;
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if (err < 0)
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goto err_vma;
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}
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if (unlikely(eb.batch->exec_entry->flags & EXEC_OBJECT_WRITE)) {
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DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
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@ -284,12 +284,12 @@ static inline void __i915_vma_pin(struct i915_vma *vma)
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static inline void __i915_vma_unpin(struct i915_vma *vma)
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{
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GEM_BUG_ON(!i915_vma_is_pinned(vma));
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vma->flags--;
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}
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static inline void i915_vma_unpin(struct i915_vma *vma)
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{
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GEM_BUG_ON(!i915_vma_is_pinned(vma));
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GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
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__i915_vma_unpin(vma);
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}
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@ -1896,8 +1896,8 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, u32 level)
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val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln));
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val &= ~LOADGEN_SELECT;
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if (((rate < 600000) && (width == 4) && (ln >= 1)) ||
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((rate < 600000) && (width < 4) && ((ln == 1) || (ln == 2)))) {
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if ((rate <= 600000 && width == 4 && ln >= 1) ||
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(rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
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val |= LOADGEN_SELECT;
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}
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I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val);
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@ -3427,26 +3427,6 @@ static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
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intel_finish_page_flip_cs(dev_priv, crtc->pipe);
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}
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static void intel_update_primary_planes(struct drm_device *dev)
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{
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struct drm_crtc *crtc;
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for_each_crtc(dev, crtc) {
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struct intel_plane *plane = to_intel_plane(crtc->primary);
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struct intel_plane_state *plane_state =
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to_intel_plane_state(plane->base.state);
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if (plane_state->base.visible) {
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trace_intel_update_plane(&plane->base,
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to_intel_crtc(crtc));
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plane->update_plane(plane,
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to_intel_crtc_state(crtc->state),
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plane_state);
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}
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}
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}
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static int
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__intel_display_resume(struct drm_device *dev,
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struct drm_atomic_state *state,
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@ -3499,6 +3479,12 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv)
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struct drm_atomic_state *state;
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int ret;
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/* reset doesn't touch the display */
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if (!i915.force_reset_modeset_test &&
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!gpu_reset_clobbers_display(dev_priv))
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return;
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/*
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* Need mode_config.mutex so that we don't
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* trample ongoing ->detect() and whatnot.
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@ -3512,12 +3498,6 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv)
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drm_modeset_backoff(ctx);
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}
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/* reset doesn't touch the display, but flips might get nuked anyway, */
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if (!i915.force_reset_modeset_test &&
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!gpu_reset_clobbers_display(dev_priv))
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return;
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/*
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* Disabling the crtcs gracefully seems nicer. Also the
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* g33 docs say we should at least disable all the planes.
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@ -3547,6 +3527,14 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
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struct drm_atomic_state *state = dev_priv->modeset_restore_state;
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int ret;
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/* reset doesn't touch the display */
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if (!i915.force_reset_modeset_test &&
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!gpu_reset_clobbers_display(dev_priv))
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return;
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if (!state)
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goto unlock;
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/*
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* Flips in the rings will be nuked by the reset,
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* so complete all pending flips so that user space
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@ -3558,22 +3546,10 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
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/* reset doesn't touch the display */
|
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if (!gpu_reset_clobbers_display(dev_priv)) {
|
||||
if (!state) {
|
||||
/*
|
||||
* Flips in the rings have been nuked by the reset,
|
||||
* so update the base address of all primary
|
||||
* planes to the the last fb to make sure we're
|
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* showing the correct fb after a reset.
|
||||
*
|
||||
* FIXME: Atomic will make this obsolete since we won't schedule
|
||||
* CS-based flips (which might get lost in gpu resets) any more.
|
||||
*/
|
||||
intel_update_primary_planes(dev);
|
||||
} else {
|
||||
ret = __intel_display_resume(dev, state, ctx);
|
||||
/* for testing only restore the display */
|
||||
ret = __intel_display_resume(dev, state, ctx);
|
||||
if (ret)
|
||||
DRM_ERROR("Restoring old state failed with %i\n", ret);
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* The display has been reset as well,
|
||||
|
|
@ -3597,8 +3573,8 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
|
|||
intel_hpd_init(dev_priv);
|
||||
}
|
||||
|
||||
if (state)
|
||||
drm_atomic_state_put(state);
|
||||
drm_atomic_state_put(state);
|
||||
unlock:
|
||||
drm_modeset_drop_locks(ctx);
|
||||
drm_modeset_acquire_fini(ctx);
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
|
|
@ -9117,6 +9093,13 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
|
|||
u64 power_domain_mask;
|
||||
bool active;
|
||||
|
||||
if (INTEL_GEN(dev_priv) >= 9) {
|
||||
intel_crtc_init_scalers(crtc, pipe_config);
|
||||
|
||||
pipe_config->scaler_state.scaler_id = -1;
|
||||
pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
|
||||
}
|
||||
|
||||
power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
|
||||
if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
|
||||
return false;
|
||||
|
|
@ -9145,13 +9128,6 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
|
|||
pipe_config->gamma_mode =
|
||||
I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
|
||||
|
||||
if (INTEL_GEN(dev_priv) >= 9) {
|
||||
intel_crtc_init_scalers(crtc, pipe_config);
|
||||
|
||||
pipe_config->scaler_state.scaler_id = -1;
|
||||
pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
|
||||
}
|
||||
|
||||
power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
|
||||
if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
|
||||
power_domain_mask |= BIT_ULL(power_domain);
|
||||
|
|
@ -9540,7 +9516,16 @@ static void i9xx_update_cursor(struct intel_plane *plane,
|
|||
* On some platforms writing CURCNTR first will also
|
||||
* cause CURPOS to be armed by the CURBASE write.
|
||||
* Without the CURCNTR write the CURPOS write would
|
||||
* arm itself.
|
||||
* arm itself. Thus we always start the full update
|
||||
* with a CURCNTR write.
|
||||
*
|
||||
* On other platforms CURPOS always requires the
|
||||
* CURBASE write to arm the update. Additonally
|
||||
* a write to any of the cursor register will cancel
|
||||
* an already armed cursor update. Thus leaving out
|
||||
* the CURBASE write after CURPOS could lead to a
|
||||
* cursor that doesn't appear to move, or even change
|
||||
* shape. Thus we always write CURBASE.
|
||||
*
|
||||
* CURCNTR and CUR_FBC_CTL are always
|
||||
* armed by the CURBASE write only.
|
||||
|
|
@ -9559,6 +9544,7 @@ static void i9xx_update_cursor(struct intel_plane *plane,
|
|||
plane->cursor.cntl = cntl;
|
||||
} else {
|
||||
I915_WRITE_FW(CURPOS(pipe), pos);
|
||||
I915_WRITE_FW(CURBASE(pipe), base);
|
||||
}
|
||||
|
||||
POSTING_READ_FW(CURBASE(pipe));
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@ static bool is_supported_device(struct drm_i915_private *dev_priv)
|
|||
return true;
|
||||
if (IS_SKYLAKE(dev_priv))
|
||||
return true;
|
||||
if (IS_KABYLAKE(dev_priv) && INTEL_DEVID(dev_priv) == 0x591D)
|
||||
if (IS_KABYLAKE(dev_priv))
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4463,8 +4463,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
|
|||
if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
|
||||
(plane_bytes_per_line / 512 < 1))
|
||||
selected_result = method2;
|
||||
else if ((ddb_allocation && ddb_allocation /
|
||||
fixed_16_16_to_u32_round_up(plane_blocks_per_line)) >= 1)
|
||||
else if (ddb_allocation >=
|
||||
fixed_16_16_to_u32_round_up(plane_blocks_per_line))
|
||||
selected_result = min_fixed_16_16(method1, method2);
|
||||
else if (latency >= linetime_us)
|
||||
selected_result = min_fixed_16_16(method1, method2);
|
||||
|
|
|
|||
|
|
@ -206,7 +206,7 @@ struct drm_i915_private *mock_gem_device(void)
|
|||
mkwrite_device_info(i915)->ring_mask = BIT(0);
|
||||
i915->engine[RCS] = mock_engine(i915, "mock");
|
||||
if (!i915->engine[RCS])
|
||||
goto err_dependencies;
|
||||
goto err_priorities;
|
||||
|
||||
i915->kernel_context = mock_context(i915, NULL);
|
||||
if (!i915->kernel_context)
|
||||
|
|
|
|||
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