drm/amd/powerplay: added vega20 overdrive support V3
Added vega20 overdrive support based on existing OD sysfs
APIs. However, the OD logics are simplified on vega20. So,
the behavior will be a little different and works only on
some limited levels.
V2: fix typo
fix commit description
revise error logs
add support for clock OD
V3: separate clock from voltage OD settings
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan
Alex Deucher
Родитель
6abc0c8f8c
Коммит
d5bf265394
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@ -474,6 +474,8 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
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* in each power level within a power state. The pp_od_clk_voltage is used for
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* this.
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*
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* < For Vega10 and previous ASICs >
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*
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* Reading the file will display:
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*
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* - a list of engine clock levels and voltages labeled OD_SCLK
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@ -491,6 +493,44 @@ static ssize_t amdgpu_set_pp_table(struct device *dev,
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* "c" (commit) to the file to commit your changes. If you want to reset to the
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* default power levels, write "r" (reset) to the file to reset them.
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*
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*
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* < For Vega20 >
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*
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* Reading the file will display:
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*
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* - minimum and maximum engine clock labeled OD_SCLK
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*
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* - maximum memory clock labeled OD_MCLK
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*
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* - three <frequency, voltage offset> points labeled OD_VDDC_CURVE.
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* They can be used to calibrate the sclk voltage curve.
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*
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* - a list of valid ranges for sclk, mclk, and voltage curve points
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* labeled OD_RANGE
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*
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* To manually adjust these settings:
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*
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* - First select manual using power_dpm_force_performance_level
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*
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* - For clock frequency setting, enter a new value by writing a
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* string that contains "s/m index clock" to the file. The index
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* should be 0 if to set minimum clock. And 1 if to set maximum
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* clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
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* "m 1 800" will update maximum mclk to be 800Mhz.
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*
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* For sclk voltage curve, enter the new values by writing a
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* string that contains "vc point clock voff" to the file. The
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* points are indexed by 0, 1 and 2. E.g., "vc 0 300 10" will
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* update point1 with clock set as 300Mhz and voltage increased
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* by 10mV. "vc 2 1000 -10" will update point3 with clock set
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* as 1000Mhz and voltage drop by 10mV.
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*
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* - When you have edited all of the states as needed, write "c" (commit)
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* to the file to commit your changes
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*
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* - If you want to reset to the default power levels, write "r" (reset)
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* to the file to reset them
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*
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*/
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static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
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@ -520,6 +560,8 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
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type = PP_OD_RESTORE_DEFAULT_TABLE;
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else if (*buf == 'c')
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type = PP_OD_COMMIT_DPM_TABLE;
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else if (!strncmp(buf, "vc", 2))
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type = PP_OD_EDIT_VDDC_CURVE;
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else
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return -EINVAL;
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@ -527,6 +569,8 @@ static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
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tmp_str = buf_cpy;
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if (type == PP_OD_EDIT_VDDC_CURVE)
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tmp_str++;
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while (isspace(*++tmp_str));
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while (tmp_str[0]) {
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@ -570,6 +614,7 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
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if (adev->powerplay.pp_funcs->print_clock_levels) {
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size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
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size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
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size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
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size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
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return size;
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} else {
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@ -94,6 +94,7 @@ enum pp_clock_type {
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PP_PCIE,
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OD_SCLK,
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OD_MCLK,
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OD_VDDC_CURVE,
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OD_RANGE,
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};
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@ -141,6 +142,7 @@ enum {
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enum PP_OD_DPM_TABLE_COMMAND {
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PP_OD_EDIT_SCLK_VDDC_TABLE,
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PP_OD_EDIT_MCLK_VDDC_TABLE,
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PP_OD_EDIT_VDDC_CURVE,
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PP_OD_RESTORE_DEFAULT_TABLE,
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PP_OD_COMMIT_DPM_TABLE
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};
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@ -2325,11 +2325,207 @@ static int vega20_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
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return 0;
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}
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static int vega20_odn_edit_dpm_table(struct pp_hwmgr *hwmgr,
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enum PP_OD_DPM_TABLE_COMMAND type,
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long *input, uint32_t size)
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{
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struct vega20_hwmgr *data =
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(struct vega20_hwmgr *)(hwmgr->backend);
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struct vega20_od8_single_setting *od8_settings =
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data->od8_settings.od8_settings_array;
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OverDriveTable_t *od_table =
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&(data->smc_state_table.overdrive_table);
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struct pp_clock_levels_with_latency clocks;
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int32_t input_index, input_clk, input_vol, i;
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int ret;
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PP_ASSERT_WITH_CODE(input, "NULL user input for clock and voltage",
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return -EINVAL);
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switch (type) {
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case PP_OD_EDIT_SCLK_VDDC_TABLE:
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if (!(od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id)) {
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pr_info("Sclk min/max frequency overdrive not supported\n");
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return -EOPNOTSUPP;
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}
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for (i = 0; i < size; i += 2) {
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if (i + 2 > size) {
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pr_info("invalid number of input parameters %d\n",
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size);
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return -EINVAL;
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}
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input_index = input[i];
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input_clk = input[i + 1];
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if (input_index != 0 && input_index != 1) {
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pr_info("Invalid index %d\n", input_index);
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pr_info("Support min/max sclk frequency setting only which index by 0/1\n");
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return -EINVAL;
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}
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if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
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input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
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pr_info("clock freq %d is not within allowed range [%d - %d]\n",
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input_clk,
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od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
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od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
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return -EINVAL;
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}
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if (input_index == 0)
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od_table->GfxclkFmin = input_clk;
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else
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od_table->GfxclkFmax = input_clk;
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}
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break;
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case PP_OD_EDIT_MCLK_VDDC_TABLE:
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if (!od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
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pr_info("Mclk max frequency overdrive not supported\n");
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return -EOPNOTSUPP;
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}
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ret = vega20_get_memclocks(hwmgr, &clocks);
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PP_ASSERT_WITH_CODE(!ret,
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"Attempt to get memory clk levels failed!",
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return ret);
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for (i = 0; i < size; i += 2) {
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if (i + 2 > size) {
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pr_info("invalid number of input parameters %d\n",
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size);
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return -EINVAL;
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}
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input_index = input[i];
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input_clk = input[i + 1];
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if (input_index != 1) {
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pr_info("Invalid index %d\n", input_index);
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pr_info("Support max Mclk frequency setting only which index by 1\n");
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return -EINVAL;
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}
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if (input_clk < clocks.data[0].clocks_in_khz / 100 ||
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input_clk > od8_settings[OD8_SETTING_UCLK_FMAX].max_value) {
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pr_info("clock freq %d is not within allowed range [%d - %d]\n",
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input_clk,
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clocks.data[0].clocks_in_khz / 100,
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od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
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return -EINVAL;
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}
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od_table->UclkFmax = input_clk;
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}
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break;
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case PP_OD_EDIT_VDDC_CURVE:
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if (!(od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id)) {
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pr_info("Voltage curve calibrate not supported\n");
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return -EOPNOTSUPP;
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}
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for (i = 0; i < size; i += 3) {
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if (i + 3 > size) {
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pr_info("invalid number of input parameters %d\n",
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size);
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return -EINVAL;
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}
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input_index = input[i];
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input_clk = input[i + 1];
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input_vol = input[i + 2];
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if (input_index > 2) {
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pr_info("Setting for point %d is not supported\n",
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input_index + 1);
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pr_info("Three supported points index by 0, 1, 2\n");
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return -EINVAL;
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}
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if (input_clk < od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value ||
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input_clk > od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value) {
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pr_info("clock freq %d is not within allowed range [%d - %d]\n",
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input_clk,
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od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
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od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
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return -EINVAL;
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}
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/* TODO: suppose voltage1/2/3 has the same min/max value */
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if (input_vol < od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value ||
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input_vol > od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value) {
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pr_info("clock voltage offset %d is not within allowed range [%d - %d]\n",
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input_vol,
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
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return -EINVAL;
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}
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switch (input_index) {
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case 0:
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od_table->GfxclkFreq1 = input_clk;
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od_table->GfxclkOffsetVolt1 = input_vol;
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break;
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case 1:
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od_table->GfxclkFreq2 = input_clk;
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od_table->GfxclkOffsetVolt2 = input_vol;
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break;
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case 2:
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od_table->GfxclkFreq3 = input_clk;
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od_table->GfxclkOffsetVolt3 = input_vol;
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break;
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}
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}
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break;
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case PP_OD_RESTORE_DEFAULT_TABLE:
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ret = vega20_copy_table_from_smc(hwmgr,
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(uint8_t *)od_table,
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TABLE_OVERDRIVE);
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PP_ASSERT_WITH_CODE(!ret,
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"Failed to export overdrive table!",
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return ret);
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break;
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case PP_OD_COMMIT_DPM_TABLE:
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ret = vega20_copy_table_to_smc(hwmgr,
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(uint8_t *)od_table,
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TABLE_OVERDRIVE);
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PP_ASSERT_WITH_CODE(!ret,
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"Failed to import overdrive table!",
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return ret);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
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enum pp_clock_type type, char *buf)
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{
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int i, now, size = 0;
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struct vega20_hwmgr *data =
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(struct vega20_hwmgr *)(hwmgr->backend);
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struct vega20_od8_single_setting *od8_settings =
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data->od8_settings.od8_settings_array;
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OverDriveTable_t *od_table =
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&(data->smc_state_table.overdrive_table);
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struct pp_clock_levels_with_latency clocks;
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int i, now, size = 0;
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int ret = 0;
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switch (type) {
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@ -2370,6 +2566,95 @@ static int vega20_print_clock_levels(struct pp_hwmgr *hwmgr,
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case PP_PCIE:
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break;
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case OD_SCLK:
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if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
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size = sprintf(buf, "%s:\n", "OD_SCLK");
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size += sprintf(buf + size, "0: %10uMhz\n",
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od_table->GfxclkFmin);
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size += sprintf(buf + size, "1: %10uMhz\n",
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od_table->GfxclkFmax);
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}
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break;
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case OD_MCLK:
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if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
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size = sprintf(buf, "%s:\n", "OD_MCLK");
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size += sprintf(buf + size, "1: %10uMhz\n",
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od_table->UclkFmax);
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}
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break;
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case OD_VDDC_CURVE:
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if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
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size = sprintf(buf, "%s:\n", "OD_VDDC_CURVE");
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size += sprintf(buf + size, "0: %10uMhz %10dmV\n",
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od_table->GfxclkFreq1,
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od_table->GfxclkOffsetVolt1);
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size += sprintf(buf + size, "1: %10uMhz %10dmV\n",
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od_table->GfxclkFreq2,
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od_table->GfxclkOffsetVolt2);
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size += sprintf(buf + size, "2: %10uMhz %10dmV\n",
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od_table->GfxclkFreq3,
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od_table->GfxclkOffsetVolt3);
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}
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||||
break;
|
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|
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case OD_RANGE:
|
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size = sprintf(buf, "%s:\n", "OD_RANGE");
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|
||||
if (od8_settings[OD8_SETTING_GFXCLK_FMIN].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_FMAX].feature_id) {
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size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
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od8_settings[OD8_SETTING_GFXCLK_FMIN].min_value,
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od8_settings[OD8_SETTING_GFXCLK_FMAX].max_value);
|
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}
|
||||
|
||||
if (od8_settings[OD8_SETTING_UCLK_FMAX].feature_id) {
|
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ret = vega20_get_memclocks(hwmgr, &clocks);
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PP_ASSERT_WITH_CODE(!ret,
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"Fail to get memory clk levels!",
|
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return ret);
|
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|
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size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
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clocks.data[0].clocks_in_khz / 100,
|
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od8_settings[OD8_SETTING_UCLK_FMAX].max_value);
|
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}
|
||||
|
||||
if (od8_settings[OD8_SETTING_GFXCLK_FREQ1].feature_id &&
|
||||
od8_settings[OD8_SETTING_GFXCLK_FREQ2].feature_id &&
|
||||
od8_settings[OD8_SETTING_GFXCLK_FREQ3].feature_id &&
|
||||
od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].feature_id &&
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].feature_id &&
|
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].feature_id) {
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size += sprintf(buf + size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
|
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od8_settings[OD8_SETTING_GFXCLK_FREQ1].min_value,
|
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od8_settings[OD8_SETTING_GFXCLK_FREQ1].max_value);
|
||||
size += sprintf(buf + size, "VDDC_CURVE_VOFF[0]: %7dmV %11dmV\n",
|
||||
od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].min_value,
|
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od8_settings[OD8_SETTING_GFXCLK_VOLTAGE1].max_value);
|
||||
size += sprintf(buf + size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
|
||||
od8_settings[OD8_SETTING_GFXCLK_FREQ2].min_value,
|
||||
od8_settings[OD8_SETTING_GFXCLK_FREQ2].max_value);
|
||||
size += sprintf(buf + size, "VDDC_CURVE_VOFF[1]: %7dmV %11dmV\n",
|
||||
od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].min_value,
|
||||
od8_settings[OD8_SETTING_GFXCLK_VOLTAGE2].max_value);
|
||||
size += sprintf(buf + size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
|
||||
od8_settings[OD8_SETTING_GFXCLK_FREQ3].min_value,
|
||||
od8_settings[OD8_SETTING_GFXCLK_FREQ3].max_value);
|
||||
size += sprintf(buf + size, "VDDC_CURVE_VOFF[2]: %7dmV %11dmV\n",
|
||||
od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].min_value,
|
||||
od8_settings[OD8_SETTING_GFXCLK_VOLTAGE3].max_value);
|
||||
}
|
||||
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -2977,6 +3262,8 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = {
|
|||
vega20_get_mclk_od,
|
||||
.set_mclk_od =
|
||||
vega20_set_mclk_od,
|
||||
.odn_edit_dpm_table =
|
||||
vega20_odn_edit_dpm_table,
|
||||
/* for sysfs to retrive/set gfxclk/memclk */
|
||||
.force_clock_level =
|
||||
vega20_force_clock_level,
|
||||
|
|
|
|||
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Ссылка в новой задаче