max44000: Expose ambient sensor scaling
This patch exposes ALSTIM as illuminance_integration_time and ALSPGA as illuminance_scale. Changing ALSTIM also changes the number of bits available in the data register. This is handled inside raw value reading because: * It's very easy to shift a few bits * It allows SCALE and INT_TIME to be completely independent controls * Buffer support requires constant scan_type.realbits per-channel Signed-off-by: Crestez Dan Leonard <leonard.crestez@intel.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
This commit is contained in:
Crestez Dan Leonard
Jonathan Cameron
Родитель
237a378b3b
Коммит
d5d8f49b63
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@ -59,6 +59,12 @@
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*/
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#define MAX44000_REG_CFG_RX_DEFAULT 0xf0
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/* REG_RX bits */
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#define MAX44000_CFG_RX_ALSTIM_MASK 0x0c
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#define MAX44000_CFG_RX_ALSTIM_SHIFT 2
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#define MAX44000_CFG_RX_ALSPGA_MASK 0x03
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#define MAX44000_CFG_RX_ALSPGA_SHIFT 0
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/* REG_TX bits */
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#define MAX44000_LED_CURRENT_MASK 0xf
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#define MAX44000_LED_CURRENT_MAX 11
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@ -74,11 +80,57 @@ struct max44000_data {
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/* Default scale is set to the minimum of 0.03125 or 1 / (1 << 5) lux */
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#define MAX44000_ALS_TO_LUX_DEFAULT_FRACTION_LOG2 5
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/* Scale can be multiplied by up to 128x via ALSPGA for measurement gain */
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static const int max44000_alspga_shift[] = {0, 2, 4, 7};
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#define MAX44000_ALSPGA_MAX_SHIFT 7
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/*
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* Scale can be multiplied by up to 64x via ALSTIM because of lost resolution
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*
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* This scaling factor is hidden from userspace and instead accounted for when
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* reading raw values from the device.
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*
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* This makes it possible to cleanly expose ALSPGA as IIO_CHAN_INFO_SCALE and
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* ALSTIM as IIO_CHAN_INFO_INT_TIME without the values affecting each other.
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*
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* Handling this internally is also required for buffer support because the
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* channel's scan_type can't be modified dynamically.
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*/
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static const int max44000_alstim_shift[] = {0, 2, 4, 6};
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#define MAX44000_ALSTIM_SHIFT(alstim) (2 * (alstim))
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/* Available integration times with pretty manual alignment: */
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static const int max44000_int_time_avail_ns_array[] = {
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100000000,
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25000000,
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6250000,
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1562500,
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};
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static const char max44000_int_time_avail_str[] =
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"0.100 "
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"0.025 "
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"0.00625 "
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"0.001625";
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/* Available scales (internal to ulux) with pretty manual alignment: */
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static const int max44000_scale_avail_ulux_array[] = {
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31250,
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125000,
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500000,
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4000000,
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};
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static const char max44000_scale_avail_str[] =
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"0.03125 "
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"0.125 "
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"0.5 "
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"4";
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static const struct iio_chan_spec max44000_channels[] = {
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{
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.type = IIO_LIGHT,
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.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
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.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
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BIT(IIO_CHAN_INFO_INT_TIME),
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},
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{
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.type = IIO_PROXIMITY,
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@ -94,15 +146,54 @@ static const struct iio_chan_spec max44000_channels[] = {
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},
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};
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static int max44000_read_alstim(struct max44000_data *data)
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{
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unsigned int val;
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int ret;
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ret = regmap_read(data->regmap, MAX44000_REG_CFG_RX, &val);
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if (ret < 0)
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return ret;
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return (val & MAX44000_CFG_RX_ALSTIM_MASK) >> MAX44000_CFG_RX_ALSTIM_SHIFT;
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}
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static int max44000_write_alstim(struct max44000_data *data, int val)
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{
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return regmap_write_bits(data->regmap, MAX44000_REG_CFG_RX,
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MAX44000_CFG_RX_ALSTIM_MASK,
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val << MAX44000_CFG_RX_ALSTIM_SHIFT);
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}
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static int max44000_read_alspga(struct max44000_data *data)
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{
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unsigned int val;
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int ret;
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ret = regmap_read(data->regmap, MAX44000_REG_CFG_RX, &val);
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if (ret < 0)
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return ret;
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return (val & MAX44000_CFG_RX_ALSPGA_MASK) >> MAX44000_CFG_RX_ALSPGA_SHIFT;
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}
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static int max44000_write_alspga(struct max44000_data *data, int val)
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{
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return regmap_write_bits(data->regmap, MAX44000_REG_CFG_RX,
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MAX44000_CFG_RX_ALSPGA_MASK,
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val << MAX44000_CFG_RX_ALSPGA_SHIFT);
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}
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static int max44000_read_alsval(struct max44000_data *data)
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{
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u16 regval;
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int ret;
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int alstim, ret;
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ret = regmap_bulk_read(data->regmap, MAX44000_REG_ALS_DATA_HI,
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®val, sizeof(regval));
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if (ret < 0)
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return ret;
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alstim = ret = max44000_read_alstim(data);
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if (ret < 0)
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return ret;
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regval = be16_to_cpu(regval);
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@ -118,7 +209,7 @@ static int max44000_read_alsval(struct max44000_data *data)
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if (regval & MAX44000_ALSDATA_OVERFLOW)
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return 0x3FFF;
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return regval;
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return regval << MAX44000_ALSTIM_SHIFT(alstim);
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}
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static int max44000_write_led_current_raw(struct max44000_data *data, int val)
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@ -151,6 +242,7 @@ static int max44000_read_raw(struct iio_dev *indio_dev,
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int *val, int *val2, long mask)
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{
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struct max44000_data *data = iio_priv(indio_dev);
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int alstim, alspga;
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unsigned int regval;
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int ret;
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@ -196,14 +288,34 @@ static int max44000_read_raw(struct iio_dev *indio_dev,
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return IIO_VAL_INT;
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case IIO_LIGHT:
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*val = 1;
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*val2 = MAX44000_ALS_TO_LUX_DEFAULT_FRACTION_LOG2;
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mutex_lock(&data->lock);
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alspga = ret = max44000_read_alspga(data);
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mutex_unlock(&data->lock);
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if (ret < 0)
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return ret;
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/* Avoid negative shifts */
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*val = (1 << MAX44000_ALSPGA_MAX_SHIFT);
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*val2 = MAX44000_ALS_TO_LUX_DEFAULT_FRACTION_LOG2
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+ MAX44000_ALSPGA_MAX_SHIFT
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- max44000_alspga_shift[alspga];
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return IIO_VAL_FRACTIONAL_LOG2;
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default:
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return -EINVAL;
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}
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case IIO_CHAN_INFO_INT_TIME:
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mutex_lock(&data->lock);
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alstim = ret = max44000_read_alstim(data);
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mutex_unlock(&data->lock);
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if (ret < 0)
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return ret;
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*val = 0;
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*val2 = max44000_int_time_avail_ns_array[alstim];
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return IIO_VAL_INT_PLUS_NANO;
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default:
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return -EINVAL;
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}
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@ -221,15 +333,60 @@ static int max44000_write_raw(struct iio_dev *indio_dev,
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ret = max44000_write_led_current_raw(data, val);
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mutex_unlock(&data->lock);
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return ret;
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} else if (mask == IIO_CHAN_INFO_INT_TIME && chan->type == IIO_LIGHT) {
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s64 valns = val * NSEC_PER_SEC + val2;
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int alstim = find_closest_descending(valns,
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max44000_int_time_avail_ns_array,
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ARRAY_SIZE(max44000_int_time_avail_ns_array));
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mutex_lock(&data->lock);
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ret = max44000_write_alstim(data, alstim);
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mutex_unlock(&data->lock);
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return ret;
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} else if (mask == IIO_CHAN_INFO_SCALE && chan->type == IIO_LIGHT) {
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s64 valus = val * USEC_PER_SEC + val2;
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int alspga = find_closest(valus,
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max44000_scale_avail_ulux_array,
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ARRAY_SIZE(max44000_scale_avail_ulux_array));
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mutex_lock(&data->lock);
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ret = max44000_write_alspga(data, alspga);
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mutex_unlock(&data->lock);
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return ret;
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}
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return -EINVAL;
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}
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static int max44000_write_raw_get_fmt(struct iio_dev *indio_dev,
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struct iio_chan_spec const *chan,
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long mask)
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{
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if (mask == IIO_CHAN_INFO_INT_TIME && chan->type == IIO_LIGHT)
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return IIO_VAL_INT_PLUS_NANO;
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else if (mask == IIO_CHAN_INFO_SCALE && chan->type == IIO_LIGHT)
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return IIO_VAL_INT_PLUS_MICRO;
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else
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return IIO_VAL_INT;
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}
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static IIO_CONST_ATTR(illuminance_integration_time_available, max44000_int_time_avail_str);
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static IIO_CONST_ATTR(illuminance_scale_available, max44000_scale_avail_str);
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static struct attribute *max44000_attributes[] = {
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&iio_const_attr_illuminance_integration_time_available.dev_attr.attr,
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&iio_const_attr_illuminance_scale_available.dev_attr.attr,
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NULL
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};
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static const struct attribute_group max44000_attribute_group = {
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.attrs = max44000_attributes,
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};
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static const struct iio_info max44000_info = {
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.driver_module = THIS_MODULE,
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.read_raw = max44000_read_raw,
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.write_raw = max44000_write_raw,
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.write_raw_get_fmt = max44000_write_raw_get_fmt,
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.attrs = &max44000_attribute_group,
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};
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static bool max44000_readable_reg(struct device *dev, unsigned int reg)
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