tty/8250_dw: Add support for OCTEON UARTS.
A few differences needed by OCTEON: o These are DWC UARTS, but have USR at a different offset. o Internal SoC buses require reading back from registers to maintain write ordering. o 8250 on OCTEON appears with 64-bit wide registers, so when using readb/writeb in big endian mode we have to adjust the membase to hit the proper part of the register. o No UCV register, so we hard code some properties. Because OCTEON doesn't have a UCV register, I change where dw8250_setup_port(), which reads the UCV, is called by pushing it in to the OF and ACPI probe functions, and move unchanged dw8250_setup_port() earlier in the file. Signed-off-by: David Daney <david.daney@cavium.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com> Cc: linux-mips@linux-mips.org Cc: Jamie Iles <jamie@jamieiles.com> Cc: Jiri Slaby <jslaby@suse.cz> Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/5516/ Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
Родитель
5219343f83
Коммит
d5f1af7ece
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@ -29,6 +29,8 @@
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <asm/byteorder.h>
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#include "8250.h"
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/* Offsets for the DesignWare specific registers */
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@ -57,6 +59,7 @@ struct dw8250_data {
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int last_lcr;
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int line;
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struct clk *clk;
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u8 usr_reg;
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};
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static void dw8250_serial_out(struct uart_port *p, int offset, int value)
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@ -77,6 +80,13 @@ static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
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return readb(p->membase + offset);
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}
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/* Read Back (rb) version to ensure register access ording. */
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static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
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{
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dw8250_serial_out(p, offset, value);
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dw8250_serial_in(p, UART_LCR);
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}
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static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = p->private_data;
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@ -104,7 +114,7 @@ static int dw8250_handle_irq(struct uart_port *p)
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return 1;
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} else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
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/* Clear the USR and write the LCR again. */
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(void)p->serial_in(p, DW_UART_USR);
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(void)p->serial_in(p, d->usr_reg);
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p->serial_out(p, UART_LCR, d->last_lcr);
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return 1;
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@ -125,77 +135,6 @@ dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
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pm_runtime_put_sync_suspend(port->dev);
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}
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static int dw8250_probe_of(struct uart_port *p)
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{
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struct device_node *np = p->dev->of_node;
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u32 val;
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if (!of_property_read_u32(np, "reg-io-width", &val)) {
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switch (val) {
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case 1:
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break;
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case 4:
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p->iotype = UPIO_MEM32;
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p->serial_in = dw8250_serial_in32;
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p->serial_out = dw8250_serial_out32;
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break;
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default:
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dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
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return -EINVAL;
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}
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}
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if (!of_property_read_u32(np, "reg-shift", &val))
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p->regshift = val;
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/* clock got configured through clk api, all done */
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if (p->uartclk)
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return 0;
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/* try to find out clock frequency from DT as fallback */
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if (of_property_read_u32(np, "clock-frequency", &val)) {
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dev_err(p->dev, "clk or clock-frequency not defined\n");
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return -EINVAL;
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}
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p->uartclk = val;
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return 0;
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}
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#ifdef CONFIG_ACPI
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static int dw8250_probe_acpi(struct uart_8250_port *up)
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{
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const struct acpi_device_id *id;
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struct uart_port *p = &up->port;
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id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
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if (!id)
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return -ENODEV;
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p->iotype = UPIO_MEM32;
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p->serial_in = dw8250_serial_in32;
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p->serial_out = dw8250_serial_out32;
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p->regshift = 2;
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if (!p->uartclk)
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p->uartclk = (unsigned int)id->driver_data;
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up->dma = devm_kzalloc(p->dev, sizeof(*up->dma), GFP_KERNEL);
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if (!up->dma)
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return -ENOMEM;
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up->dma->rxconf.src_maxburst = p->fifosize / 4;
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up->dma->txconf.dst_maxburst = p->fifosize / 4;
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return 0;
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}
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#else
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static inline int dw8250_probe_acpi(struct uart_8250_port *up)
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{
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return -ENODEV;
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}
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#endif /* CONFIG_ACPI */
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static void dw8250_setup_port(struct uart_8250_port *up)
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{
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struct uart_port *p = &up->port;
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@ -228,6 +167,97 @@ static void dw8250_setup_port(struct uart_8250_port *up)
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up->capabilities |= UART_CAP_AFE;
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}
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static int dw8250_probe_of(struct uart_port *p,
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struct dw8250_data *data)
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{
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struct device_node *np = p->dev->of_node;
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u32 val;
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bool has_ucv = true;
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if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
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#ifdef __BIG_ENDIAN
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/*
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* Low order bits of these 64-bit registers, when
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* accessed as a byte, are 7 bytes further down in the
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* address space in big endian mode.
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*/
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p->membase += 7;
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#endif
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p->serial_out = dw8250_serial_out_rb;
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p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
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p->type = PORT_OCTEON;
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data->usr_reg = 0x27;
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has_ucv = false;
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} else if (!of_property_read_u32(np, "reg-io-width", &val)) {
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switch (val) {
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case 1:
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break;
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case 4:
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p->iotype = UPIO_MEM32;
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p->serial_in = dw8250_serial_in32;
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p->serial_out = dw8250_serial_out32;
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break;
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default:
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dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
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return -EINVAL;
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}
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}
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if (has_ucv)
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dw8250_setup_port(container_of(p, struct uart_8250_port, port));
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if (!of_property_read_u32(np, "reg-shift", &val))
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p->regshift = val;
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/* clock got configured through clk api, all done */
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if (p->uartclk)
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return 0;
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/* try to find out clock frequency from DT as fallback */
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if (of_property_read_u32(np, "clock-frequency", &val)) {
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dev_err(p->dev, "clk or clock-frequency not defined\n");
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return -EINVAL;
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}
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p->uartclk = val;
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return 0;
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}
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#ifdef CONFIG_ACPI
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static int dw8250_probe_acpi(struct uart_8250_port *up)
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{
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const struct acpi_device_id *id;
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struct uart_port *p = &up->port;
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dw8250_setup_port(up);
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id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
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if (!id)
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return -ENODEV;
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p->iotype = UPIO_MEM32;
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p->serial_in = dw8250_serial_in32;
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p->serial_out = dw8250_serial_out32;
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p->regshift = 2;
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if (!p->uartclk)
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p->uartclk = (unsigned int)id->driver_data;
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up->dma = devm_kzalloc(p->dev, sizeof(*up->dma), GFP_KERNEL);
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if (!up->dma)
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return -ENOMEM;
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up->dma->rxconf.src_maxburst = p->fifosize / 4;
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up->dma->txconf.dst_maxburst = p->fifosize / 4;
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return 0;
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}
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#else
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static inline int dw8250_probe_acpi(struct uart_8250_port *up)
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{
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return -ENODEV;
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}
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#endif /* CONFIG_ACPI */
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static int dw8250_probe(struct platform_device *pdev)
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{
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struct uart_8250_port uart = {};
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@ -259,6 +289,7 @@ static int dw8250_probe(struct platform_device *pdev)
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if (!data)
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return -ENOMEM;
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data->usr_reg = DW_UART_USR;
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data->clk = devm_clk_get(&pdev->dev, NULL);
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if (!IS_ERR(data->clk)) {
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clk_prepare_enable(data->clk);
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@ -270,10 +301,8 @@ static int dw8250_probe(struct platform_device *pdev)
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uart.port.serial_out = dw8250_serial_out;
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uart.port.private_data = data;
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dw8250_setup_port(&uart);
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if (pdev->dev.of_node) {
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err = dw8250_probe_of(&uart.port);
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err = dw8250_probe_of(&uart.port, data);
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if (err)
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return err;
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} else if (ACPI_HANDLE(&pdev->dev)) {
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@ -362,6 +391,7 @@ static const struct dev_pm_ops dw8250_pm_ops = {
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static const struct of_device_id dw8250_of_match[] = {
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{ .compatible = "snps,dw-apb-uart" },
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{ .compatible = "cavium,octeon-3860-uart" },
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{ /* Sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, dw8250_of_match);
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