ia64/pv_ops/xen: define xen paravirtualized instructions for hand written assembly code
define xen paravirtualized instructions for hand written assembly code. Signed-off-by: Yaozu (Eddie) Dong <eddie.dong@intel.com> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Cc: Akio Takebe <takebe_akio@jp.fujitsu.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Isaku Yamahata
Tony Luck
Родитель
4b83ce4367
Коммит
d65b503edd
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/******************************************************************************
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* arch/ia64/include/asm/xen/inst.h
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*
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* Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <asm/xen/privop.h>
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#define MOV_FROM_IFA(reg) \
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movl reg = XSI_IFA; \
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;; \
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ld8 reg = [reg]
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#define MOV_FROM_ITIR(reg) \
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movl reg = XSI_ITIR; \
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;; \
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ld8 reg = [reg]
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#define MOV_FROM_ISR(reg) \
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movl reg = XSI_ISR; \
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;; \
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ld8 reg = [reg]
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#define MOV_FROM_IHA(reg) \
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movl reg = XSI_IHA; \
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;; \
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ld8 reg = [reg]
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#define MOV_FROM_IPSR(pred, reg) \
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(pred) movl reg = XSI_IPSR; \
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;; \
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(pred) ld8 reg = [reg]
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#define MOV_FROM_IIM(reg) \
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movl reg = XSI_IIM; \
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;; \
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ld8 reg = [reg]
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#define MOV_FROM_IIP(reg) \
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movl reg = XSI_IIP; \
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;; \
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ld8 reg = [reg]
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.macro __MOV_FROM_IVR reg, clob
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.ifc "\reg", "r8"
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XEN_HYPER_GET_IVR
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.exitm
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.endif
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.ifc "\clob", "r8"
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XEN_HYPER_GET_IVR
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;;
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mov \reg = r8
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.exitm
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.endif
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mov \clob = r8
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;;
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XEN_HYPER_GET_IVR
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;;
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mov \reg = r8
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;;
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mov r8 = \clob
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.endm
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#define MOV_FROM_IVR(reg, clob) __MOV_FROM_IVR reg, clob
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.macro __MOV_FROM_PSR pred, reg, clob
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.ifc "\reg", "r8"
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(\pred) XEN_HYPER_GET_PSR;
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.exitm
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.endif
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.ifc "\clob", "r8"
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(\pred) XEN_HYPER_GET_PSR
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;;
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(\pred) mov \reg = r8
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.exitm
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.endif
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(\pred) mov \clob = r8
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(\pred) XEN_HYPER_GET_PSR
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;;
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(\pred) mov \reg = r8
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(\pred) mov r8 = \clob
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.endm
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#define MOV_FROM_PSR(pred, reg, clob) __MOV_FROM_PSR pred, reg, clob
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#define MOV_TO_IFA(reg, clob) \
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movl clob = XSI_IFA; \
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;; \
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st8 [clob] = reg \
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#define MOV_TO_ITIR(pred, reg, clob) \
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(pred) movl clob = XSI_ITIR; \
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;; \
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(pred) st8 [clob] = reg
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#define MOV_TO_IHA(pred, reg, clob) \
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(pred) movl clob = XSI_IHA; \
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;; \
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(pred) st8 [clob] = reg
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#define MOV_TO_IPSR(pred, reg, clob) \
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(pred) movl clob = XSI_IPSR; \
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;; \
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(pred) st8 [clob] = reg; \
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;;
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#define MOV_TO_IFS(pred, reg, clob) \
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(pred) movl clob = XSI_IFS; \
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;; \
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(pred) st8 [clob] = reg; \
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;;
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#define MOV_TO_IIP(reg, clob) \
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movl clob = XSI_IIP; \
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;; \
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st8 [clob] = reg
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.macro ____MOV_TO_KR kr, reg, clob0, clob1
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.ifc "\clob0", "r9"
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.error "clob0 \clob0 must not be r9"
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.endif
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.ifc "\clob1", "r8"
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.error "clob1 \clob1 must not be r8"
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.endif
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.ifnc "\reg", "r9"
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.ifnc "\clob1", "r9"
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mov \clob1 = r9
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.endif
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mov r9 = \reg
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.endif
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.ifnc "\clob0", "r8"
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mov \clob0 = r8
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.endif
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mov r8 = \kr
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;;
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XEN_HYPER_SET_KR
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.ifnc "\reg", "r9"
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.ifnc "\clob1", "r9"
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mov r9 = \clob1
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.endif
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.endif
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.ifnc "\clob0", "r8"
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mov r8 = \clob0
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.endif
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.endm
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.macro __MOV_TO_KR kr, reg, clob0, clob1
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.ifc "\clob0", "r9"
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____MOV_TO_KR \kr, \reg, \clob1, \clob0
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.exitm
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.endif
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.ifc "\clob1", "r8"
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____MOV_TO_KR \kr, \reg, \clob1, \clob0
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.exitm
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.endif
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____MOV_TO_KR \kr, \reg, \clob0, \clob1
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.endm
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#define MOV_TO_KR(kr, reg, clob0, clob1) \
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__MOV_TO_KR IA64_KR_ ## kr, reg, clob0, clob1
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.macro __ITC_I pred, reg, clob
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.ifc "\reg", "r8"
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(\pred) XEN_HYPER_ITC_I
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.exitm
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.endif
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.ifc "\clob", "r8"
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(\pred) mov r8 = \reg
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;;
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(\pred) XEN_HYPER_ITC_I
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.exitm
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.endif
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(\pred) mov \clob = r8
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(\pred) mov r8 = \reg
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;;
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(\pred) XEN_HYPER_ITC_I
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;;
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(\pred) mov r8 = \clob
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;;
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.endm
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#define ITC_I(pred, reg, clob) __ITC_I pred, reg, clob
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.macro __ITC_D pred, reg, clob
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.ifc "\reg", "r8"
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(\pred) XEN_HYPER_ITC_D
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;;
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.exitm
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.endif
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.ifc "\clob", "r8"
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(\pred) mov r8 = \reg
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;;
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(\pred) XEN_HYPER_ITC_D
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;;
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.exitm
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.endif
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(\pred) mov \clob = r8
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(\pred) mov r8 = \reg
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;;
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(\pred) XEN_HYPER_ITC_D
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;;
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(\pred) mov r8 = \clob
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;;
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.endm
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#define ITC_D(pred, reg, clob) __ITC_D pred, reg, clob
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.macro __ITC_I_AND_D pred_i, pred_d, reg, clob
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.ifc "\reg", "r8"
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(\pred_i)XEN_HYPER_ITC_I
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;;
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(\pred_d)XEN_HYPER_ITC_D
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;;
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.exitm
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.endif
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.ifc "\clob", "r8"
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mov r8 = \reg
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;;
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(\pred_i)XEN_HYPER_ITC_I
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;;
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(\pred_d)XEN_HYPER_ITC_D
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;;
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.exitm
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.endif
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mov \clob = r8
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mov r8 = \reg
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;;
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(\pred_i)XEN_HYPER_ITC_I
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;;
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(\pred_d)XEN_HYPER_ITC_D
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;;
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mov r8 = \clob
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;;
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.endm
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#define ITC_I_AND_D(pred_i, pred_d, reg, clob) \
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__ITC_I_AND_D pred_i, pred_d, reg, clob
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.macro __THASH pred, reg0, reg1, clob
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.ifc "\reg0", "r8"
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(\pred) mov r8 = \reg1
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(\pred) XEN_HYPER_THASH
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.exitm
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.endc
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.ifc "\reg1", "r8"
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(\pred) XEN_HYPER_THASH
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;;
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(\pred) mov \reg0 = r8
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;;
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.exitm
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.endif
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.ifc "\clob", "r8"
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(\pred) mov r8 = \reg1
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(\pred) XEN_HYPER_THASH
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;;
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(\pred) mov \reg0 = r8
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;;
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.exitm
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.endif
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(\pred) mov \clob = r8
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(\pred) mov r8 = \reg1
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(\pred) XEN_HYPER_THASH
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;;
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(\pred) mov \reg0 = r8
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(\pred) mov r8 = \clob
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;;
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.endm
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#define THASH(pred, reg0, reg1, clob) __THASH pred, reg0, reg1, clob
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#define SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(clob0, clob1) \
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mov clob0 = 1; \
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movl clob1 = XSI_PSR_IC; \
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;; \
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st4 [clob1] = clob0 \
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;;
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#define SSM_PSR_IC_AND_SRLZ_D(clob0, clob1) \
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;; \
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srlz.d; \
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mov clob1 = 1; \
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movl clob0 = XSI_PSR_IC; \
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;; \
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st4 [clob0] = clob1
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#define RSM_PSR_IC(clob) \
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movl clob = XSI_PSR_IC; \
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;; \
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st4 [clob] = r0; \
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;;
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/* pred will be clobbered */
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#define MASK_TO_PEND_OFS (-1)
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#define SSM_PSR_I(pred, pred_clob, clob) \
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(pred) movl clob = XSI_PSR_I_ADDR \
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;; \
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(pred) ld8 clob = [clob] \
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;; \
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/* if (pred) vpsr.i = 1 */ \
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/* if (pred) (vcpu->vcpu_info->evtchn_upcall_mask)=0 */ \
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(pred) st1 [clob] = r0, MASK_TO_PEND_OFS \
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;; \
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/* if (vcpu->vcpu_info->evtchn_upcall_pending) */ \
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(pred) ld1 clob = [clob] \
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;; \
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(pred) cmp.ne.unc pred_clob, p0 = clob, r0 \
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;; \
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(pred_clob)XEN_HYPER_SSM_I /* do areal ssm psr.i */
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#define RSM_PSR_I(pred, clob0, clob1) \
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movl clob0 = XSI_PSR_I_ADDR; \
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mov clob1 = 1; \
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;; \
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ld8 clob0 = [clob0]; \
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;; \
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(pred) st1 [clob0] = clob1
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#define RSM_PSR_I_IC(clob0, clob1, clob2) \
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movl clob0 = XSI_PSR_I_ADDR; \
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movl clob1 = XSI_PSR_IC; \
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;; \
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ld8 clob0 = [clob0]; \
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mov clob2 = 1; \
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;; \
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/* note: clears both vpsr.i and vpsr.ic! */ \
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st1 [clob0] = clob2; \
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st4 [clob1] = r0; \
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;;
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#define RSM_PSR_DT \
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XEN_HYPER_RSM_PSR_DT
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#define SSM_PSR_DT_AND_SRLZ_I \
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XEN_HYPER_SSM_PSR_DT
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#define BSW_0(clob0, clob1, clob2) \
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;; \
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/* r16-r31 all now hold bank1 values */ \
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mov clob2 = ar.unat; \
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movl clob0 = XSI_BANK1_R16; \
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movl clob1 = XSI_BANK1_R16 + 8; \
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;; \
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.mem.offset 0, 0; st8.spill [clob0] = r16, 16; \
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.mem.offset 8, 0; st8.spill [clob1] = r17, 16; \
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;; \
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.mem.offset 0, 0; st8.spill [clob0] = r18, 16; \
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.mem.offset 8, 0; st8.spill [clob1] = r19, 16; \
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;; \
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.mem.offset 0, 0; st8.spill [clob0] = r20, 16; \
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.mem.offset 8, 0; st8.spill [clob1] = r21, 16; \
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;; \
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.mem.offset 0, 0; st8.spill [clob0] = r22, 16; \
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.mem.offset 8, 0; st8.spill [clob1] = r23, 16; \
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;; \
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.mem.offset 0, 0; st8.spill [clob0] = r24, 16; \
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.mem.offset 8, 0; st8.spill [clob1] = r25, 16; \
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;; \
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.mem.offset 0, 0; st8.spill [clob0] = r26, 16; \
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.mem.offset 8, 0; st8.spill [clob1] = r27, 16; \
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;; \
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.mem.offset 0, 0; st8.spill [clob0] = r28, 16; \
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.mem.offset 8, 0; st8.spill [clob1] = r29, 16; \
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;; \
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.mem.offset 0, 0; st8.spill [clob0] = r30, 16; \
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.mem.offset 8, 0; st8.spill [clob1] = r31, 16; \
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;; \
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mov clob1 = ar.unat; \
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movl clob0 = XSI_B1NAT; \
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;; \
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st8 [clob0] = clob1; \
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mov ar.unat = clob2; \
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movl clob0 = XSI_BANKNUM; \
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;; \
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st4 [clob0] = r0
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/* FIXME: THIS CODE IS NOT NaT SAFE! */
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#define XEN_BSW_1(clob) \
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mov clob = ar.unat; \
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movl r30 = XSI_B1NAT; \
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;; \
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ld8 r30 = [r30]; \
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mov r31 = 1; \
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;; \
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mov ar.unat = r30; \
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movl r30 = XSI_BANKNUM; \
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;; \
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st4 [r30] = r31; \
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movl r30 = XSI_BANK1_R16; \
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movl r31 = XSI_BANK1_R16+8; \
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;; \
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ld8.fill r16 = [r30], 16; \
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ld8.fill r17 = [r31], 16; \
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;; \
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ld8.fill r18 = [r30], 16; \
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ld8.fill r19 = [r31], 16; \
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;; \
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ld8.fill r20 = [r30], 16; \
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ld8.fill r21 = [r31], 16; \
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;; \
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ld8.fill r22 = [r30], 16; \
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ld8.fill r23 = [r31], 16; \
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;; \
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ld8.fill r24 = [r30], 16; \
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ld8.fill r25 = [r31], 16; \
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;; \
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ld8.fill r26 = [r30], 16; \
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ld8.fill r27 = [r31], 16; \
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;; \
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ld8.fill r28 = [r30], 16; \
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ld8.fill r29 = [r31], 16; \
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;; \
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ld8.fill r30 = [r30]; \
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ld8.fill r31 = [r31]; \
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;; \
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mov ar.unat = clob
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#define BSW_1(clob0, clob1) XEN_BSW_1(clob1)
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#define COVER \
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XEN_HYPER_COVER
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#define RFI \
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XEN_HYPER_RFI; \
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dv_serialize_data
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