Merge branch 'fixes' into next
This commit is contained in:
Kishon Vijay Abraham I
Коммит
d664817452
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@ -111,6 +111,8 @@
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#define MVEBU_COMPHY_CONF6_40B BIT(18)
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#define MVEBU_COMPHY_SELECTOR 0x1140
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#define MVEBU_COMPHY_SELECTOR_PHY(n) ((n) * 0x4)
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#define MVEBU_COMPHY_PIPE_SELECTOR 0x1144
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#define MVEBU_COMPHY_PIPE_SELECTOR_PIPE(n) ((n) * 0x4)
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#define MVEBU_COMPHY_LANES 6
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#define MVEBU_COMPHY_PORTS 3
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@ -468,13 +470,17 @@ static int mvebu_comphy_power_on(struct phy *phy)
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{
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struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
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struct mvebu_comphy_priv *priv = lane->priv;
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int ret;
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u32 mux, val;
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int ret, mux;
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u32 val;
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mux = mvebu_comphy_get_mux(lane->id, lane->port, lane->mode);
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if (mux < 0)
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return -ENOTSUPP;
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regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);
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val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
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regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);
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regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);
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val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
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val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id);
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@ -526,6 +532,10 @@ static int mvebu_comphy_power_off(struct phy *phy)
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val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
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regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);
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regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);
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val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
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regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);
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return 0;
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}
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@ -576,8 +586,8 @@ static int mvebu_comphy_probe(struct platform_device *pdev)
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return PTR_ERR(priv->regmap);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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priv->base = devm_ioremap_resource(&pdev->dev, res);
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if (!priv->base)
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return -ENOMEM;
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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for_each_available_child_of_node(pdev->dev.of_node, child) {
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struct mvebu_comphy_lane *lane;
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@ -27,6 +27,7 @@
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/* banks shared by multiple phys */
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#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */
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#define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */
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#define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */
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/* u2 phy bank */
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#define SSUSB_SIFSLV_V1_U2PHY_COM 0x000
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/* u3/pcie/sata phy banks */
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@ -762,7 +763,7 @@ static void phy_v1_banks_init(struct mtk_tphy *tphy,
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case PHY_TYPE_USB3:
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case PHY_TYPE_PCIE:
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u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC;
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u3_banks->chip = NULL;
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u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP;
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u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD;
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u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA;
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break;
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@ -443,14 +443,34 @@ static inline int property_enable(struct rockchip_typec_phy *tcphy,
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return regmap_write(tcphy->grf_regs, reg->offset, val | mask);
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}
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static void tcphy_dp_aux_set_flip(struct rockchip_typec_phy *tcphy)
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{
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u16 tx_ana_ctrl_reg_1;
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/*
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* Select the polarity of the xcvr:
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* 1, Reverses the polarity (If TYPEC, Pulls ups aux_p and pull
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* down aux_m)
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* 0, Normal polarity (if TYPEC, pulls up aux_m and pulls down
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* aux_p)
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*/
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tx_ana_ctrl_reg_1 = readl(tcphy->base + TX_ANA_CTRL_REG_1);
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if (!tcphy->flip)
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tx_ana_ctrl_reg_1 |= BIT(12);
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else
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tx_ana_ctrl_reg_1 &= ~BIT(12);
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writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
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}
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static void tcphy_dp_aux_calibration(struct rockchip_typec_phy *tcphy)
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{
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u16 tx_ana_ctrl_reg_1;
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u16 rdata, rdata2, val;
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/* disable txda_cal_latch_en for rewrite the calibration values */
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rdata = readl(tcphy->base + TX_ANA_CTRL_REG_1);
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val = rdata & 0xdfff;
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writel(val, tcphy->base + TX_ANA_CTRL_REG_1);
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tx_ana_ctrl_reg_1 = readl(tcphy->base + TX_ANA_CTRL_REG_1);
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tx_ana_ctrl_reg_1 &= ~BIT(13);
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writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
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/*
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* read a resistor calibration code from CMN_TXPUCAL_CTRL[6:0] and
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@ -472,9 +492,8 @@ static void tcphy_dp_aux_calibration(struct rockchip_typec_phy *tcphy)
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* Activate this signal for 1 clock cycle to sample new calibration
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* values.
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*/
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rdata = readl(tcphy->base + TX_ANA_CTRL_REG_1);
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val = rdata | 0x2000;
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writel(val, tcphy->base + TX_ANA_CTRL_REG_1);
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tx_ana_ctrl_reg_1 |= BIT(13);
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writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
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usleep_range(150, 200);
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/* set TX Voltage Level and TX Deemphasis to 0 */
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@ -482,8 +501,10 @@ static void tcphy_dp_aux_calibration(struct rockchip_typec_phy *tcphy)
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/* re-enable decap */
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writel(0x100, tcphy->base + TX_ANA_CTRL_REG_2);
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writel(0x300, tcphy->base + TX_ANA_CTRL_REG_2);
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writel(0x2008, tcphy->base + TX_ANA_CTRL_REG_1);
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writel(0x2018, tcphy->base + TX_ANA_CTRL_REG_1);
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tx_ana_ctrl_reg_1 |= BIT(3);
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writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
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tx_ana_ctrl_reg_1 |= BIT(4);
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writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
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writel(0, tcphy->base + TX_ANA_CTRL_REG_5);
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@ -494,8 +515,10 @@ static void tcphy_dp_aux_calibration(struct rockchip_typec_phy *tcphy)
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writel(0x1001, tcphy->base + TX_ANA_CTRL_REG_4);
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/* re-enables Bandgap reference for LDO */
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writel(0x2098, tcphy->base + TX_ANA_CTRL_REG_1);
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writel(0x2198, tcphy->base + TX_ANA_CTRL_REG_1);
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tx_ana_ctrl_reg_1 |= BIT(7);
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writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
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tx_ana_ctrl_reg_1 |= BIT(8);
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writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
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/*
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* re-enables the transmitter pre-driver, driver data selection MUX,
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@ -505,27 +528,26 @@ static void tcphy_dp_aux_calibration(struct rockchip_typec_phy *tcphy)
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writel(0x303, tcphy->base + TX_ANA_CTRL_REG_2);
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/*
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* BIT 12: Controls auxda_polarity, which selects the polarity of the
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* xcvr:
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* 1, Reverses the polarity (If TYPEC, Pulls ups aux_p and pull
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* down aux_m)
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* 0, Normal polarity (if TYPE_C, pulls up aux_m and pulls down
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* aux_p)
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* Do some magic undocumented stuff, some of which appears to
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* undo the "re-enables Bandgap reference for LDO" above.
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*/
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val = 0xa078;
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if (!tcphy->flip)
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val |= BIT(12);
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writel(val, tcphy->base + TX_ANA_CTRL_REG_1);
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tx_ana_ctrl_reg_1 |= BIT(15);
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tx_ana_ctrl_reg_1 &= ~BIT(8);
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tx_ana_ctrl_reg_1 &= ~BIT(7);
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tx_ana_ctrl_reg_1 |= BIT(6);
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tx_ana_ctrl_reg_1 |= BIT(5);
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writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
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writel(0, tcphy->base + TX_ANA_CTRL_REG_3);
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writel(0, tcphy->base + TX_ANA_CTRL_REG_4);
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writel(0, tcphy->base + TX_ANA_CTRL_REG_5);
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/*
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* Controls low_power_swing_en, set the voltage swing of the driver
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* to 400mv. The values below are peak to peak (differential) values.
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* Controls low_power_swing_en, don't set the voltage swing of the
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* driver to 400mv. The values below are peak to peak (differential)
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* values.
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*/
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writel(4, tcphy->base + TXDA_COEFF_CALC_CTRL);
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writel(0, tcphy->base + TXDA_COEFF_CALC_CTRL);
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writel(0, tcphy->base + TXDA_CYA_AUXDA_CYA);
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/* Controls tx_high_z_tm_en */
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@ -555,6 +577,7 @@ static int tcphy_phy_init(struct rockchip_typec_phy *tcphy, u8 mode)
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reset_control_deassert(tcphy->tcphy_rst);
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property_enable(tcphy, &cfg->typec_conn_dir, tcphy->flip);
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tcphy_dp_aux_set_flip(tcphy);
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tcphy_cfg_24m(tcphy);
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@ -685,8 +708,11 @@ static int rockchip_usb3_phy_power_on(struct phy *phy)
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if (tcphy->mode == new_mode)
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goto unlock_ret;
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if (tcphy->mode == MODE_DISCONNECT)
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tcphy_phy_init(tcphy, new_mode);
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if (tcphy->mode == MODE_DISCONNECT) {
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ret = tcphy_phy_init(tcphy, new_mode);
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if (ret)
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goto unlock_ret;
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}
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/* wait TCPHY for pipe ready */
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for (timeout = 0; timeout < 100; timeout++) {
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@ -760,10 +786,12 @@ static int rockchip_dp_phy_power_on(struct phy *phy)
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*/
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if (new_mode == MODE_DFP_DP && tcphy->mode != MODE_DISCONNECT) {
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tcphy_phy_deinit(tcphy);
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tcphy_phy_init(tcphy, new_mode);
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ret = tcphy_phy_init(tcphy, new_mode);
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} else if (tcphy->mode == MODE_DISCONNECT) {
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tcphy_phy_init(tcphy, new_mode);
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ret = tcphy_phy_init(tcphy, new_mode);
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}
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if (ret)
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goto unlock_ret;
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ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL,
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val, val & DP_MODE_A2, 1000,
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@ -454,6 +454,8 @@ tegra_xusb_find_port_node(struct tegra_xusb_padctl *padctl, const char *type,
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char *name;
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name = kasprintf(GFP_KERNEL, "%s-%u", type, index);
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if (!name)
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return ERR_PTR(-ENOMEM);
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np = of_find_node_by_name(np, name);
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kfree(name);
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}
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