csiostor: Header file modifications for chip support and bug fixes.
This patch defines the common operations to support multiple chips. It includes common header file modifications to support the current chips (T4 and T5). It also includes the following bug fixes: - reconfirms the rnode state after an implicit logo. - corrects the stats array size. - sets up and checks flags correctly when coming up as master and finding the card initialized Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Arvind Bhushan <arvindb@chelsio.com> Signed-off-by: Naresh Kumar Inna <naresh@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Arvind Bhushan
David S. Miller
Родитель
4a22edb593
Коммит
d69630e8a4
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@ -0,0 +1,175 @@
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/*
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* This file is part of the Chelsio FCoE driver for Linux.
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*
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* Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __CSIO_HW_CHIP_H__
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#define __CSIO_HW_CHIP_H__
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#include "csio_defs.h"
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/* FCoE device IDs for T4 */
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#define CSIO_DEVID_T440DBG_FCOE 0x4600
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#define CSIO_DEVID_T420CR_FCOE 0x4601
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#define CSIO_DEVID_T422CR_FCOE 0x4602
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#define CSIO_DEVID_T440CR_FCOE 0x4603
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#define CSIO_DEVID_T420BCH_FCOE 0x4604
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#define CSIO_DEVID_T440BCH_FCOE 0x4605
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#define CSIO_DEVID_T440CH_FCOE 0x4606
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#define CSIO_DEVID_T420SO_FCOE 0x4607
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#define CSIO_DEVID_T420CX_FCOE 0x4608
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#define CSIO_DEVID_T420BT_FCOE 0x4609
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#define CSIO_DEVID_T404BT_FCOE 0x460A
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#define CSIO_DEVID_B420_FCOE 0x460B
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#define CSIO_DEVID_B404_FCOE 0x460C
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#define CSIO_DEVID_T480CR_FCOE 0x460D
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#define CSIO_DEVID_T440LPCR_FCOE 0x460E
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#define CSIO_DEVID_AMSTERDAM_T4_FCOE 0x460F
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#define CSIO_DEVID_HUAWEI_T480_FCOE 0x4680
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#define CSIO_DEVID_HUAWEI_T440_FCOE 0x4681
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#define CSIO_DEVID_HUAWEI_STG310_FCOE 0x4682
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#define CSIO_DEVID_ACROMAG_XMC_XAUI 0x4683
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#define CSIO_DEVID_ACROMAG_XMC_SFP_FCOE 0x4684
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#define CSIO_DEVID_QUANTA_MEZZ_SFP_FCOE 0x4685
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#define CSIO_DEVID_HUAWEI_10GT_FCOE 0x4686
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#define CSIO_DEVID_HUAWEI_T440_TOE_FCOE 0x4687
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/* FCoE device IDs for T5 */
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#define CSIO_DEVID_T580DBG_FCOE 0x5600
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#define CSIO_DEVID_T520CR_FCOE 0x5601
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#define CSIO_DEVID_T522CR_FCOE 0x5602
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#define CSIO_DEVID_T540CR_FCOE 0x5603
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#define CSIO_DEVID_T520BCH_FCOE 0x5604
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#define CSIO_DEVID_T540BCH_FCOE 0x5605
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#define CSIO_DEVID_T540CH_FCOE 0x5606
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#define CSIO_DEVID_T520SO_FCOE 0x5607
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#define CSIO_DEVID_T520CX_FCOE 0x5608
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#define CSIO_DEVID_T520BT_FCOE 0x5609
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#define CSIO_DEVID_T504BT_FCOE 0x560A
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#define CSIO_DEVID_B520_FCOE 0x560B
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#define CSIO_DEVID_B504_FCOE 0x560C
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#define CSIO_DEVID_T580CR2_FCOE 0x560D
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#define CSIO_DEVID_T540LPCR_FCOE 0x560E
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#define CSIO_DEVID_AMSTERDAM_T5_FCOE 0x560F
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#define CSIO_DEVID_T580LPCR_FCOE 0x5610
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#define CSIO_DEVID_T520LLCR_FCOE 0x5611
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#define CSIO_DEVID_T560CR_FCOE 0x5612
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#define CSIO_DEVID_T580CR_FCOE 0x5613
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/* Define MACRO values */
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#define CSIO_HW_T4 0x4000
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#define CSIO_T4_FCOE_ASIC 0x4600
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#define CSIO_HW_T5 0x5000
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#define CSIO_T5_FCOE_ASIC 0x5600
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#define CSIO_HW_CHIP_MASK 0xF000
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#define T4_REGMAP_SIZE (160 * 1024)
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#define T5_REGMAP_SIZE (332 * 1024)
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#define FW_FNAME_T4 "cxgb4/t4fw.bin"
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#define FW_FNAME_T5 "cxgb4/t5fw.bin"
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#define FW_CFG_NAME_T4 "cxgb4/t4-config.txt"
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#define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
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/* Define static functions */
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static inline int csio_is_t4(uint16_t chip)
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{
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return (chip == CSIO_HW_T4);
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}
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static inline int csio_is_t5(uint16_t chip)
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{
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return (chip == CSIO_HW_T5);
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}
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/* Define MACRO DEFINITIONS */
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#define CSIO_DEVICE(devid, idx) \
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{ PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
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#define CSIO_HW_PIDX(hw, index) \
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(csio_is_t4(hw->chip_id) ? (PIDX(index)) : \
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(PIDX_T5(index) | DBTYPE(1U)))
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#define CSIO_HW_LP_INT_THRESH(hw, val) \
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(csio_is_t4(hw->chip_id) ? (LP_INT_THRESH(val)) : \
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(V_LP_INT_THRESH_T5(val)))
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#define CSIO_HW_M_LP_INT_THRESH(hw) \
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(csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_MASK) : (M_LP_INT_THRESH_T5))
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#define CSIO_MAC_INT_CAUSE_REG(hw, port) \
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(csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE)) : \
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(T5_PORT_REG(port, MAC_PORT_INT_CAUSE)))
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#define FW_VERSION_MAJOR(hw) (csio_is_t4(hw->chip_id) ? 1 : 0)
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#define FW_VERSION_MINOR(hw) (csio_is_t4(hw->chip_id) ? 2 : 0)
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#define FW_VERSION_MICRO(hw) (csio_is_t4(hw->chip_id) ? 8 : 0)
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#define CSIO_FW_FNAME(hw) \
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(csio_is_t4(hw->chip_id) ? FW_FNAME_T4 : FW_FNAME_T5)
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#define CSIO_CF_FNAME(hw) \
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(csio_is_t4(hw->chip_id) ? FW_CFG_NAME_T4 : FW_CFG_NAME_T5)
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/* Declare ENUMS */
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enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
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enum {
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MEMWIN_APERTURE = 2048,
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MEMWIN_BASE = 0x1b800,
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MEMWIN_CSIOSTOR = 6, /* PCI-e Memory Window access */
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};
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/* Slow path handlers */
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struct intr_info {
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unsigned int mask; /* bits to check in interrupt status */
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const char *msg; /* message to print or NULL */
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short stat_idx; /* stat counter to increment or -1 */
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unsigned short fatal; /* whether the condition reported is fatal */
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};
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/* T4/T5 Chip specific ops */
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struct csio_hw;
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struct csio_hw_chip_ops {
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int (*chip_set_mem_win)(struct csio_hw *, uint32_t);
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void (*chip_pcie_intr_handler)(struct csio_hw *);
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uint32_t (*chip_flash_cfg_addr)(struct csio_hw *);
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int (*chip_mc_read)(struct csio_hw *, int, uint32_t,
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__be32 *, uint64_t *);
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int (*chip_edc_read)(struct csio_hw *, int, uint32_t,
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__be32 *, uint64_t *);
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int (*chip_memory_rw)(struct csio_hw *, u32, int, u32,
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u32, uint32_t *, int);
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void (*chip_dfs_create_ext_mem)(struct csio_hw *);
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};
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extern struct csio_hw_chip_ops t4_ops;
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extern struct csio_hw_chip_ops t5_ops;
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#endif /* #ifndef __CSIO_HW_CHIP_H__ */
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@ -114,7 +114,7 @@ struct csio_lnode_stats {
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uint32_t n_rnode_match; /* matched rnode */
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uint32_t n_dev_loss_tmo; /* Device loss timeout */
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uint32_t n_fdmi_err; /* fdmi err */
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uint32_t n_evt_fw[RSCN_DEV_LOST]; /* fw events */
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uint32_t n_evt_fw[PROTO_ERR_IMPL_LOGO]; /* fw events */
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enum csio_ln_ev n_evt_sm[CSIO_LNE_MAX_EVENT]; /* State m/c events */
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uint32_t n_rnode_alloc; /* rnode allocated */
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uint32_t n_rnode_free; /* rnode freed */
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@ -302,7 +302,7 @@ csio_confirm_rnode(struct csio_lnode *ln, uint32_t rdev_flowid,
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{
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uint8_t rport_type;
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struct csio_rnode *rn, *match_rn;
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uint32_t vnp_flowid;
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uint32_t vnp_flowid = 0;
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__be32 *port_id;
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port_id = (__be32 *)&rdevp->r_id[0];
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@ -350,6 +350,14 @@ csio_confirm_rnode(struct csio_lnode *ln, uint32_t rdev_flowid,
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* Else, go ahead and alloc a new rnode.
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*/
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if (!memcmp(csio_rn_wwpn(match_rn), rdevp->wwpn, 8)) {
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if (rn == match_rn)
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goto found_rnode;
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csio_ln_dbg(ln,
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"nport_id:x%x and wwpn:%llx"
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" match for ssni:x%x\n",
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rn->nport_id,
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wwn_to_u64(rdevp->wwpn),
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rdev_flowid);
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if (csio_is_rnode_ready(rn)) {
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csio_ln_warn(ln,
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"rnode is already"
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@ -63,7 +63,7 @@ struct csio_rnode_stats {
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uint32_t n_err_nomem; /* error nomem */
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uint32_t n_evt_unexp; /* unexpected event */
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uint32_t n_evt_drop; /* unexpected event */
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uint32_t n_evt_fw[RSCN_DEV_LOST]; /* fw events */
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uint32_t n_evt_fw[PROTO_ERR_IMPL_LOGO]; /* fw events */
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enum csio_rn_ev n_evt_sm[CSIO_RNFE_MAX_EVENT]; /* State m/c events */
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uint32_t n_lun_rst; /* Number of resets of
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* of LUNs under this
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@ -1331,14 +1331,21 @@ csio_wr_fixup_host_params(struct csio_hw *hw)
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/* FL BUFFER SIZE#0 is Page size i,e already aligned to cache line */
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csio_wr_reg32(hw, PAGE_SIZE, SGE_FL_BUFFER_SIZE0);
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csio_wr_reg32(hw,
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(csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE2) +
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sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1),
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SGE_FL_BUFFER_SIZE2);
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csio_wr_reg32(hw,
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(csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE3) +
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sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1),
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SGE_FL_BUFFER_SIZE3);
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/*
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* If using hard params, the following will get set correctly
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* in csio_wr_set_sge().
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*/
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if (hw->flags & CSIO_HWF_USING_SOFT_PARAMS) {
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csio_wr_reg32(hw,
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(csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE2) +
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sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1),
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SGE_FL_BUFFER_SIZE2);
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csio_wr_reg32(hw,
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(csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE3) +
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sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1),
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SGE_FL_BUFFER_SIZE3);
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}
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csio_wr_reg32(hw, HPZ0(PAGE_SHIFT - 12), ULP_RX_TDDP_PSZ);
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@ -1470,8 +1477,10 @@ csio_wr_set_sge(struct csio_hw *hw)
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/* SGE_FL_BUFFER_SIZE0 is set up by csio_wr_fixup_host_params(). */
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CSIO_SET_FLBUF_SIZE(hw, 1, CSIO_SGE_FLBUF_SIZE1);
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CSIO_SET_FLBUF_SIZE(hw, 2, CSIO_SGE_FLBUF_SIZE2);
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CSIO_SET_FLBUF_SIZE(hw, 3, CSIO_SGE_FLBUF_SIZE3);
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csio_wr_reg32(hw, (CSIO_SGE_FLBUF_SIZE2 + sge->csio_fl_align - 1)
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& ~(sge->csio_fl_align - 1), SGE_FL_BUFFER_SIZE2);
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csio_wr_reg32(hw, (CSIO_SGE_FLBUF_SIZE3 + sge->csio_fl_align - 1)
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& ~(sge->csio_fl_align - 1), SGE_FL_BUFFER_SIZE3);
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CSIO_SET_FLBUF_SIZE(hw, 4, CSIO_SGE_FLBUF_SIZE4);
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CSIO_SET_FLBUF_SIZE(hw, 5, CSIO_SGE_FLBUF_SIZE5);
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CSIO_SET_FLBUF_SIZE(hw, 6, CSIO_SGE_FLBUF_SIZE6);
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@ -1522,22 +1531,24 @@ void
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csio_wr_sge_init(struct csio_hw *hw)
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{
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/*
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* If we are master:
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* If we are master and chip is not initialized:
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* - If we plan to use the config file, we need to fixup some
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* host specific registers, and read the rest of the SGE
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* configuration.
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* - If we dont plan to use the config file, we need to initialize
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* SGE entirely, including fixing the host specific registers.
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* If we are master and chip is initialized, just read and work off of
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* the already initialized SGE values.
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* If we arent the master, we are only allowed to read and work off of
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* the already initialized SGE values.
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*
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* Therefore, before calling this function, we assume that the master-
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* ship of the card, and whether to use config file or not, have
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* already been decided. In other words, CSIO_HWF_USING_SOFT_PARAMS and
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* CSIO_HWF_MASTER should be set/unset.
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* ship of the card, state and whether to use config file or not, have
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* already been decided.
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*/
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if (csio_is_hw_master(hw)) {
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csio_wr_fixup_host_params(hw);
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if (hw->fw_state != CSIO_DEV_STATE_INIT)
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csio_wr_fixup_host_params(hw);
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if (hw->flags & CSIO_HWF_USING_SOFT_PARAMS)
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csio_wr_get_sge(hw);
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