[POWERPC] spufs: rework class 0 and 1 interrupt handling
Based on original patches from Arnd Bergmann <arnd.bergman@de.ibm.com>; and Luke Browning <lukebr@linux.vnet.ibm.com> Currently, spu contexts need to be loaded to the SPU in order to take class 0 and class 1 exceptions. This change makes the actual interrupt-handlers much simpler (ie, set the exception information in the context save area), and defers the handling code to the spufs_handle_class[01] functions, called from spufs_run_spu. This should improve the concurrency of the spu scheduling leading to greater SPU utilization when SPUs are overcommited. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Jeremy Kerr
Paul Mackerras
Родитель
8af30675c3
Коммит
d6ad39bc53
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@ -132,27 +132,6 @@ int spu_64k_pages_available(void)
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}
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EXPORT_SYMBOL_GPL(spu_64k_pages_available);
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static int __spu_trap_invalid_dma(struct spu *spu)
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{
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pr_debug("%s\n", __FUNCTION__);
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spu->dma_callback(spu, SPE_EVENT_INVALID_DMA);
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return 0;
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}
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static int __spu_trap_dma_align(struct spu *spu)
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{
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pr_debug("%s\n", __FUNCTION__);
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spu->dma_callback(spu, SPE_EVENT_DMA_ALIGNMENT);
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return 0;
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}
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static int __spu_trap_error(struct spu *spu)
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{
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pr_debug("%s\n", __FUNCTION__);
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spu->dma_callback(spu, SPE_EVENT_SPE_ERROR);
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return 0;
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}
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static void spu_restart_dma(struct spu *spu)
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{
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struct spu_priv2 __iomem *priv2 = spu->priv2;
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@ -252,10 +231,12 @@ static int __spu_trap_data_map(struct spu *spu, unsigned long ea, u64 dsisr)
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return 1;
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}
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spu->class_0_pending = 0;
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spu->dar = ea;
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spu->dsisr = dsisr;
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mb();
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spu->stop_callback(spu);
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return 0;
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}
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@ -335,12 +316,13 @@ spu_irq_class_0(int irq, void *data)
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spu = data;
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mask = spu_int_mask_get(spu, 0);
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stat = spu_int_stat_get(spu, 0);
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stat &= mask;
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spin_lock(&spu->register_lock);
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mask = spu_int_mask_get(spu, 0);
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stat = spu_int_stat_get(spu, 0) & mask;
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spu->class_0_pending |= stat;
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spu->dsisr = spu_mfc_dsisr_get(spu);
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spu->dar = spu_mfc_dar_get(spu);
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spin_unlock(&spu->register_lock);
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spu->stop_callback(spu);
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@ -350,31 +332,6 @@ spu_irq_class_0(int irq, void *data)
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return IRQ_HANDLED;
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}
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int
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spu_irq_class_0_bottom(struct spu *spu)
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{
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unsigned long flags;
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unsigned long stat;
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spin_lock_irqsave(&spu->register_lock, flags);
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stat = spu->class_0_pending;
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spu->class_0_pending = 0;
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if (stat & CLASS0_DMA_ALIGNMENT_INTR)
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__spu_trap_dma_align(spu);
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if (stat & CLASS0_INVALID_DMA_COMMAND_INTR)
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__spu_trap_invalid_dma(spu);
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if (stat & CLASS0_SPU_ERROR_INTR)
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__spu_trap_error(spu);
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spin_unlock_irqrestore(&spu->register_lock, flags);
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return (stat & CLASS0_INTR_MASK) ? -EIO : 0;
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}
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EXPORT_SYMBOL_GPL(spu_irq_class_0_bottom);
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static irqreturn_t
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spu_irq_class_1(int irq, void *data)
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{
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@ -28,46 +28,69 @@
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#include "spufs.h"
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static void spufs_handle_dma_error(struct spu_context *ctx,
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/**
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* Handle an SPE event, depending on context SPU_CREATE_EVENTS_ENABLED flag.
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*
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* If the context was created with events, we just set the return event.
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* Otherwise, send an appropriate signal to the process.
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*/
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static void spufs_handle_event(struct spu_context *ctx,
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unsigned long ea, int type)
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{
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siginfo_t info;
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if (ctx->flags & SPU_CREATE_EVENTS_ENABLED) {
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ctx->event_return |= type;
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wake_up_all(&ctx->stop_wq);
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} else {
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siginfo_t info;
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memset(&info, 0, sizeof(info));
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switch (type) {
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case SPE_EVENT_INVALID_DMA:
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info.si_signo = SIGBUS;
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info.si_code = BUS_OBJERR;
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break;
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case SPE_EVENT_SPE_DATA_STORAGE:
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info.si_signo = SIGBUS;
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info.si_addr = (void __user *)ea;
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info.si_code = BUS_ADRERR;
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break;
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case SPE_EVENT_DMA_ALIGNMENT:
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info.si_signo = SIGBUS;
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/* DAR isn't set for an alignment fault :( */
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info.si_code = BUS_ADRALN;
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break;
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case SPE_EVENT_SPE_ERROR:
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info.si_signo = SIGILL;
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info.si_addr = (void __user *)(unsigned long)
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ctx->ops->npc_read(ctx) - 4;
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info.si_code = ILL_ILLOPC;
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break;
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}
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if (info.si_signo)
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force_sig_info(info.si_signo, &info, current);
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return;
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}
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memset(&info, 0, sizeof(info));
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switch (type) {
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case SPE_EVENT_INVALID_DMA:
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info.si_signo = SIGBUS;
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info.si_code = BUS_OBJERR;
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break;
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case SPE_EVENT_SPE_DATA_STORAGE:
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info.si_signo = SIGBUS;
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info.si_addr = (void __user *)ea;
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info.si_code = BUS_ADRERR;
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break;
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case SPE_EVENT_DMA_ALIGNMENT:
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info.si_signo = SIGBUS;
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/* DAR isn't set for an alignment fault :( */
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info.si_code = BUS_ADRALN;
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break;
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case SPE_EVENT_SPE_ERROR:
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info.si_signo = SIGILL;
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info.si_addr = (void __user *)(unsigned long)
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ctx->ops->npc_read(ctx) - 4;
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info.si_code = ILL_ILLOPC;
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break;
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}
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if (info.si_signo)
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force_sig_info(info.si_signo, &info, current);
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}
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void spufs_dma_callback(struct spu *spu, int type)
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int spufs_handle_class0(struct spu_context *ctx)
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{
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spufs_handle_dma_error(spu->ctx, spu->dar, type);
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unsigned long stat = ctx->csa.class_0_pending & CLASS0_INTR_MASK;
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if (likely(!stat))
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return 0;
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if (stat & CLASS0_DMA_ALIGNMENT_INTR)
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spufs_handle_event(ctx, ctx->csa.dar, SPE_EVENT_DMA_ALIGNMENT);
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if (stat & CLASS0_INVALID_DMA_COMMAND_INTR)
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spufs_handle_event(ctx, ctx->csa.dar, SPE_EVENT_INVALID_DMA);
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if (stat & CLASS0_SPU_ERROR_INTR)
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spufs_handle_event(ctx, ctx->csa.dar, SPE_EVENT_SPE_ERROR);
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return -EIO;
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}
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/*
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@ -95,16 +118,8 @@ int spufs_handle_class1(struct spu_context *ctx)
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* in time, we can still expect to get the same fault
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* the immediately after the context restore.
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*/
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if (ctx->state == SPU_STATE_RUNNABLE) {
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ea = ctx->spu->dar;
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dsisr = ctx->spu->dsisr;
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ctx->spu->dar= ctx->spu->dsisr = 0;
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} else {
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ea = ctx->csa.priv1.mfc_dar_RW;
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dsisr = ctx->csa.priv1.mfc_dsisr_RW;
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ctx->csa.priv1.mfc_dar_RW = 0;
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ctx->csa.priv1.mfc_dsisr_RW = 0;
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}
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ea = ctx->csa.dar;
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dsisr = ctx->csa.dsisr;
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if (!(dsisr & (MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED)))
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return 0;
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@ -132,6 +147,14 @@ int spufs_handle_class1(struct spu_context *ctx)
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ret = spu_handle_mm_fault(current->mm, ea, dsisr, &flt);
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spu_acquire(ctx);
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/*
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* Clear dsisr under ctxt lock after handling the fault, so that
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* time slicing will not preempt the context while the page fault
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* handler is running. Context switch code removes mappings.
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*/
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ctx->csa.dar = ctx->csa.dsisr = 0;
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/*
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* If we handled the fault successfully and are in runnable
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* state, restart the DMA.
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@ -152,7 +175,7 @@ int spufs_handle_class1(struct spu_context *ctx)
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if (ctx->spu)
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ctx->ops->restart_dma(ctx);
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} else
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spufs_handle_dma_error(ctx, ea, SPE_EVENT_SPE_DATA_STORAGE);
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spufs_handle_event(ctx, ea, SPE_EVENT_SPE_DATA_STORAGE);
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spuctx_switch_state(ctx, SPU_UTIL_SYSTEM);
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return ret;
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@ -15,7 +15,30 @@ void spufs_stop_callback(struct spu *spu)
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{
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struct spu_context *ctx = spu->ctx;
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wake_up_all(&ctx->stop_wq);
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/*
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* It should be impossible to preempt a context while an exception
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* is being processed, since the context switch code is specially
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* coded to deal with interrupts ... But, just in case, sanity check
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* the context pointer. It is OK to return doing nothing since
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* the exception will be regenerated when the context is resumed.
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*/
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if (ctx) {
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/* Copy exception arguments into module specific structure */
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ctx->csa.class_0_pending = spu->class_0_pending;
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ctx->csa.dsisr = spu->dsisr;
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ctx->csa.dar = spu->dar;
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/* ensure that the exception status has hit memory before a
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* thread waiting on the context's stop queue is woken */
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smp_wmb();
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wake_up_all(&ctx->stop_wq);
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}
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/* Clear callback arguments from spu structure */
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spu->class_0_pending = 0;
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spu->dsisr = 0;
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spu->dar = 0;
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}
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static inline int spu_stopped(struct spu_context *ctx, u32 *stat)
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@ -29,9 +52,9 @@ static inline int spu_stopped(struct spu_context *ctx, u32 *stat)
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if (ctx->state != SPU_STATE_RUNNABLE ||
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test_bit(SPU_SCHED_NOTIFY_ACTIVE, &ctx->sched_flags))
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return 1;
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pte_fault = spu->dsisr &
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pte_fault = ctx->csa.dsisr &
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(MFC_DSISR_PTE_NOT_FOUND | MFC_DSISR_ACCESS_DENIED);
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return (!(*stat & SPU_STATUS_RUNNING) || pte_fault || spu->class_0_pending) ?
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return (!(*stat & SPU_STATUS_RUNNING) || pte_fault || ctx->csa.class_0_pending) ?
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1 : 0;
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}
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@ -287,18 +310,6 @@ static int spu_process_callback(struct spu_context *ctx)
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return ret;
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}
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static inline int spu_process_events(struct spu_context *ctx)
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{
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struct spu *spu = ctx->spu;
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int ret = 0;
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if (spu->class_0_pending)
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ret = spu_irq_class_0_bottom(spu);
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if (!ret && signal_pending(current))
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ret = -ERESTARTSYS;
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return ret;
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}
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long spufs_run_spu(struct spu_context *ctx, u32 *npc, u32 *event)
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{
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int ret;
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@ -364,13 +375,20 @@ long spufs_run_spu(struct spu_context *ctx, u32 *npc, u32 *event)
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if (ret)
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break;
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ret = spufs_handle_class0(ctx);
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if (ret)
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break;
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if (unlikely(ctx->state != SPU_STATE_RUNNABLE)) {
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ret = spu_reacquire_runnable(ctx, npc, &status);
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if (ret)
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goto out2;
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continue;
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}
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ret = spu_process_events(ctx);
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if (signal_pending(current))
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ret = -ERESTARTSYS;
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} while (!ret && !(status & (SPU_STATUS_STOPPED_BY_STOP |
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SPU_STATUS_STOPPED_BY_HALT |
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@ -245,7 +245,6 @@ static void spu_bind_context(struct spu *spu, struct spu_context *ctx)
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spu->wbox_callback = spufs_wbox_callback;
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spu->stop_callback = spufs_stop_callback;
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spu->mfc_callback = spufs_mfc_callback;
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spu->dma_callback = spufs_dma_callback;
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mb();
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spu_unmap_mappings(ctx);
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spu_restore(&ctx->csa, spu);
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@ -433,7 +432,6 @@ static void spu_unbind_context(struct spu *spu, struct spu_context *ctx)
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spu->wbox_callback = NULL;
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spu->stop_callback = NULL;
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spu->mfc_callback = NULL;
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spu->dma_callback = NULL;
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spu_associate_mm(spu, NULL);
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spu->pid = 0;
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spu->tgid = 0;
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@ -222,6 +222,7 @@ void spu_gang_add_ctx(struct spu_gang *gang, struct spu_context *ctx);
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/* fault handling */
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int spufs_handle_class1(struct spu_context *ctx);
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int spufs_handle_class0(struct spu_context *ctx);
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/* affinity */
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struct spu *affinity_check(struct spu_context *ctx);
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@ -2077,10 +2077,6 @@ int spu_save(struct spu_state *prev, struct spu *spu)
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int rc;
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acquire_spu_lock(spu); /* Step 1. */
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prev->dar = spu->dar;
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prev->dsisr = spu->dsisr;
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spu->dar = 0;
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spu->dsisr = 0;
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rc = __do_spu_save(prev, spu); /* Steps 2-53. */
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release_spu_lock(spu);
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if (rc != 0 && rc != 2 && rc != 6) {
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@ -2107,9 +2103,6 @@ int spu_restore(struct spu_state *new, struct spu *spu)
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acquire_spu_lock(spu);
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harvest(NULL, spu);
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spu->slb_replace = 0;
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new->dar = 0;
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new->dsisr = 0;
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spu->class_0_pending = 0;
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rc = __do_spu_restore(new, spu);
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release_spu_lock(spu);
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if (rc) {
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|
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@ -146,7 +146,6 @@ struct spu {
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void (* ibox_callback)(struct spu *spu);
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void (* stop_callback)(struct spu *spu);
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void (* mfc_callback)(struct spu *spu);
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void (* dma_callback)(struct spu *spu, int type);
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char irq_c0[8];
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char irq_c1[8];
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@ -197,8 +196,6 @@ struct cbe_spu_info {
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extern struct cbe_spu_info cbe_spu_info[];
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void spu_init_channels(struct spu *spu);
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int spu_irq_class_0_bottom(struct spu *spu);
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int spu_irq_class_1_bottom(struct spu *spu);
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void spu_irq_setaffinity(struct spu *spu, int cpu);
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void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
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@ -254,7 +254,7 @@ struct spu_state {
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u64 spu_chnldata_RW[32];
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u32 spu_mailbox_data[4];
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u32 pu_mailbox_data[1];
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u64 dar, dsisr;
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u64 dar, dsisr, class_0_pending;
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unsigned long suspend_time;
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spinlock_t register_lock;
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};
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