dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support
Extend the binding to cover the set of feature found in Tegra210. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -35,6 +35,7 @@ Required properties:
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- compatible: Must be:
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- Tegra124: "nvidia,tegra124-xusb-padctl"
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- Tegra132: "nvidia,tegra132-xusb-padctl", "nvidia,tegra124-xusb-padctl"
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- Tegra210: "nvidia,tegra210-xusb-padctl"
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- reg: Physical base address and length of the controller's registers.
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- resets: Must contain an entry for each entry in reset-names.
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- reset-names: Must include the following entries:
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@ -55,6 +56,44 @@ the pad and any of its lanes, this property must be set to "okay".
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For Tegra124 and Tegra132, the following pads exist: usb2, ulpi, hsic, pcie
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and sata. No extra resources are required for operation of these pads.
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For Tegra210, the following pads exist: usb2, hsic, pcie and sata. Below is
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a description of the properties of each pad.
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UTMI pad:
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---------
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Required properties:
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Must contain the following entries:
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- "trk": phandle and specifier referring to the USB2 tracking clock
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HSIC pad:
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---------
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Required properties:
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Must contain the following entries:
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- "trk": phandle and specifier referring to the HSIC tracking clock
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PCIe pad:
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---------
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Required properties:
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- clocks: Must contain an entry for each entry in clock-names.
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- clock-names: Must contain the following entries:
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- "pll": phandle and specifier referring to the PLLE
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- resets: Must contain an entry for each entry in reset-names.
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- reset-names: Must contain the following entries:
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- "phy": reset for the PCIe UPHY block
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SATA pad:
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---------
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Required properties:
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- resets: Must contain an entry for each entry in reset-names.
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- reset-names: Must contain the following entries:
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- "phy": reset for the SATA UPHY block
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PHY nodes:
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==========
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@ -84,6 +123,16 @@ For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
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- sata: sata-0
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- functions: "usb3-ss", "sata"
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For Tegra210, the list of valid PHY nodes is given below:
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- utmi: utmi-0, utmi-1, utmi-2, utmi-3
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- functions: "snps", "xusb", "uart"
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- hsic: hsic-0, hsic-1
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- functions: "snps", "xusb"
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- pcie: pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, pcie-5, pcie-6
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- functions: "pcie-x1", "usb3-ss", "pcie-x4"
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- sata: sata-0
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- functions: "usb3-ss", "sata"
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Port nodes:
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===========
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@ -144,6 +193,7 @@ Required properties:
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to map this super-speed USB port to. The range of valid port numbers varies
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with the SoC generation:
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- 0-2: for Tegra124 and Tegra132
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- 0-3: for Tegra210
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Optional properties:
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- nvidia,internal: A boolean property whose presence determines that a port
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@ -157,6 +207,11 @@ ports:
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- 2x HSIC: hsic-0, hsic-1
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- 2x super-speed USB: usb3-0, usb3-1
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For Tegra210, the XUSB pad controller exposes the following ports:
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- 4x USB2: usb2-0, usb2-1, usb2-2, usb2-3
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- 2x HSIC: hsic-0, hsic-1
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- 4x super-speed USB: usb3-0, usb3-1, usb3-2, usb3-3
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Examples:
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=========
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@ -390,3 +445,289 @@ Board file:
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};
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};
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};
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Tegra210:
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---------
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SoC include:
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padctl@7009f000 {
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compatible = "nvidia,tegra210-xusb-padctl";
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reg = <0x0 0x7009f000 0x0 0x1000>;
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resets = <&tegra_car 142>;
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reset-names = "padctl";
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status = "disabled";
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pads {
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usb2 {
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clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
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clock-names = "trk";
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status = "disabled";
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lanes {
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usb2-0 {
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status = "disabled";
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#phy-cells = <0>;
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};
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usb2-1 {
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status = "disabled";
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#phy-cells = <0>;
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};
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usb2-2 {
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status = "disabled";
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#phy-cells = <0>;
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};
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usb2-3 {
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status = "disabled";
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#phy-cells = <0>;
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};
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};
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};
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hsic {
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clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
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clock-names = "trk";
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status = "disabled";
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lanes {
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hsic-0 {
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status = "disabled";
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#phy-cells = <0>;
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};
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hsic-1 {
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status = "disabled";
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#phy-cells = <0>;
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};
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};
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};
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pcie {
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clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
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clock-names = "pll";
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resets = <&tegra_car 205>;
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reset-names = "phy";
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status = "disabled";
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lanes {
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pcie-0 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-1 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-2 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-3 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-4 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-5 {
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status = "disabled";
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#phy-cells = <0>;
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};
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pcie-6 {
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status = "disabled";
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#phy-cells = <0>;
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};
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};
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};
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sata {
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clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
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clock-names = "pll";
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resets = <&tegra_car 204>;
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reset-names = "phy";
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status = "disabled";
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lanes {
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sata-0 {
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status = "disabled";
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#phy-cells = <0>;
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};
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};
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};
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};
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ports {
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usb2-0 {
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status = "disabled";
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};
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usb2-1 {
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status = "disabled";
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};
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usb2-2 {
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status = "disabled";
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};
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usb2-3 {
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status = "disabled";
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};
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hsic-0 {
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status = "disabled";
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};
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hsic-1 {
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status = "disabled";
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};
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usb3-0 {
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status = "disabled";
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};
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usb3-1 {
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status = "disabled";
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};
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usb3-2 {
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status = "disabled";
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};
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usb3-3 {
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status = "disabled";
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};
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};
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};
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Board file:
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padctl@7009f000 {
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status = "okay";
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pads {
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usb2 {
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status = "okay";
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lanes {
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usb2-0 {
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nvidia,function = "xusb";
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status = "okay";
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};
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usb2-1 {
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nvidia,function = "xusb";
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status = "okay";
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};
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usb2-2 {
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nvidia,function = "xusb";
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status = "okay";
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};
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usb2-3 {
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nvidia,function = "xusb";
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status = "okay";
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};
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};
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};
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pcie {
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status = "okay";
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lanes {
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pcie-0 {
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nvidia,function = "pcie-x1";
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status = "okay";
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};
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pcie-1 {
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nvidia,function = "pcie-x4";
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status = "okay";
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};
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pcie-2 {
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nvidia,function = "pcie-x4";
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status = "okay";
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};
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pcie-3 {
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nvidia,function = "pcie-x4";
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status = "okay";
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};
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pcie-4 {
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nvidia,function = "pcie-x4";
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status = "okay";
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};
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pcie-5 {
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nvidia,function = "usb3-ss";
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status = "okay";
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};
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pcie-6 {
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nvidia,function = "usb3-ss";
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status = "okay";
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};
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};
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};
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sata {
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status = "okay";
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lanes {
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sata-0 {
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nvidia,function = "sata";
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status = "okay";
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};
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};
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};
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};
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ports {
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usb2-0 {
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status = "okay";
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mode = "otg";
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};
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usb2-1 {
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status = "okay";
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vbus-supply = <&vdd_5v0_rtl>;
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mode = "host";
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};
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usb2-2 {
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status = "okay";
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vbus-supply = <&vdd_usb_vbus>;
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mode = "host";
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};
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usb2-3 {
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status = "okay";
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mode = "host";
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};
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usb3-0 {
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status = "okay";
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nvidia,lanes = "pcie-6";
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nvidia,port = <1>;
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};
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usb3-1 {
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status = "okay";
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nvidia,lanes = "pcie-5";
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nvidia,port = <2>;
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};
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};
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};
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