mtd: rawnand: Use the ECC framework user input parsing bits
Many helpers are generic to all NAND chips, they should not be raw-NAND specific, so use the generic ones. To avoid moving all the raw NAND core "history" into the generic NAND layer, we keep a part of this parsing in the raw NAND core to ensure backward compatibility. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/20200827085208.16276-20-miquel.raynal@bootlin.com
This commit is contained in:
Miquel Raynal
Родитель
8c126720fe
Коммит
d7157ff49a
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@ -4877,18 +4877,27 @@ free_detect_allocation:
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return ret;
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}
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static const char * const nand_ecc_modes[] = {
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[NAND_ECC_NONE] = "none",
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[NAND_ECC_SOFT] = "soft",
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[NAND_ECC_HW] = "hw",
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[NAND_ECC_HW_SYNDROME] = "hw_syndrome",
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[NAND_ECC_ON_DIE] = "on-die",
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};
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static enum nand_ecc_engine_type
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of_get_nand_ecc_engine_type(struct device_node *np)
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of_get_rawnand_ecc_engine_type_legacy(struct device_node *np)
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{
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enum nand_ecc_mode eng_type;
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enum nand_ecc_legacy_mode {
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NAND_ECC_INVALID,
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NAND_ECC_NONE,
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NAND_ECC_SOFT,
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NAND_ECC_SOFT_BCH,
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NAND_ECC_HW,
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NAND_ECC_HW_SYNDROME,
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NAND_ECC_ON_DIE,
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};
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const char * const nand_ecc_legacy_modes[] = {
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[NAND_ECC_NONE] = "none",
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[NAND_ECC_SOFT] = "soft",
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[NAND_ECC_SOFT_BCH] = "soft_bch",
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[NAND_ECC_HW] = "hw",
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[NAND_ECC_HW_SYNDROME] = "hw_syndrome",
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[NAND_ECC_ON_DIE] = "on-die",
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};
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enum nand_ecc_legacy_mode eng_type;
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const char *pm;
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int err;
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@ -4897,12 +4906,13 @@ of_get_nand_ecc_engine_type(struct device_node *np)
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return NAND_ECC_ENGINE_TYPE_INVALID;
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for (eng_type = NAND_ECC_NONE;
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eng_type < ARRAY_SIZE(nand_ecc_modes); eng_type++) {
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if (!strcasecmp(pm, nand_ecc_modes[eng_type])) {
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eng_type < ARRAY_SIZE(nand_ecc_legacy_modes); eng_type++) {
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if (!strcasecmp(pm, nand_ecc_legacy_modes[eng_type])) {
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switch (eng_type) {
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case NAND_ECC_NONE:
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return NAND_ECC_ENGINE_TYPE_NONE;
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case NAND_ECC_SOFT:
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case NAND_ECC_SOFT_BCH:
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return NAND_ECC_ENGINE_TYPE_SOFT;
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case NAND_ECC_HW:
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case NAND_ECC_HW_SYNDROME:
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@ -4915,43 +4925,29 @@ of_get_nand_ecc_engine_type(struct device_node *np)
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}
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}
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/*
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* For backward compatibility we support few obsoleted values that don't
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* have their mappings into the nand_ecc_engine_providers enum anymore
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* (they were merged with other enums).
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*/
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if (!strcasecmp(pm, "soft_bch"))
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return NAND_ECC_ENGINE_TYPE_SOFT;
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return NAND_ECC_ENGINE_TYPE_INVALID;
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}
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static const char * const nand_ecc_algos[] = {
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[NAND_ECC_ALGO_HAMMING] = "hamming",
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[NAND_ECC_ALGO_BCH] = "bch",
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[NAND_ECC_ALGO_RS] = "rs",
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};
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static enum nand_ecc_algo of_get_nand_ecc_algo(struct device_node *np)
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static enum nand_ecc_placement
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of_get_rawnand_ecc_placement_legacy(struct device_node *np)
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{
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enum nand_ecc_algo ecc_algo;
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const char *pm;
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int err;
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err = of_property_read_string(np, "nand-ecc-algo", &pm);
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err = of_property_read_string(np, "nand-ecc-mode", &pm);
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if (!err) {
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for (ecc_algo = NAND_ECC_ALGO_HAMMING;
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ecc_algo < ARRAY_SIZE(nand_ecc_algos);
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ecc_algo++) {
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if (!strcasecmp(pm, nand_ecc_algos[ecc_algo]))
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return ecc_algo;
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}
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if (!strcasecmp(pm, "hw_syndrome"))
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return NAND_ECC_PLACEMENT_INTERLEAVED;
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}
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/*
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* For backward compatibility we also read "nand-ecc-mode" checking
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* for some obsoleted values that were specifying ECC algorithm.
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*/
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return NAND_ECC_PLACEMENT_UNKNOWN;
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}
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static enum nand_ecc_algo of_get_rawnand_ecc_algo_legacy(struct device_node *np)
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{
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const char *pm;
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int err;
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err = of_property_read_string(np, "nand-ecc-mode", &pm);
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if (!err) {
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if (!strcasecmp(pm, "soft"))
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@ -4963,22 +4959,19 @@ static enum nand_ecc_algo of_get_nand_ecc_algo(struct device_node *np)
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return NAND_ECC_ALGO_UNKNOWN;
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}
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static int of_get_nand_ecc_step_size(struct device_node *np)
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static void of_get_nand_ecc_legacy_user_config(struct nand_chip *chip)
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{
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int ret;
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u32 val;
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struct device_node *dn = nand_get_flash_node(chip);
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struct nand_ecc_props *user_conf = &chip->base.ecc.user_conf;
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ret = of_property_read_u32(np, "nand-ecc-step-size", &val);
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return ret ? ret : val;
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}
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if (user_conf->engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
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user_conf->engine_type = of_get_rawnand_ecc_engine_type_legacy(dn);
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static int of_get_nand_ecc_strength(struct device_node *np)
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{
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int ret;
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u32 val;
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if (user_conf->algo == NAND_ECC_ALGO_UNKNOWN)
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user_conf->algo = of_get_rawnand_ecc_algo_legacy(dn);
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ret = of_property_read_u32(np, "nand-ecc-strength", &val);
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return ret ? ret : val;
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if (user_conf->placement == NAND_ECC_PLACEMENT_UNKNOWN)
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user_conf->placement = of_get_rawnand_ecc_placement_legacy(dn);
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}
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static int of_get_nand_bus_width(struct device_node *np)
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@ -5002,12 +4995,10 @@ static bool of_get_nand_on_flash_bbt(struct device_node *np)
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return of_property_read_bool(np, "nand-on-flash-bbt");
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}
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static int nand_dt_init(struct nand_chip *chip)
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static int rawnand_dt_init(struct nand_chip *chip)
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{
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struct nand_device *nand = mtd_to_nanddev(nand_to_mtd(chip));
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struct device_node *dn = nand_get_flash_node(chip);
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enum nand_ecc_engine_type ecc_type;
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enum nand_ecc_algo ecc_algo;
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int ecc_strength, ecc_step;
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if (!dn)
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return 0;
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@ -5021,26 +5012,33 @@ static int nand_dt_init(struct nand_chip *chip)
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if (of_get_nand_on_flash_bbt(dn))
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chip->bbt_options |= NAND_BBT_USE_FLASH;
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ecc_type = of_get_nand_ecc_engine_type(dn);
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ecc_algo = of_get_nand_ecc_algo(dn);
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ecc_strength = of_get_nand_ecc_strength(dn);
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ecc_step = of_get_nand_ecc_step_size(dn);
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if (ecc_type != NAND_ECC_ENGINE_TYPE_INVALID)
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chip->ecc.engine_type = ecc_type;
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if (ecc_algo != NAND_ECC_ALGO_UNKNOWN)
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chip->ecc.algo = ecc_algo;
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if (ecc_strength >= 0)
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chip->ecc.strength = ecc_strength;
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if (ecc_step > 0)
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chip->ecc.size = ecc_step;
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if (of_property_read_bool(dn, "nand-ecc-maximize"))
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chip->ecc.options |= NAND_ECC_MAXIMIZE;
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of_get_nand_ecc_user_config(nand);
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of_get_nand_ecc_legacy_user_config(chip);
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/*
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* If neither the user nor the NAND controller have requested a specific
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* ECC engine type, we will default to NAND_ECC_ENGINE_TYPE_ON_HOST.
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*/
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nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;
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/*
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* Use the user requested engine type, unless there is none, in this
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* case default to the NAND controller choice, otherwise fallback to
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* the raw NAND default one.
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*/
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if (nand->ecc.user_conf.engine_type != NAND_ECC_ENGINE_TYPE_INVALID)
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chip->ecc.engine_type = nand->ecc.user_conf.engine_type;
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if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID)
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chip->ecc.engine_type = nand->ecc.defaults.engine_type;
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chip->ecc.placement = nand->ecc.user_conf.placement;
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chip->ecc.algo = nand->ecc.user_conf.algo;
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chip->ecc.strength = nand->ecc.user_conf.strength;
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chip->ecc.size = nand->ecc.user_conf.step_size;
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return 0;
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}
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@ -5077,7 +5075,7 @@ static int nand_scan_ident(struct nand_chip *chip, unsigned int maxchips,
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/* Enforce the right timings for reset/detection */
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chip->current_interface_config = nand_get_reset_interface_config();
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ret = nand_dt_init(chip);
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ret = rawnand_dt_init(chip);
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if (ret)
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return ret;
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@ -81,18 +81,6 @@ struct nand_chip;
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#define NAND_DATA_IFACE_CHECK_ONLY -1
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/*
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* Constants for ECC_MODES
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*/
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enum nand_ecc_mode {
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NAND_ECC_INVALID,
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NAND_ECC_NONE,
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NAND_ECC_SOFT,
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NAND_ECC_HW,
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NAND_ECC_HW_SYNDROME,
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NAND_ECC_ON_DIE,
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};
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/*
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* Constants for Hardware ECC
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*/
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