PCI: pciehp: Reshuffle controller struct for clarity
The members in pciehp's controller struct are arranged in a seemingly arbitrary order and have grown to an amount that I no longer consider easily graspable by contributors. Sort the members into 5 rubrics: * Slot Capabilities register and quirks * Slot Control register access * Slot Status register event handling * state machine * hotplug core interface Obviously, this is just my personal bikeshed color and if anyone has a better idea, please come forward. Any ordering will do as long as the information is presented in a manageable manner. No functional change intended. Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -60,38 +60,38 @@ do { \
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/**
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* struct controller - PCIe hotplug controller
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* @ctrl_lock: serializes writes to the Slot Control register
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* @pcie: pointer to the controller's PCIe port service device
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* @reset_lock: prevents access to the Data Link Layer Link Active bit in the
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* Link Status register and to the Presence Detect State bit in the Slot
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* Status register during a slot reset which may cause them to flap
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* @queue: wait queue to wake up on reception of a Command Completed event,
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* used for synchronous writes to the Slot Control register
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* @slot_cap: cached copy of the Slot Capabilities register
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* @slot_ctrl: cached copy of the Slot Control register
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* @poll_thread: thread to poll for slot events if no IRQ is available,
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* enabled with pciehp_poll_mode module parameter
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* @cmd_started: jiffies when the Slot Control register was last written;
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* the next write is allowed 1 second later, absent a Command Completed
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* interrupt (PCIe r4.0, sec 6.7.3.2)
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* @cmd_busy: flag set on Slot Control register write, cleared by IRQ handler
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* on reception of a Command Completed event
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* @link_active_reporting: cached copy of Data Link Layer Link Active Reporting
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* Capable bit in Link Capabilities register; if this bit is zero, the
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* Data Link Layer Link Active bit in the Link Status register will never
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* be set and the driver is thus confined to wait 1 second before assuming
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* the link to a hotplugged device is up and accessing it
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* @slot_ctrl: cached copy of the Slot Control register
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* @ctrl_lock: serializes writes to the Slot Control register
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* @cmd_started: jiffies when the Slot Control register was last written;
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* the next write is allowed 1 second later, absent a Command Completed
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* interrupt (PCIe r4.0, sec 6.7.3.2)
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* @cmd_busy: flag set on Slot Control register write, cleared by IRQ handler
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* on reception of a Command Completed event
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* @queue: wait queue to wake up on reception of a Command Completed event,
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* used for synchronous writes to the Slot Control register
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* @pending_events: used by the IRQ handler to save events retrieved from the
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* Slot Status register for later consumption by the IRQ thread
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* @notification_enabled: whether the IRQ was requested successfully
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* @power_fault_detected: whether a power fault was detected by the hardware
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* that has not yet been cleared by the user
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* @pending_events: used by the IRQ handler to save events retrieved from the
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* Slot Status register for later consumption by the IRQ thread
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* @poll_thread: thread to poll for slot events if no IRQ is available,
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* enabled with pciehp_poll_mode module parameter
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* @state: current state machine position
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* @state_lock: protects reads and writes of @state;
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* protects scheduling, execution and cancellation of @button_work
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* @button_work: work item to turn the slot on or off after 5 seconds
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* in response to an Attention Button press
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* @hotplug_slot: pointer to the structure registered with the PCI hotplug core
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* @reset_lock: prevents access to the Data Link Layer Link Active bit in the
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* Link Status register and to the Presence Detect State bit in the Slot
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* Status register during a slot reset which may cause them to flap
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* @request_result: result of last user request submitted to the IRQ thread
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* @requester: wait queue to wake up on completion of user request,
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* used for synchronous slot enable/disable request via sysfs
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@ -100,23 +100,28 @@ do { \
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* unlike other drivers, the two aren't represented by separate structures.
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*/
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struct controller {
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struct mutex ctrl_lock;
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struct pcie_device *pcie;
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struct rw_semaphore reset_lock;
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wait_queue_head_t queue;
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u32 slot_cap;
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u16 slot_ctrl;
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struct task_struct *poll_thread;
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unsigned long cmd_started; /* jiffies */
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unsigned int cmd_busy:1;
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u32 slot_cap; /* capabilities and quirks */
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unsigned int link_active_reporting:1;
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u16 slot_ctrl; /* control register access */
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struct mutex ctrl_lock;
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unsigned long cmd_started;
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unsigned int cmd_busy:1;
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wait_queue_head_t queue;
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atomic_t pending_events; /* event handling */
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unsigned int notification_enabled:1;
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unsigned int power_fault_detected;
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atomic_t pending_events;
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u8 state;
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struct task_struct *poll_thread;
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u8 state; /* state machine */
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struct mutex state_lock;
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struct delayed_work button_work;
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struct hotplug_slot *hotplug_slot;
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struct hotplug_slot *hotplug_slot; /* hotplug core interface */
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struct rw_semaphore reset_lock;
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int request_result;
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wait_queue_head_t requester;
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};
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