drm/amdgpu: Modify indirect register access for gfx9 sriov
Expand RLCG interface for new GC read & write commands. New interface will only be used if the PF enables the flag in pf2vf msg. v2: Added a description for the scratch registers Signed-off-by: Victor Skvortsov <victor.skvortsov@amd.com> Reviewed-by: David Nieto <david.nieto@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Victor Skvortsov
Alex Deucher
Родитель
4a0165f060
Коммит
d764fb2af6
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@ -63,6 +63,13 @@
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#define mmGCEA_PROBE_MAP 0x070c
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#define mmGCEA_PROBE_MAP_BASE_IDX 0
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#define GFX9_RLCG_GC_WRITE_OLD (0x8 << 28)
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#define GFX9_RLCG_GC_WRITE (0x0 << 28)
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#define GFX9_RLCG_GC_READ (0x1 << 28)
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#define GFX9_RLCG_VFGATE_DISABLED 0x4000000
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#define GFX9_RLCG_WRONG_OPERATION_TYPE 0x2000000
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#define GFX9_RLCG_NOT_IN_RANGE 0x1000000
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MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
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MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
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MODULE_FIRMWARE("amdgpu/vega10_me.bin");
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@ -739,7 +746,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
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mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
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};
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static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
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static u32 gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
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{
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static void *scratch_reg0;
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static void *scratch_reg1;
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@ -748,21 +755,20 @@ static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 f
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static void *spare_int;
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static uint32_t grbm_cntl;
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static uint32_t grbm_idx;
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uint32_t i = 0;
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uint32_t retries = 50000;
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u32 ret = 0;
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u32 tmp;
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scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
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scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
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scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
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scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
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scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG2_BASE_IDX] + mmSCRATCH_REG2)*4;
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scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG3_BASE_IDX] + mmSCRATCH_REG3)*4;
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spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
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grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
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grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
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if (amdgpu_sriov_runtime(adev)) {
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pr_err("shouldn't call rlcg write register during runtime\n");
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return;
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}
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if (offset == grbm_cntl || offset == grbm_idx) {
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if (offset == grbm_cntl)
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writel(v, scratch_reg2);
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@ -771,41 +777,95 @@ static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 f
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writel(v, ((void __iomem *)adev->rmmio) + (offset * 4));
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} else {
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uint32_t i = 0;
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uint32_t retries = 50000;
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/*
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* SCRATCH_REG0 = read/write value
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* SCRATCH_REG1[30:28] = command
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* SCRATCH_REG1[19:0] = address in dword
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* SCRATCH_REG1[26:24] = Error reporting
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*/
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writel(v, scratch_reg0);
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writel(offset | 0x80000000, scratch_reg1);
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writel(offset | flag, scratch_reg1);
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writel(1, spare_int);
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for (i = 0; i < retries; i++) {
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u32 tmp;
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for (i = 0; i < retries; i++) {
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tmp = readl(scratch_reg1);
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if (!(tmp & 0x80000000))
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if (!(tmp & flag))
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break;
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udelay(10);
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}
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if (i >= retries)
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pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
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if (i >= retries) {
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if (amdgpu_sriov_reg_indirect_gc(adev)) {
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if (tmp & GFX9_RLCG_VFGATE_DISABLED)
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pr_err("The vfgate is disabled, program reg:0x%05x failed!\n", offset);
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else if (tmp & GFX9_RLCG_WRONG_OPERATION_TYPE)
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pr_err("Wrong operation type, program reg:0x%05x failed!\n", offset);
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else if (tmp & GFX9_RLCG_NOT_IN_RANGE)
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pr_err("The register is not in range, program reg:0x%05x failed!\n", offset);
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else
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pr_err("Unknown error type, program reg:0x%05x failed!\n", offset);
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} else
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pr_err("timeout: rlcg program reg:0x%05x failed!\n", offset);
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}
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}
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ret = readl(scratch_reg0);
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return ret;
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}
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static bool gfx_v9_0_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip,
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int write, u32 *rlcg_flag)
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{
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switch (hwip) {
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case GC_HWIP:
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if (amdgpu_sriov_reg_indirect_gc(adev)) {
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*rlcg_flag = write ? GFX9_RLCG_GC_WRITE : GFX9_RLCG_GC_READ;
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return true;
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/* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC enabled simultaneously */
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} else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags & AMDGPU_REGS_NO_KIQ) && write) {
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*rlcg_flag = GFX9_RLCG_GC_WRITE_OLD;
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return true;
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}
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break;
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default:
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return false;
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}
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return false;
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}
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static u32 gfx_v9_0_sriov_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)
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{
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u32 rlcg_flag;
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if (!amdgpu_sriov_runtime(adev) && gfx_v9_0_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag))
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return gfx_v9_0_rlcg_rw(adev, offset, 0, rlcg_flag);
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if (acc_flags & AMDGPU_REGS_NO_KIQ)
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return RREG32_NO_KIQ(offset);
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else
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return RREG32(offset);
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}
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static void gfx_v9_0_sriov_wreg(struct amdgpu_device *adev, u32 offset,
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u32 v, u32 acc_flags, u32 hwip)
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u32 value, u32 acc_flags, u32 hwip)
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{
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if ((acc_flags & AMDGPU_REGS_RLC) &&
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amdgpu_sriov_fullaccess(adev)) {
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gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
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u32 rlcg_flag;
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if (!amdgpu_sriov_runtime(adev) && gfx_v9_0_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) {
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gfx_v9_0_rlcg_rw(adev, offset, value, rlcg_flag);
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return;
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}
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if (acc_flags & AMDGPU_REGS_NO_KIQ)
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WREG32_NO_KIQ(offset, v);
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WREG32_NO_KIQ(offset, value);
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else
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WREG32(offset, v);
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WREG32(offset, value);
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}
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#define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
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@ -5135,7 +5195,7 @@ static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
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if (amdgpu_sriov_is_pp_one_vf(adev))
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data = RREG32_NO_KIQ(reg);
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else
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data = RREG32(reg);
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data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
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data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
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data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
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@ -5191,6 +5251,7 @@ static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
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.start = gfx_v9_0_rlc_start,
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.update_spm_vmid = gfx_v9_0_update_spm_vmid,
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.sriov_wreg = gfx_v9_0_sriov_wreg,
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.sriov_rreg = gfx_v9_0_sriov_rreg,
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.is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range,
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};
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@ -5796,16 +5857,16 @@ static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
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switch (state) {
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case AMDGPU_IRQ_STATE_DISABLE:
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mec_int_cntl = RREG32(mec_int_cntl_reg);
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mec_int_cntl = RREG32_SOC15_IP(GC,mec_int_cntl_reg);
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mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
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TIME_STAMP_INT_ENABLE, 0);
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WREG32(mec_int_cntl_reg, mec_int_cntl);
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WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
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break;
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case AMDGPU_IRQ_STATE_ENABLE:
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mec_int_cntl = RREG32(mec_int_cntl_reg);
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mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
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mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
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TIME_STAMP_INT_ENABLE, 1);
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WREG32(mec_int_cntl_reg, mec_int_cntl);
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WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
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break;
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default:
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break;
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