MIPS: BMIPS: Add support SPI device nodes
Adds SPI device nodes to BCM7xxx MIPS based SoCs. Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14990/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Jaedon Shin
Ralf Baechle
Родитель
35e7f7885e
Коммит
d783738c00
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@ -91,15 +91,15 @@
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compatible = "brcm,bcm7120-l2-intc";
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reg = <0x406780 0x8>;
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brcm,int-map-mask = <0x44>, <0xf000000>;
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brcm,int-map-mask = <0x44>, <0xf000000>, <0x100000>;
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brcm,int-fwd-mask = <0x70000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <18>, <19>;
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interrupt-names = "upg_main", "upg_bsc";
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interrupts = <18>, <19>, <20>;
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interrupt-names = "upg_main", "upg_bsc", "upg_spi";
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};
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sun_top_ctrl: syscon@404000 {
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@ -226,5 +226,48 @@
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interrupts = <61>;
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status = "disabled";
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};
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spi_l2_intc: interrupt-controller@411d00 {
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compatible = "brcm,l2-intc";
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reg = <0x411d00 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <79>;
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};
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qspi: spi@443000 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-qspi";
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clocks = <&upg_clk>;
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reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
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reg-names = "cs_reg", "hif_mspi", "bspi";
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interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
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interrupt-parent = <&spi_l2_intc>;
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interrupt-names = "spi_lr_fullness_reached",
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"spi_lr_session_aborted",
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"spi_lr_impatient",
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"spi_lr_session_done",
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"spi_lr_overread",
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"mspi_done",
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"mspi_halted";
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status = "disabled";
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};
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mspi: spi@406400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-mspi";
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clocks = <&upg_clk>;
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reg = <0x406400 0x180>;
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reg-names = "mspi";
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interrupts = <0x14>;
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interrupt-parent = <&upg_irq0_intc>;
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interrupt-names = "mspi_done";
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status = "disabled";
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};
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};
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};
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@ -439,5 +439,48 @@
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interrupts = <85>;
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status = "disabled";
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};
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spi_l2_intc: interrupt-controller@411d00 {
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compatible = "brcm,l2-intc";
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reg = <0x411d00 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <31>;
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};
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qspi: spi@413000 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-qspi";
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clocks = <&upg_clk>;
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reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
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reg-names = "cs_reg", "hif_mspi", "bspi";
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interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
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interrupt-parent = <&spi_l2_intc>;
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interrupt-names = "spi_lr_fullness_reached",
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"spi_lr_session_aborted",
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"spi_lr_impatient",
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"spi_lr_session_done",
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"spi_lr_overread",
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"mspi_done",
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"mspi_halted";
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status = "disabled";
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};
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mspi: spi@408a00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-mspi";
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clocks = <&upg_clk>;
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reg = <0x408a00 0x180>;
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reg-names = "mspi";
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interrupts = <0x14>;
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interrupt-parent = <&upg_aon_irq0_intc>;
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interrupt-names = "mspi_done";
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status = "disabled";
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};
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};
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};
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@ -318,5 +318,48 @@
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interrupts = <24>;
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status = "disabled";
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};
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spi_l2_intc: interrupt-controller@411d00 {
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compatible = "brcm,l2-intc";
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reg = <0x411d00 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <31>;
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};
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qspi: spi@413000 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-qspi";
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clocks = <&upg_clk>;
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reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
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reg-names = "cs_reg", "hif_mspi", "bspi";
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interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
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interrupt-parent = <&spi_l2_intc>;
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interrupt-names = "spi_lr_fullness_reached",
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"spi_lr_session_aborted",
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"spi_lr_impatient",
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"spi_lr_session_done",
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"spi_lr_overread",
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"mspi_done",
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"mspi_halted";
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status = "disabled";
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};
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mspi: spi@408a00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-mspi";
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clocks = <&upg_clk>;
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reg = <0x408a00 0x180>;
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reg-names = "mspi";
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interrupts = <0x14>;
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interrupt-parent = <&upg_aon_irq0_intc>;
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interrupt-names = "mspi_done";
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status = "disabled";
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};
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};
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};
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@ -358,5 +358,48 @@
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interrupts = <82>;
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status = "disabled";
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};
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spi_l2_intc: interrupt-controller@411d00 {
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compatible = "brcm,l2-intc";
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reg = <0x411d00 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <31>;
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};
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qspi: spi@413000 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-qspi";
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clocks = <&upg_clk>;
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reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
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reg-names = "cs_reg", "hif_mspi", "bspi";
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interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
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interrupt-parent = <&spi_l2_intc>;
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interrupt-names = "spi_lr_fullness_reached",
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"spi_lr_session_aborted",
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"spi_lr_impatient",
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"spi_lr_session_done",
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"spi_lr_overread",
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"mspi_done",
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"mspi_halted";
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status = "disabled";
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};
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mspi: spi@408a00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-mspi";
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clocks = <&upg_clk>;
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reg = <0x408a00 0x180>;
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reg-names = "mspi";
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interrupts = <0x14>;
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interrupt-parent = <&upg_aon_irq0_intc>;
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interrupt-names = "mspi_done";
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status = "disabled";
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};
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};
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};
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@ -354,5 +354,48 @@
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interrupts = <82>;
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status = "disabled";
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};
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spi_l2_intc: interrupt-controller@411d00 {
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compatible = "brcm,l2-intc";
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reg = <0x411d00 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <31>;
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};
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qspi: spi@413000 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-qspi";
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clocks = <&upg_clk>;
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reg = <0x410920 0x4 0x413200 0x188 0x413000 0x50>;
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reg-names = "cs_reg", "hif_mspi", "bspi";
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interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
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interrupt-parent = <&spi_l2_intc>;
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interrupt-names = "spi_lr_fullness_reached",
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"spi_lr_session_aborted",
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"spi_lr_impatient",
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"spi_lr_session_done",
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"spi_lr_overread",
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"mspi_done",
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"mspi_halted";
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status = "disabled";
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};
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mspi: spi@408a00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-mspi";
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clocks = <&upg_clk>;
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reg = <0x408a00 0x180>;
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reg-names = "mspi";
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interrupts = <0x14>;
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interrupt-parent = <&upg_aon_irq0_intc>;
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interrupt-names = "mspi_done";
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status = "disabled";
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};
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};
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};
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@ -92,15 +92,15 @@
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compatible = "brcm,bcm7120-l2-intc";
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reg = <0x406780 0x8>;
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brcm,int-map-mask = <0x44>, <0x1f000000>;
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brcm,int-map-mask = <0x44>, <0x1f000000>, <0x100000>;
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brcm,int-fwd-mask = <0x70000>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <18>, <19>;
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interrupt-names = "upg_main", "upg_bsc";
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interrupts = <18>, <19>, <20>;
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interrupt-names = "upg_main", "upg_bsc", "upg_spi";
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};
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sun_top_ctrl: syscon@404000 {
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@ -287,5 +287,48 @@
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interrupts = <62>;
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status = "disabled";
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};
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spi_l2_intc: interrupt-controller@411d00 {
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compatible = "brcm,l2-intc";
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reg = <0x411d00 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <78>;
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};
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qspi: spi@443000 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-qspi";
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clocks = <&upg_clk>;
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reg = <0x440920 0x4 0x443200 0x188 0x443000 0x50>;
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reg-names = "cs_reg", "hif_mspi", "bspi";
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interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
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interrupt-parent = <&spi_l2_intc>;
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interrupt-names = "spi_lr_fullness_reached",
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"spi_lr_session_aborted",
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"spi_lr_impatient",
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"spi_lr_session_done",
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"spi_lr_overread",
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"mspi_done",
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"mspi_halted";
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status = "disabled";
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};
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mspi: spi@406400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-mspi";
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clocks = <&upg_clk>;
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reg = <0x406400 0x180>;
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reg-names = "mspi";
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interrupts = <0x14>;
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interrupt-parent = <&upg_irq0_intc>;
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interrupt-names = "mspi_done";
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status = "disabled";
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};
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};
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};
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@ -450,5 +450,48 @@
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mmc-hs200-1_8v;
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status = "disabled";
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};
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spi_l2_intc: interrupt-controller@41ad00 {
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compatible = "brcm,l2-intc";
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reg = <0x41ad00 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <25>;
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};
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qspi: spi@41c000 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-qspi";
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clocks = <&upg_clk>;
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reg = <0x419920 0x4 0x41c200 0x188 0x41c000 0x50>;
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reg-names = "cs_reg", "hif_mspi", "bspi";
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interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
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interrupt-parent = <&spi_l2_intc>;
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interrupt-names = "spi_lr_fullness_reached",
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"spi_lr_session_aborted",
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"spi_lr_impatient",
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"spi_lr_session_done",
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"spi_lr_overread",
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"mspi_done",
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"mspi_halted";
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status = "disabled";
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};
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mspi: spi@409200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-mspi";
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clocks = <&upg_clk>;
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reg = <0x409200 0x180>;
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reg-names = "mspi";
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interrupts = <0x14>;
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interrupt-parent = <&upg_aon_irq0_intc>;
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interrupt-names = "mspi_done";
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status = "disabled";
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};
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};
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};
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|
|
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|
|
@ -465,5 +465,48 @@
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mmc-hs200-1_8v;
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status = "disabled";
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};
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spi_l2_intc: interrupt-controller@41bd00 {
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compatible = "brcm,l2-intc";
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reg = <0x41bd00 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&periph_intc>;
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interrupts = <25>;
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};
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qspi: spi@41d200 {
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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compatible = "brcm,spi-bcm-qspi",
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"brcm,spi-brcmstb-qspi";
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clocks = <&upg_clk>;
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reg = <0x41a920 0x4 0x41d400 0x188 0x41d200 0x50>;
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reg-names = "cs_reg", "hif_mspi", "bspi";
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interrupts = <0x0 0x1 0x2 0x3 0x4 0x5 0x6>;
|
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interrupt-parent = <&spi_l2_intc>;
|
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interrupt-names = "spi_lr_fullness_reached",
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"spi_lr_session_aborted",
|
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"spi_lr_impatient",
|
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"spi_lr_session_done",
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"spi_lr_overread",
|
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"mspi_done",
|
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"mspi_halted";
|
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status = "disabled";
|
||||
};
|
||||
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||||
mspi: spi@409200 {
|
||||
#address-cells = <1>;
|
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#size-cells = <0>;
|
||||
compatible = "brcm,spi-bcm-qspi",
|
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"brcm,spi-brcmstb-mspi";
|
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clocks = <&upg_clk>;
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reg = <0x409200 0x180>;
|
||||
reg-names = "mspi";
|
||||
interrupts = <0x14>;
|
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interrupt-parent = <&upg_aon_irq0_intc>;
|
||||
interrupt-names = "mspi_done";
|
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status = "disabled";
|
||||
};
|
||||
};
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||||
};
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||||
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|||
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@ -57,3 +57,7 @@
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|||
&ohci0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -109,3 +109,7 @@
|
|||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -69,3 +69,39 @@
|
|||
&nand {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
m25p80@0 {
|
||||
compatible = "m25p80";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
use-bspi;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
flash0.cfe@0 {
|
||||
reg = <0x0 0x200000>;
|
||||
};
|
||||
|
||||
flash0.mac@200000 {
|
||||
reg = <0x200000 0x40000>;
|
||||
};
|
||||
|
||||
flash0.nvram@240000 {
|
||||
reg = <0x240000 0x10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -72,3 +72,39 @@
|
|||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
m25p80@0 {
|
||||
compatible = "m25p80";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
use-bspi;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
flash0.cfe@0 {
|
||||
reg = <0x0 0x200000>;
|
||||
};
|
||||
|
||||
flash0.mac@200000 {
|
||||
reg = <0x200000 0x40000>;
|
||||
};
|
||||
|
||||
flash0.nvram@240000 {
|
||||
reg = <0x240000 0x10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -73,3 +73,7 @@
|
|||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -79,3 +79,7 @@
|
|||
&ohci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -107,3 +107,39 @@
|
|||
&sdhci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
|
||||
m25p80@0 {
|
||||
compatible = "m25p80";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
use-bspi;
|
||||
m25p,fast-read;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
flash0.cfe@0 {
|
||||
reg = <0x0 0x200000>;
|
||||
};
|
||||
|
||||
flash0.mac@200000 {
|
||||
reg = <0x200000 0x40000>;
|
||||
};
|
||||
|
||||
flash0.nvram@240000 {
|
||||
reg = <0x240000 0x10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -115,3 +115,7 @@
|
|||
&sdhci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mspi {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче