arm64: dts: uniphier: Add USB3 controller nodes
Add USB3 controller nodes including usb-core, resets, regulator, ss-phy and hs-phy. This supports for LD20, PXs3 and the boards. This includes additional efuse nodes for obtaining PHY trimming values. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Kunihiko Hayashi
Masahiro Yamada
Родитель
8bb2f53203
Коммит
d7b9beb830
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@ -148,3 +148,7 @@
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&nand {
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status = "okay";
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};
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&usb {
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status = "okay";
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};
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@ -75,3 +75,7 @@
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drive-strength = <9>;
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};
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};
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&usb {
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status = "okay";
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};
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@ -611,6 +611,50 @@
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efuse@200 {
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compatible = "socionext,uniphier-efuse";
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reg = <0x200 0x68>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* USB cells */
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usb_rterm0: trim@54,4 {
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reg = <0x54 1>;
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bits = <4 2>;
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};
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usb_rterm1: trim@55,4 {
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reg = <0x55 1>;
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bits = <4 2>;
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};
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usb_rterm2: trim@58,4 {
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reg = <0x58 1>;
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bits = <4 2>;
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};
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usb_rterm3: trim@59,4 {
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reg = <0x59 1>;
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bits = <4 2>;
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};
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usb_sel_t0: trim@54,0 {
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reg = <0x54 1>;
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bits = <0 4>;
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};
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usb_sel_t1: trim@55,0 {
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reg = <0x55 1>;
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bits = <0 4>;
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};
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usb_sel_t2: trim@58,0 {
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reg = <0x58 1>;
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bits = <0 4>;
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};
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usb_sel_t3: trim@59,0 {
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reg = <0x59 1>;
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bits = <0 4>;
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};
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usb_hs_i0: trim@56,0 {
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reg = <0x56 1>;
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bits = <0 4>;
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};
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usb_hs_i2: trim@5a,0 {
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reg = <0x5a 1>;
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bits = <0 4>;
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};
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};
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};
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@ -678,6 +722,156 @@
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};
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};
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usb: usb@65a00000 {
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compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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status = "disabled";
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reg = <0x65a00000 0xcd00>;
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interrupt-names = "host";
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interrupts = <0 134 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
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<&pinctrl_usb2>, <&pinctrl_usb3>;
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clock-names = "ref", "bus_early", "suspend";
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clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>;
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resets = <&usb_rst 15>;
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phys = <&usb_hsphy0>, <&usb_hsphy1>,
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<&usb_hsphy2>, <&usb_hsphy3>,
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<&usb_ssphy0>, <&usb_ssphy1>;
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dr_mode = "host";
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};
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usb-glue@65b00000 {
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compatible = "socionext,uniphier-ld20-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb_rst: reset@0 {
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compatible = "socionext,uniphier-ld20-usb3-reset";
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reg = <0x0 0x4>;
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#reset-cells = <1>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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usb_vbus0: regulator@100 {
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compatible = "socionext,uniphier-ld20-usb3-regulator";
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reg = <0x100 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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usb_vbus1: regulator@110 {
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compatible = "socionext,uniphier-ld20-usb3-regulator";
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reg = <0x110 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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usb_vbus2: regulator@120 {
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compatible = "socionext,uniphier-ld20-usb3-regulator";
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reg = <0x120 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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usb_vbus3: regulator@130 {
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compatible = "socionext,uniphier-ld20-usb3-regulator";
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reg = <0x130 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 14>;
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reset-names = "link";
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resets = <&sys_rst 14>;
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};
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usb_hsphy0: hs-phy@200 {
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compatible = "socionext,uniphier-ld20-usb3-hsphy";
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reg = <0x200 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 16>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 16>;
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vbus-supply = <&usb_vbus0>;
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nvmem-cell-names = "rterm", "sel_t", "hs_i";
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nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
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<&usb_hs_i0>;
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};
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usb_hsphy1: hs-phy@210 {
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compatible = "socionext,uniphier-ld20-usb3-hsphy";
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reg = <0x210 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 16>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 16>;
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vbus-supply = <&usb_vbus1>;
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nvmem-cell-names = "rterm", "sel_t", "hs_i";
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nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
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<&usb_hs_i0>;
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};
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usb_hsphy2: hs-phy@220 {
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compatible = "socionext,uniphier-ld20-usb3-hsphy";
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reg = <0x220 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 17>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 17>;
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vbus-supply = <&usb_vbus2>;
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nvmem-cell-names = "rterm", "sel_t", "hs_i";
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nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
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<&usb_hs_i2>;
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};
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usb_hsphy3: hs-phy@230 {
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compatible = "socionext,uniphier-ld20-usb3-hsphy";
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reg = <0x230 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 17>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 17>;
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vbus-supply = <&usb_vbus3>;
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nvmem-cell-names = "rterm", "sel_t", "hs_i";
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nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
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<&usb_hs_i2>;
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};
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usb_ssphy0: ss-phy@300 {
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compatible = "socionext,uniphier-ld20-usb3-ssphy";
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reg = <0x300 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 18>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 18>;
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vbus-supply = <&usb_vbus0>;
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};
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usb_ssphy1: ss-phy@310 {
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compatible = "socionext,uniphier-ld20-usb3-ssphy";
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reg = <0x310 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 14>, <&sys_clk 19>;
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reset-names = "link", "phy";
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resets = <&sys_rst 14>, <&sys_rst 19>;
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vbus-supply = <&usb_vbus1>;
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};
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};
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nand: nand@68000000 {
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compatible = "socionext,uniphier-denali-nand-v5b";
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status = "disabled";
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@ -104,3 +104,11 @@
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&nand {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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@ -406,6 +406,50 @@
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efuse@200 {
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compatible = "socionext,uniphier-efuse";
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reg = <0x200 0x68>;
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#address-cells = <1>;
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#size-cells = <1>;
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/* USB cells */
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usb_rterm0: trim@54,4 {
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reg = <0x54 1>;
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bits = <4 2>;
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};
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usb_rterm1: trim@55,4 {
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reg = <0x55 1>;
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bits = <4 2>;
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};
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usb_rterm2: trim@58,4 {
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reg = <0x58 1>;
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bits = <4 2>;
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};
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usb_rterm3: trim@59,4 {
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reg = <0x59 1>;
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bits = <4 2>;
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};
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usb_sel_t0: trim@54,0 {
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reg = <0x54 1>;
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bits = <0 4>;
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};
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usb_sel_t1: trim@55,0 {
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reg = <0x55 1>;
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bits = <0 4>;
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};
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usb_sel_t2: trim@58,0 {
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reg = <0x58 1>;
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bits = <0 4>;
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};
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usb_sel_t3: trim@59,0 {
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reg = <0x59 1>;
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bits = <0 4>;
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};
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usb_hs_i0: trim@56,0 {
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reg = <0x56 1>;
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bits = <0 4>;
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};
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usb_hs_i2: trim@5a,0 {
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reg = <0x5a 1>;
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bits = <0 4>;
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};
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};
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};
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@ -487,6 +531,202 @@
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};
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};
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usb0: usb@65a00000 {
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compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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status = "disabled";
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reg = <0x65a00000 0xcd00>;
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interrupt-names = "host", "peripheral";
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interrupts = <0 134 4>, <0 135 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
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clock-names = "ref", "bus_early", "suspend";
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clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
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resets = <&usb0_rst 15>;
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phys = <&usb0_hsphy0>, <&usb0_hsphy1>,
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<&usb0_ssphy0>, <&usb0_ssphy1>;
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dr_mode = "host";
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};
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usb-glue@65b00000 {
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compatible = "socionext,uniphier-pxs3-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65b00000 0x400>;
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usb0_rst: reset@0 {
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compatible = "socionext,uniphier-pxs3-usb3-reset";
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reg = <0x0 0x4>;
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#reset-cells = <1>;
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clock-names = "link";
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clocks = <&sys_clk 12>;
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reset-names = "link";
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resets = <&sys_rst 12>;
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};
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usb0_vbus0: regulator@100 {
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compatible = "socionext,uniphier-pxs3-usb3-regulator";
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reg = <0x100 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 12>;
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reset-names = "link";
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resets = <&sys_rst 12>;
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};
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usb0_vbus1: regulator@110 {
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compatible = "socionext,uniphier-pxs3-usb3-regulator";
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reg = <0x110 0x10>;
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clock-names = "link";
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clocks = <&sys_clk 12>;
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reset-names = "link";
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resets = <&sys_rst 12>;
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};
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usb0_hsphy0: hs-phy@200 {
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compatible = "socionext,uniphier-pxs3-usb3-hsphy";
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reg = <0x200 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 12>, <&sys_clk 16>;
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reset-names = "link", "phy";
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resets = <&sys_rst 12>, <&sys_rst 16>;
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vbus-supply = <&usb0_vbus0>;
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nvmem-cell-names = "rterm", "sel_t", "hs_i";
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nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>,
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<&usb_hs_i0>;
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};
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usb0_hsphy1: hs-phy@210 {
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compatible = "socionext,uniphier-pxs3-usb3-hsphy";
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reg = <0x210 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 12>, <&sys_clk 16>;
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reset-names = "link", "phy";
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resets = <&sys_rst 12>, <&sys_rst 16>;
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vbus-supply = <&usb0_vbus1>;
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nvmem-cell-names = "rterm", "sel_t", "hs_i";
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nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>,
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<&usb_hs_i0>;
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};
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usb0_ssphy0: ss-phy@300 {
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compatible = "socionext,uniphier-pxs3-usb3-ssphy";
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reg = <0x300 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 12>, <&sys_clk 17>;
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reset-names = "link", "phy";
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resets = <&sys_rst 12>, <&sys_rst 17>;
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vbus-supply = <&usb0_vbus0>;
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};
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usb0_ssphy1: ss-phy@310 {
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compatible = "socionext,uniphier-pxs3-usb3-ssphy";
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reg = <0x310 0x10>;
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#phy-cells = <0>;
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clock-names = "link", "phy";
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clocks = <&sys_clk 12>, <&sys_clk 18>;
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reset-names = "link", "phy";
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resets = <&sys_rst 12>, <&sys_rst 18>;
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vbus-supply = <&usb0_vbus1>;
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};
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};
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usb1: usb@65c00000 {
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compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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status = "disabled";
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reg = <0x65c00000 0xcd00>;
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interrupt-names = "host", "peripheral";
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interrupts = <0 137 4>, <0 138 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
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clock-names = "ref", "bus_early", "suspend";
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clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>;
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resets = <&usb1_rst 15>;
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phys = <&usb1_hsphy0>, <&usb1_hsphy1>,
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<&usb1_ssphy0>;
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dr_mode = "host";
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};
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usb-glue@65d00000 {
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compatible = "socionext,uniphier-pxs3-dwc3-glue",
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"simple-mfd";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x65d00000 0x400>;
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usb1_rst: reset@0 {
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compatible = "socionext,uniphier-pxs3-usb3-reset";
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reg = <0x0 0x4>;
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#reset-cells = <1>;
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clock-names = "link";
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clocks = <&sys_clk 13>;
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reset-names = "link";
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resets = <&sys_rst 13>;
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};
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usb1_vbus0: regulator@100 {
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compatible = "socionext,uniphier-pxs3-usb3-regulator";
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reg = <0x100 0x10>;
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||||
clock-names = "link";
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clocks = <&sys_clk 13>;
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reset-names = "link";
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resets = <&sys_rst 13>;
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};
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usb1_vbus1: regulator@110 {
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compatible = "socionext,uniphier-pxs3-usb3-regulator";
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reg = <0x110 0x10>;
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clock-names = "link";
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||||
clocks = <&sys_clk 13>;
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reset-names = "link";
|
||||
resets = <&sys_rst 13>;
|
||||
};
|
||||
|
||||
usb1_hsphy0: hs-phy@200 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
||||
reg = <0x200 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy", "phy-ext";
|
||||
clocks = <&sys_clk 13>, <&sys_clk 20>,
|
||||
<&sys_clk 14>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 13>, <&sys_rst 20>;
|
||||
vbus-supply = <&usb1_vbus0>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>,
|
||||
<&usb_hs_i2>;
|
||||
};
|
||||
|
||||
usb1_hsphy1: hs-phy@210 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-hsphy";
|
||||
reg = <0x210 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy", "phy-ext";
|
||||
clocks = <&sys_clk 13>, <&sys_clk 20>,
|
||||
<&sys_clk 14>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 13>, <&sys_rst 20>;
|
||||
vbus-supply = <&usb1_vbus1>;
|
||||
nvmem-cell-names = "rterm", "sel_t", "hs_i";
|
||||
nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>,
|
||||
<&usb_hs_i2>;
|
||||
};
|
||||
|
||||
usb1_ssphy0: ss-phy@300 {
|
||||
compatible = "socionext,uniphier-pxs3-usb3-ssphy";
|
||||
reg = <0x300 0x10>;
|
||||
#phy-cells = <0>;
|
||||
clock-names = "link", "phy", "phy-ext";
|
||||
clocks = <&sys_clk 13>, <&sys_clk 21>,
|
||||
<&sys_clk 14>;
|
||||
reset-names = "link", "phy";
|
||||
resets = <&sys_rst 13>, <&sys_rst 21>;
|
||||
vbus-supply = <&usb1_vbus0>;
|
||||
};
|
||||
};
|
||||
|
||||
nand: nand@68000000 {
|
||||
compatible = "socionext,uniphier-denali-nand-v5b";
|
||||
status = "disabled";
|
||||
|
|
|
|||
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