drm/i915: Allow DRM_ROOT_ONLY|DRM_MASTER to submit privileged batchbuffers
With the introduction of per-process GTT space, the hardware designers thought it wise to also limit the ability to write to MMIO space to only a "secure" batch buffer. The ability to rewrite registers is the only way to program the hardware to perform certain operations like scanline waits (required for tear-free windowed updates). So we either have a choice of adding an interface to perform those synchronized updates inside the kernel, or we permit certain processes the ability to write to the "safe" registers from within its command stream. This patch exposes the ability to submit a SECURE batch buffer to DRM_ROOT_ONLY|DRM_MASTER processes. v2: Haswell split up bit8 into a ppgtt bit (still bit8) and a security bit (bit 13, accidentally not set). Also add a comment explaining why secure batches need a global gtt binding. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> (v1) [danvet: added hsw fixup.] Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Chris Wilson
Daniel Vetter
Родитель
76e4383034
Коммит
d7d4eeddb8
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@ -1015,6 +1015,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
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case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
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value = 1;
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break;
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case I915_PARAM_HAS_SECURE_BATCHES:
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value = capable(CAP_SYS_ADMIN);
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break;
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default:
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DRM_DEBUG_DRIVER("Unknown parameter %d\n",
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param->param);
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@ -801,6 +801,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
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u32 exec_start, exec_len;
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u32 seqno;
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u32 mask;
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u32 flags;
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int ret, mode, i;
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if (!i915_gem_check_execbuffer(args)) {
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@ -812,6 +813,14 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
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if (ret)
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return ret;
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flags = 0;
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if (args->flags & I915_EXEC_SECURE) {
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if (!file->is_master || !capable(CAP_SYS_ADMIN))
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return -EPERM;
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flags |= I915_DISPATCH_SECURE;
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}
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switch (args->flags & I915_EXEC_RING_MASK) {
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case I915_EXEC_DEFAULT:
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case I915_EXEC_RENDER:
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@ -984,6 +993,13 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
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}
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batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
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/* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
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* batch" bit. Hence we need to pin secure batches into the global gtt.
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* hsw should have this fixed, but let's be paranoid and do it
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* unconditionally for now. */
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if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
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i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
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ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
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if (ret)
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goto err;
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@ -1029,7 +1045,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
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goto err;
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}
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trace_i915_gem_ring_dispatch(ring, seqno);
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trace_i915_gem_ring_dispatch(ring, seqno, flags);
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exec_start = batch_obj->gtt_offset + args->batch_start_offset;
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exec_len = args->batch_len;
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@ -1041,12 +1057,15 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
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goto err;
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ret = ring->dispatch_execbuffer(ring,
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exec_start, exec_len);
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exec_start, exec_len,
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flags);
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if (ret)
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goto err;
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}
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} else {
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ret = ring->dispatch_execbuffer(ring, exec_start, exec_len);
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ret = ring->dispatch_execbuffer(ring,
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exec_start, exec_len,
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flags);
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if (ret)
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goto err;
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}
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@ -244,8 +244,11 @@
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#define MI_INVALIDATE_TLB (1<<18)
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#define MI_INVALIDATE_BSD (1<<7)
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#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
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#define MI_BATCH_NON_SECURE (1)
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#define MI_BATCH_NON_SECURE_I965 (1<<8)
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#define MI_BATCH_NON_SECURE (1)
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/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
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#define MI_BATCH_NON_SECURE_I965 (1<<8)
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#define MI_BATCH_PPGTT_HSW (1<<8)
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#define MI_BATCH_NON_SECURE_HSW (1<<13)
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#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
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#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
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#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
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@ -229,24 +229,26 @@ TRACE_EVENT(i915_gem_evict_everything,
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);
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TRACE_EVENT(i915_gem_ring_dispatch,
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TP_PROTO(struct intel_ring_buffer *ring, u32 seqno),
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TP_ARGS(ring, seqno),
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TP_PROTO(struct intel_ring_buffer *ring, u32 seqno, u32 flags),
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TP_ARGS(ring, seqno, flags),
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TP_STRUCT__entry(
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__field(u32, dev)
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__field(u32, ring)
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__field(u32, seqno)
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__field(u32, flags)
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),
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TP_fast_assign(
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__entry->dev = ring->dev->primary->index;
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__entry->ring = ring->id;
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__entry->seqno = seqno;
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__entry->flags = flags;
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i915_trace_irq_get(ring, seqno);
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),
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TP_printk("dev=%u, ring=%u, seqno=%u",
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__entry->dev, __entry->ring, __entry->seqno)
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TP_printk("dev=%u, ring=%u, seqno=%u, flags=%x",
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__entry->dev, __entry->ring, __entry->seqno, __entry->flags)
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);
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TRACE_EVENT(i915_gem_ring_flush,
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@ -965,7 +965,9 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
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}
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static int
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i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
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i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
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u32 offset, u32 length,
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unsigned flags)
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{
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int ret;
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@ -976,7 +978,7 @@ i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
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intel_ring_emit(ring,
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MI_BATCH_BUFFER_START |
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MI_BATCH_GTT |
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MI_BATCH_NON_SECURE_I965);
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(flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
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intel_ring_emit(ring, offset);
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intel_ring_advance(ring);
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@ -985,7 +987,8 @@ i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
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static int
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i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
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u32 offset, u32 len)
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u32 offset, u32 len,
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unsigned flags)
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{
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int ret;
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@ -994,7 +997,7 @@ i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
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return ret;
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intel_ring_emit(ring, MI_BATCH_BUFFER);
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intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
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intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
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intel_ring_emit(ring, offset + len - 8);
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intel_ring_emit(ring, 0);
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intel_ring_advance(ring);
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@ -1004,7 +1007,8 @@ i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
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static int
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i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
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u32 offset, u32 len)
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u32 offset, u32 len,
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unsigned flags)
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{
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int ret;
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@ -1013,7 +1017,7 @@ i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
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return ret;
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intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
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intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
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intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
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intel_ring_advance(ring);
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return 0;
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@ -1403,8 +1407,9 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
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}
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static int
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gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
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u32 offset, u32 len)
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hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
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u32 offset, u32 len,
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unsigned flags)
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{
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int ret;
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@ -1412,7 +1417,30 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
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if (ret)
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return ret;
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intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
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intel_ring_emit(ring,
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MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
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(flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
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/* bit0-7 is the length on GEN6+ */
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intel_ring_emit(ring, offset);
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intel_ring_advance(ring);
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return 0;
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}
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static int
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gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
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u32 offset, u32 len,
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unsigned flags)
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{
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int ret;
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ret = intel_ring_begin(ring, 2);
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if (ret)
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return ret;
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intel_ring_emit(ring,
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MI_BATCH_BUFFER_START |
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(flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
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/* bit0-7 is the length on GEN6+ */
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intel_ring_emit(ring, offset);
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intel_ring_advance(ring);
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@ -1491,7 +1519,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
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ring->irq_enable_mask = I915_USER_INTERRUPT;
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}
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ring->write_tail = ring_write_tail;
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if (INTEL_INFO(dev)->gen >= 6)
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if (IS_HASWELL(dev))
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ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
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else if (INTEL_INFO(dev)->gen >= 6)
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ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
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else if (INTEL_INFO(dev)->gen >= 4)
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ring->dispatch_execbuffer = i965_dispatch_execbuffer;
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@ -81,7 +81,9 @@ struct intel_ring_buffer {
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u32 (*get_seqno)(struct intel_ring_buffer *ring,
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bool lazy_coherency);
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int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
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u32 offset, u32 length);
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u32 offset, u32 length,
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unsigned flags);
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#define I915_DISPATCH_SECURE 0x1
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void (*cleanup)(struct intel_ring_buffer *ring);
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int (*sync_to)(struct intel_ring_buffer *ring,
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struct intel_ring_buffer *to,
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@ -314,6 +314,7 @@ typedef struct drm_i915_irq_wait {
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#define I915_PARAM_HAS_SEMAPHORES 20
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#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
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#define I915_PARAM_RSVD_FOR_FUTURE_USE 22
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#define I915_PARAM_HAS_SECURE_BATCHES 23
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typedef struct drm_i915_getparam {
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int param;
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@ -679,6 +680,11 @@ struct drm_i915_gem_execbuffer2 {
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/** Resets the SO write offset registers for transform feedback on gen7. */
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#define I915_EXEC_GEN7_SOL_RESET (1<<8)
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/** Request a privileged ("secure") batch buffer. Note only available for
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* DRM_ROOT_ONLY | DRM_MASTER processes.
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*/
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#define I915_EXEC_SECURE (1<<9)
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#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
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#define i915_execbuffer2_set_context_id(eb2, context) \
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(eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
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