spi: spi-geni-qcom: Add SPI Device mode support for GENI based QuPv3
Currently spi geni driver supports only master mode operation. Add spi device mode support to GENI based QuPv3. Signed-off-by: Praveen Talari <quic_ptalari@quicinc.com> Reviewed-by: Vijaya Krishna Nivarthi <quic_vnivarth@quicinc.com> Link: https://lore.kernel.org/r/20230714042203.14251-3-quic_ptalari@quicinc.com Signed-off-by: Mark Brown <broonie@kernel.org>
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Коммит
d7f74cc31a
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@ -12,6 +12,7 @@
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#include <linux/platform_device.h>
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#include <linux/pm_opp.h>
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#include <linux/pm_runtime.h>
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#include <linux/property.h>
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#include <linux/soc/qcom/geni-se.h>
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#include <linux/spi/spi.h>
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#include <linux/spinlock.h>
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@ -52,6 +53,9 @@
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#define SPI_CS_CLK_DELAY_MSK GENMASK(19, 10)
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#define SPI_CS_CLK_DELAY_SHFT 10
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#define SE_SPI_SLAVE_EN (0x2BC)
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#define SPI_SLAVE_EN BIT(0)
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/* M_CMD OP codes for SPI */
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#define SPI_TX_ONLY 1
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#define SPI_RX_ONLY 2
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@ -99,6 +103,16 @@ struct spi_geni_master {
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int cur_xfer_mode;
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};
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static void spi_slv_setup(struct spi_geni_master *mas)
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{
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struct geni_se *se = &mas->se;
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writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN);
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writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL);
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writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START);
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dev_dbg(mas->dev, "spi slave setup done\n");
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}
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static int get_spi_clk_cfg(unsigned int speed_hz,
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struct spi_geni_master *mas,
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unsigned int *clk_idx,
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@ -140,12 +154,22 @@ static void handle_se_timeout(struct spi_master *spi,
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const struct spi_transfer *xfer;
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spin_lock_irq(&mas->lock);
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reinit_completion(&mas->cancel_done);
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if (mas->cur_xfer_mode == GENI_SE_FIFO)
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writel(0, se->base + SE_GENI_TX_WATERMARK_REG);
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xfer = mas->cur_xfer;
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mas->cur_xfer = NULL;
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if (spi->slave) {
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/*
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* skip CMD Cancel sequnece since spi slave
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* doesn`t support CMD Cancel sequnece
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*/
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spin_unlock_irq(&mas->lock);
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goto unmap_if_dma;
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}
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reinit_completion(&mas->cancel_done);
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geni_se_cancel_m_cmd(se);
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spin_unlock_irq(&mas->lock);
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@ -542,6 +566,10 @@ static bool geni_can_dma(struct spi_controller *ctlr,
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if (mas->cur_xfer_mode == GENI_GPI_DMA)
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return true;
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/* Set SE DMA mode for SPI slave. */
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if (ctlr->slave)
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return true;
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len = get_xfer_len_in_words(xfer, mas);
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fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word;
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@ -619,6 +647,7 @@ static void spi_geni_release_dma_chan(struct spi_geni_master *mas)
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static int spi_geni_init(struct spi_geni_master *mas)
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{
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struct spi_master *spi = dev_get_drvdata(mas->dev);
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struct geni_se *se = &mas->se;
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unsigned int proto, major, minor, ver;
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u32 spi_tx_cfg, fifo_disable;
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@ -627,7 +656,14 @@ static int spi_geni_init(struct spi_geni_master *mas)
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pm_runtime_get_sync(mas->dev);
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proto = geni_se_read_proto(se);
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if (proto != GENI_SE_SPI) {
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if (spi->slave) {
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if (proto != GENI_SE_SPI_SLAVE) {
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dev_err(mas->dev, "Invalid proto %d\n", proto);
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goto out_pm;
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}
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spi_slv_setup(mas);
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} else if (proto != GENI_SE_SPI) {
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dev_err(mas->dev, "Invalid proto %d\n", proto);
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goto out_pm;
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}
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@ -679,9 +715,11 @@ static int spi_geni_init(struct spi_geni_master *mas)
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}
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/* We always control CS manually */
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spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
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spi_tx_cfg &= ~CS_TOGGLE;
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writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
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if (!spi->slave) {
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spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG);
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spi_tx_cfg &= ~CS_TOGGLE;
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writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG);
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}
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out_pm:
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pm_runtime_put(mas->dev);
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@ -1074,6 +1112,9 @@ static int spi_geni_probe(struct platform_device *pdev)
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pm_runtime_set_autosuspend_delay(&pdev->dev, 250);
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pm_runtime_enable(dev);
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if (device_property_read_bool(&pdev->dev, "spi-slave"))
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spi->slave = true;
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ret = geni_icc_get(&mas->se, NULL);
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if (ret)
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goto spi_geni_probe_runtime_disable;
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@ -1094,7 +1135,7 @@ static int spi_geni_probe(struct platform_device *pdev)
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* for dma (gsi) mode, the gsi will set cs based on params passed in
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* TRE
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*/
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if (mas->cur_xfer_mode == GENI_SE_FIFO)
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if (!spi->slave && mas->cur_xfer_mode == GENI_SE_FIFO)
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spi->set_cs = spi_geni_set_cs;
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/*
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