ARC: Timers/counters/delay management
ARC700 includes 2 in-core 32bit timers TIMER0 and TIMER1.
Both have exactly same capabilies.
* programmable to count from TIMER<n>_CNT to TIMER<n>_LIMIT
* for count 0 and LIMIT ~1, provides a free-running counter by
auto-wrapping when limit is reached.
* optionally interrupt when LIMIT is reached (oneshot event semantics)
* rearming the interrupt provides periodic semantics
* run at CPU clk
ARC Linux uses TIMER0 for clockevent (periodic/oneshot) and TIMER1 for
clocksource (free-running clock).
Newer cores provide RTSC insn which gives a 64bit cpu clk snapshot hence
is more apt for clocksource when available.
SMP poses a bit of challenge for global timekeeping clocksource /
sched_clock() backend:
-TIMER1 based local clocks are out-of-sync hence can't be used
(thus we default to jiffies based cs as well as sched_clock() one/both
of which platform can override with it's specific hardware assist)
-RTSC is only allowed in SMP if it's cross-core-sync (Kconfig glue
ensures that) and thus usable for both requirements.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Vineet Gupta
Родитель
bf90e1eab6
Коммит
d8005e6b95
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@ -47,6 +47,17 @@
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#define AUX_ITRIGGER 0x40d
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#define AUX_IPULSE 0x415
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/* Timer related Aux registers */
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#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
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#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
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#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
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#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
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#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
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#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
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#define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */
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#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
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/*
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* Floating Pt Registers
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* Status regs are read-only (build-time) so need not be saved/restored
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@ -0,0 +1,20 @@
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/*
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* Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_ARC_CLK_H
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#define _ASM_ARC_CLK_H
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/* Although we can't really hide core_freq, the accessor is still better way */
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extern unsigned long core_freq;
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static inline unsigned long arc_get_core_freq(void)
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{
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return core_freq;
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}
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#endif
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@ -0,0 +1,68 @@
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Delay routines using pre computed loops_per_jiffy value.
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*
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* vineetg: Feb 2012
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* -Rewrote in "C" to avoid dealing with availability of H/w MPY
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* -Also reduced the num of MPY operations from 3 to 2
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*
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* Amit Bhor: Codito Technologies 2004
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*/
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#ifndef __ASM_ARC_UDELAY_H
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#define __ASM_ARC_UDELAY_H
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#include <asm/param.h> /* HZ */
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static inline void __delay(unsigned long loops)
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{
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__asm__ __volatile__(
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"1: sub.f %0, %0, 1 \n"
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" jpnz 1b \n"
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: "+r"(loops)
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:
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: "cc");
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}
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extern void __bad_udelay(void);
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/*
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* Normal Math for computing loops in "N" usecs
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* -we have precomputed @loops_per_jiffy
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* -1 sec has HZ jiffies
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* loops per "N" usecs = ((loops_per_jiffy * HZ / 1000000) * N)
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*
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* Approximate Division by multiplication:
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* -Mathematically if we multiply and divide a number by same value the
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* result remains unchanged: In this case, we use 2^32
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* -> (loops_per_N_usec * 2^32 ) / 2^32
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* -> (((loops_per_jiffy * HZ / 1000000) * N) * 2^32) / 2^32
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* -> (loops_per_jiffy * HZ * N * 4295) / 2^32
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*
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* -Divide by 2^32 is very simply right shift by 32
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* -We simply need to ensure that the multiply per above eqn happens in
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* 64-bit precision (if CPU doesn't support it - gcc can emaulate it)
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*/
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static inline void __udelay(unsigned long usecs)
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{
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unsigned long loops;
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/* (long long) cast ensures 64 bit MPY - real or emulated
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* HZ * 4295 is pre-evaluated by gcc - hence only 2 mpy ops
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*/
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loops = ((long long)(usecs * 4295 * HZ) *
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(long long)(loops_per_jiffy)) >> 32;
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__delay(loops);
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}
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#define udelay(n) (__builtin_constant_p(n) ? ((n) > 20000 ? __bad_udelay() \
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: __udelay(n)) : __udelay(n))
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#endif /* __ASM_ARC_UDELAY_H */
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@ -19,4 +19,6 @@ extern void __init arc_init_IRQ(void);
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extern void __init plat_init_IRQ(void);
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extern int __init get_hw_config_num_irq(void);
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void __cpuinit arc_local_timer_setup(unsigned int cpu);
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#endif
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@ -0,0 +1,18 @@
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_ARC_TIMEX_H
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#define _ASM_ARC_TIMEX_H
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#define CLOCK_TICK_RATE 80000000 /* slated to be removed */
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#include <asm-generic/timex.h>
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/* XXX: get_cycles() to be implemented with RTSC insn */
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#endif /* _ASM_ARC_TIMEX_H */
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@ -0,0 +1,11 @@
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/*
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* Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <asm/clk.h>
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unsigned long core_freq = CONFIG_ARC_PLAT_CLK;
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@ -0,0 +1,295 @@
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/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: Jan 1011
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* -sched_clock( ) no longer jiffies based. Uses the same clocksource
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* as gtod
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*
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* Rajeshwarr/Vineetg: Mar 2008
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* -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code)
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* for arch independent gettimeofday()
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* -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers
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*
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* Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c
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*/
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/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1
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* Each can programmed to go from @count to @limit and optionally
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* interrupt when that happens.
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* A write to Control Register clears the Interrupt
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*
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* We've designated TIMER0 for events (clockevents)
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* while TIMER1 for free running (clocksource)
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*
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* Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1
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*/
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/init.h>
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#include <linux/timex.h>
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#include <linux/profile.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <asm/irq.h>
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#include <asm/arcregs.h>
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#include <asm/clk.h>
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#define ARC_TIMER_MAX 0xFFFFFFFF
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/********** Clock Source Device *********/
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#ifdef CONFIG_ARC_HAS_RTSC
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int __cpuinit arc_counter_setup(void)
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{
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/* RTSC insn taps into cpu clk, needs no setup */
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/* For SMP, only allowed if cross-core-sync, hence usable as cs */
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return 1;
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}
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static cycle_t arc_counter_read(struct clocksource *cs)
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{
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unsigned long flags;
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union {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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struct { u32 high, low; };
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#else
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struct { u32 low, high; };
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#endif
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cycle_t full;
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} stamp;
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flags = arch_local_irq_save();
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__asm__ __volatile(
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" .extCoreRegister tsch, 58, r, cannot_shortcut \n"
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" rtsc %0, 0 \n"
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" mov %1, tsch \n" /* TSCH is extn core reg 58 */
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: "=r" (stamp.low), "=r" (stamp.high));
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arch_local_irq_restore(flags);
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return stamp.full;
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}
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static struct clocksource arc_counter = {
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.name = "ARC RTSC",
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.rating = 300,
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.read = arc_counter_read,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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#else /* !CONFIG_ARC_HAS_RTSC */
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static bool is_usable_as_clocksource(void)
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{
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#ifdef CONFIG_SMP
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return 0;
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#else
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return 1;
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#endif
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}
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/*
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* set 32bit TIMER1 to keep counting monotonically and wraparound
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*/
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int __cpuinit arc_counter_setup(void)
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{
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write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
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write_aux_reg(ARC_REG_TIMER1_CNT, 0);
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write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
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return is_usable_as_clocksource();
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}
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static cycle_t arc_counter_read(struct clocksource *cs)
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{
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return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
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}
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static struct clocksource arc_counter = {
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.name = "ARC Timer1",
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.rating = 300,
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.read = arc_counter_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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#endif
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/********** Clock Event Device *********/
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/*
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* Arm the timer to interrupt after @limit cycles
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* The distinction for oneshot/periodic is done in arc_event_timer_ack() below
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*/
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static void arc_timer_event_setup(unsigned int limit)
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{
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write_aux_reg(ARC_REG_TIMER0_LIMIT, limit);
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write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
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write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
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}
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/*
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* Acknowledge the interrupt (oneshot) and optionally re-arm it (periodic)
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* -Any write to CTRL Reg will ack the intr (NH bit: Count when not halted)
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* -Rearming is done by setting the IE bit
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*
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* Small optimisation: Normal code would have been
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* if (irq_reenable)
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* CTRL_REG = (IE | NH);
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* else
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* CTRL_REG = NH;
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* However since IE is BIT0 we can fold the branch
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*/
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static void arc_timer_event_ack(unsigned int irq_reenable)
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{
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write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
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}
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static int arc_clkevent_set_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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arc_timer_event_setup(delta);
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return 0;
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}
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static void arc_clkevent_set_mode(enum clock_event_mode mode,
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struct clock_event_device *dev)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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arc_timer_event_setup(arc_get_core_freq() / HZ);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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break;
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default:
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break;
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}
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return;
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}
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static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
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.name = "ARC Timer0",
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.mode = CLOCK_EVT_MODE_UNUSED,
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.rating = 300,
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.irq = TIMER0_IRQ, /* hardwired, no need for resources */
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.set_next_event = arc_clkevent_set_next_event,
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.set_mode = arc_clkevent_set_mode,
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};
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static irqreturn_t timer_irq_handler(int irq, void *dev_id)
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{
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struct clock_event_device *clk = &__get_cpu_var(arc_clockevent_device);
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arc_timer_event_ack(clk->mode == CLOCK_EVT_MODE_PERIODIC);
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clk->event_handler(clk);
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return IRQ_HANDLED;
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}
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static struct irqaction arc_timer_irq = {
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.name = "Timer0 (clock-evt-dev)",
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.flags = IRQF_TIMER | IRQF_PERCPU,
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.handler = timer_irq_handler,
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};
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/*
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* Setup the local event timer for @cpu
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* N.B. weak so that some exotic ARC SoCs can completely override it
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*/
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void __attribute__((weak)) __cpuinit arc_local_timer_setup(unsigned int cpu)
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{
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struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu);
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clockevents_calc_mult_shift(clk, arc_get_core_freq(), 5);
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clk->max_delta_ns = clockevent_delta2ns(ARC_TIMER_MAX, clk);
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clk->cpumask = cpumask_of(cpu);
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clockevents_register_device(clk);
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/*
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* setup the per-cpu timer IRQ handler - for all cpus
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* For non boot CPU explicitly unmask at intc
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* setup_irq() -> .. -> irq_startup() already does this on boot-cpu
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*/
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if (!cpu)
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setup_irq(TIMER0_IRQ, &arc_timer_irq);
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else
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arch_unmask_irq(TIMER0_IRQ);
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}
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|
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/*
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* Called from start_kernel() - boot CPU only
|
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*
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* -Sets up h/w timers as applicable on boot cpu
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* -Also sets up any global state needed for timer subsystem:
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* - for "counting" timer, registers a clocksource, usable across CPUs
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* (provided that underlying counter h/w is synchronized across cores)
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* - for "event" timer, sets up TIMER0 IRQ (as that is platform agnostic)
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*/
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void __init time_init(void)
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{
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/*
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* sets up the timekeeping free-flowing counter which also returns
|
||||
* whether the counter is usable as clocksource
|
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*/
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if (arc_counter_setup())
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/*
|
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* CLK upto 4.29 GHz can be safely represented in 32 bits
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||||
* because Max 32 bit number is 4,294,967,295
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*/
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clocksource_register_hz(&arc_counter, arc_get_core_freq());
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/* sets up the periodic event timer */
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arc_local_timer_setup(smp_processor_id());
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}
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||||
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||||
#ifdef CONFIG_ARC_HAS_RTSC
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/*
|
||||
* sched_clock math assist
|
||||
* ns = cycles * (ns_per_sec / cpu_freq_hz)
|
||||
* ns = cycles * (10^6 / cpu_freq_khz)
|
||||
* ns = cycles * (10^6 * 2^SF / cpu_freq_khz) / 2^SF
|
||||
* ns = cycles * cyc2ns_scale >> SF
|
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*/
|
||||
#define CYC2NS_SF 10 /* 2^10, carefully chosen */
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#define CYC2NS_SCALE ((1000000 << CYC2NS_SF) / (arc_get_core_freq() / 1000))
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|
||||
static unsigned long long cycles2ns(unsigned long long cyc)
|
||||
{
|
||||
return (cyc * CYC2NS_SCALE ) >> CYC2NS_SF;
|
||||
}
|
||||
|
||||
/*
|
||||
* Scheduler clock - a monotonically increasing clock in nanosec units.
|
||||
* It's return value must NOT wrap around.
|
||||
*
|
||||
* - Since 32bit TIMER1 will overflow almost immediately (53sec @ 80MHz), it
|
||||
* can't be used directly.
|
||||
* - Using getrawmonotonic (TIMER1 based, but with state for last + current
|
||||
* snapshots), is no-good either because of seqlock deadlock possibilities
|
||||
* - So only with native 64bit timer we do this, otherwise fallback to generic
|
||||
* jiffies based version - which despite not being fine grained gaurantees
|
||||
* the monotonically increasing semantics.
|
||||
*/
|
||||
unsigned long long sched_clock(void)
|
||||
{
|
||||
return cycles2ns(arc_counter_read(NULL));
|
||||
}
|
||||
#endif
|
||||
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