bnx2: Set rx buffer water marks based on MTU.
The default rx buffer water marks for XOFF/XON are for 1500 MTU. At larger MTUs, these water marks need to be adjusted for effective flow control. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Коммит
d8026d9394
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@ -4473,7 +4473,7 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
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static int
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static int
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bnx2_init_chip(struct bnx2 *bp)
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bnx2_init_chip(struct bnx2 *bp)
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{
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{
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u32 val;
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u32 val, mtu;
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int rc, i;
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int rc, i;
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/* Make sure the interrupt is not active. */
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/* Make sure the interrupt is not active. */
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@ -4565,11 +4565,19 @@ bnx2_init_chip(struct bnx2 *bp)
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REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
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REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
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/* Program the MTU. Also include 4 bytes for CRC32. */
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/* Program the MTU. Also include 4 bytes for CRC32. */
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val = bp->dev->mtu + ETH_HLEN + 4;
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mtu = bp->dev->mtu;
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val = mtu + ETH_HLEN + ETH_FCS_LEN;
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if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
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if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
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val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
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val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
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REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
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REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
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if (mtu < 1500)
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mtu = 1500;
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bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
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bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
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bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
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for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
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for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
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bp->bnx2_napi[i].last_status_idx = 0;
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bp->bnx2_napi[i].last_status_idx = 0;
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@ -4199,7 +4199,14 @@ struct l2_fhdr {
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#define BNX2_RBUF_CONFIG 0x0020000c
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#define BNX2_RBUF_CONFIG 0x0020000c
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#define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
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#define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
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#define BNX2_RBUF_CONFIG_XOFF_TRIP_VAL(mtu) \
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((((mtu) - 1500) * 31 / 1000) + 54)
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#define BNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
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#define BNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
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#define BNX2_RBUF_CONFIG_XON_TRIP_VAL(mtu) \
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((((mtu) - 1500) * 39 / 1000) + 66)
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#define BNX2_RBUF_CONFIG_VAL(mtu) \
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(BNX2_RBUF_CONFIG_XOFF_TRIP_VAL(mtu) | \
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(BNX2_RBUF_CONFIG_XON_TRIP_VAL(mtu) << 16))
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#define BNX2_RBUF_FW_BUF_ALLOC 0x00200010
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#define BNX2_RBUF_FW_BUF_ALLOC 0x00200010
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#define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
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#define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
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@ -4221,11 +4228,25 @@ struct l2_fhdr {
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#define BNX2_RBUF_CONFIG2 0x0020001c
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#define BNX2_RBUF_CONFIG2 0x0020001c
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#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
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#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
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#define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP_VAL(mtu) \
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((((mtu) - 1500) * 4 / 1000) + 5)
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#define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
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#define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
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#define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP_VAL(mtu) \
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((((mtu) - 1500) * 2 / 100) + 30)
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#define BNX2_RBUF_CONFIG2_VAL(mtu) \
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(BNX2_RBUF_CONFIG2_MAC_DROP_TRIP_VAL(mtu) | \
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(BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP_VAL(mtu) << 16))
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#define BNX2_RBUF_CONFIG3 0x00200020
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#define BNX2_RBUF_CONFIG3 0x00200020
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#define BNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
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#define BNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
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#define BNX2_RBUF_CONFIG3_CU_DROP_TRIP_VAL(mtu) \
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((((mtu) - 1500) * 12 / 1000) + 18)
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#define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
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#define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
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#define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP_VAL(mtu) \
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((((mtu) - 1500) * 2 / 100) + 30)
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#define BNX2_RBUF_CONFIG3_VAL(mtu) \
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(BNX2_RBUF_CONFIG3_CU_DROP_TRIP_VAL(mtu) | \
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(BNX2_RBUF_CONFIG3_CU_KEEP_TRIP_VAL(mtu) << 16))
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#define BNX2_RBUF_PKT_DATA 0x00208000
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#define BNX2_RBUF_PKT_DATA 0x00208000
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#define BNX2_RBUF_CLIST_DATA 0x00210000
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#define BNX2_RBUF_CLIST_DATA 0x00210000
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