KVM: arm64: PMU: Allow ID_DFR0_EL1.PerfMon to be set from userspace
Allow userspace to write ID_DFR0_EL1, on the condition that only the PerfMon field can be altered and be something that is compatible with what was computed for the AArch64 view of the guest. Reviewed-by: Reiji Watanabe <reijiw@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20221113163832.3154370-13-maz@kernel.org
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@ -1070,6 +1070,19 @@ static u8 vcpu_pmuver(const struct kvm_vcpu *vcpu)
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return vcpu->kvm->arch.dfr0_pmuver.unimp;
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}
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static u8 perfmon_to_pmuver(u8 perfmon)
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{
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switch (perfmon) {
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case ID_DFR0_PERFMON_8_0:
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return ID_AA64DFR0_EL1_PMUVer_IMP;
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case ID_DFR0_PERFMON_IMP_DEF:
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return ID_AA64DFR0_EL1_PMUVer_IMP_DEF;
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default:
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/* Anything ARMv8.1+ and NI have the same value. For now. */
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return perfmon;
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}
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}
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static u8 pmuver_to_perfmon(u8 pmuver)
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{
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switch (pmuver) {
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@ -1281,6 +1294,46 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
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return 0;
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}
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static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
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const struct sys_reg_desc *rd,
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u64 val)
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{
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u8 perfmon, host_perfmon;
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bool valid_pmu;
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host_perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
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/*
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* Allow DFR0_EL1.PerfMon to be set from userspace as long as
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* it doesn't promise more than what the HW gives us on the
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* AArch64 side (as everything is emulated with that), and
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* that this is a PMUv3.
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*/
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perfmon = FIELD_GET(ARM64_FEATURE_MASK(ID_DFR0_PERFMON), val);
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if ((perfmon != ID_DFR0_PERFMON_IMP_DEF && perfmon > host_perfmon) ||
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(perfmon != 0 && perfmon < ID_DFR0_PERFMON_8_0))
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return -EINVAL;
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valid_pmu = (perfmon != 0 && perfmon != ID_DFR0_PERFMON_IMP_DEF);
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/* Make sure view register and PMU support do match */
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if (kvm_vcpu_has_pmu(vcpu) != valid_pmu)
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return -EINVAL;
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/* We can only differ with PerfMon, and anything else is an error */
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val ^= read_id_reg(vcpu, rd);
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val &= ~ARM64_FEATURE_MASK(ID_DFR0_PERFMON);
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if (val)
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return -EINVAL;
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if (valid_pmu)
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vcpu->kvm->arch.dfr0_pmuver.imp = perfmon_to_pmuver(perfmon);
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else
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vcpu->kvm->arch.dfr0_pmuver.unimp = perfmon_to_pmuver(perfmon);
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return 0;
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}
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/*
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* cpufeature ID register user accessors
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*
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@ -1502,7 +1555,9 @@ static const struct sys_reg_desc sys_reg_descs[] = {
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/* CRm=1 */
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AA32_ID_SANITISED(ID_PFR0_EL1),
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AA32_ID_SANITISED(ID_PFR1_EL1),
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AA32_ID_SANITISED(ID_DFR0_EL1),
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{ SYS_DESC(SYS_ID_DFR0_EL1), .access = access_id_reg,
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.get_user = get_id_reg, .set_user = set_id_dfr0_el1,
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.visibility = aa32_id_visibility, },
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ID_HIDDEN(ID_AFR0_EL1),
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AA32_ID_SANITISED(ID_MMFR0_EL1),
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AA32_ID_SANITISED(ID_MMFR1_EL1),
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