ARM: sunxi: dt: Add sample and output mmc clocks
Add the sample and output clocks for the MMC phase support. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org>
This commit is contained in:
Maxime Ripard
Родитель
6b0b8ccff0
Коммит
d8c3a392a5
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@ -226,35 +226,43 @@
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0";
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clock-output-names = "mmc0",
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"mmc0_output",
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"mmc0_sample";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc1";
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clock-output-names = "mmc1",
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"mmc1_output",
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"mmc1_sample";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc2";
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clock-output-names = "mmc2",
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"mmc2_output",
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"mmc2_sample";
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};
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mmc3_clk: clk@01c20094 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20094 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc3";
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clock-output-names = "mmc3",
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"mmc3_output",
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"mmc3_sample";
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};
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ts_clk: clk@01c20098 {
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@ -398,8 +406,14 @@
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun4i-a10-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ahb_gates 8>, <&mmc0_clk>;
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clock-names = "ahb", "mmc";
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clocks = <&ahb_gates 8>,
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<&mmc0_clk 0>,
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<&mmc0_clk 1>,
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<&mmc0_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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interrupts = <32>;
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status = "disabled";
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};
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@ -407,8 +421,14 @@
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mmc1: mmc@01c10000 {
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compatible = "allwinner,sun4i-a10-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ahb_gates 9>, <&mmc1_clk>;
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clock-names = "ahb", "mmc";
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clocks = <&ahb_gates 9>,
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<&mmc1_clk 0>,
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<&mmc1_clk 1>,
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<&mmc1_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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interrupts = <33>;
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status = "disabled";
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};
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@ -416,8 +436,14 @@
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mmc2: mmc@01c11000 {
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compatible = "allwinner,sun4i-a10-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ahb_gates 10>, <&mmc2_clk>;
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clock-names = "ahb", "mmc";
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clocks = <&ahb_gates 10>,
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<&mmc2_clk 0>,
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<&mmc2_clk 1>,
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<&mmc2_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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interrupts = <34>;
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status = "disabled";
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};
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@ -425,8 +451,14 @@
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mmc3: mmc@01c12000 {
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compatible = "allwinner,sun4i-a10-mmc";
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reg = <0x01c12000 0x1000>;
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clocks = <&ahb_gates 11>, <&mmc3_clk>;
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clock-names = "ahb", "mmc";
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clocks = <&ahb_gates 11>,
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<&mmc3_clk 0>,
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<&mmc3_clk 1>,
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<&mmc3_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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interrupts = <35>;
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status = "disabled";
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};
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@ -211,27 +211,33 @@
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0";
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clock-output-names = "mmc0",
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"mmc0_output",
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"mmc0_sample";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc1";
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clock-output-names = "mmc1",
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"mmc1_output",
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"mmc1_sample";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc2";
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clock-output-names = "mmc2",
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"mmc2_output",
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"mmc2_sample";
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};
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ts_clk: clk@01c20098 {
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@ -359,8 +365,14 @@
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ahb_gates 8>, <&mmc0_clk>;
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clock-names = "ahb", "mmc";
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clocks = <&ahb_gates 8>,
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<&mmc0_clk 0>,
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<&mmc0_clk 1>,
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<&mmc0_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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interrupts = <32>;
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status = "disabled";
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};
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@ -368,8 +380,14 @@
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mmc1: mmc@01c10000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ahb_gates 9>, <&mmc1_clk>;
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clock-names = "ahb", "mmc";
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clocks = <&ahb_gates 9>,
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<&mmc1_clk 0>,
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<&mmc1_clk 1>,
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<&mmc1_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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interrupts = <33>;
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status = "disabled";
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};
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@ -377,8 +395,14 @@
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mmc2: mmc@01c11000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ahb_gates 10>, <&mmc2_clk>;
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clock-names = "ahb", "mmc";
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clocks = <&ahb_gates 10>,
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<&mmc2_clk 0>,
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<&mmc2_clk 1>,
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<&mmc2_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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interrupts = <34>;
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status = "disabled";
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};
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@ -195,27 +195,33 @@
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0";
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clock-output-names = "mmc0",
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"mmc0_output",
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"mmc0_sample";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc1";
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clock-output-names = "mmc1",
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"mmc1_output",
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"mmc1_sample";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc2";
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clock-output-names = "mmc2",
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"mmc2_output",
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"mmc2_sample";
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};
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ts_clk: clk@01c20098 {
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@ -327,8 +333,14 @@
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ahb_gates 8>, <&mmc0_clk>;
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clock-names = "ahb", "mmc";
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clocks = <&ahb_gates 8>,
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<&mmc0_clk 0>,
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<&mmc0_clk 1>,
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<&mmc0_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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interrupts = <32>;
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status = "disabled";
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};
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@ -336,8 +348,14 @@
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mmc2: mmc@01c11000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ahb_gates 10>, <&mmc2_clk>;
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clock-names = "ahb", "mmc";
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clocks = <&ahb_gates 10>,
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<&mmc2_clk 0>,
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<&mmc2_clk 1>,
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<&mmc2_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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interrupts = <34>;
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status = "disabled";
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};
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@ -241,35 +241,43 @@
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "mmc0";
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clock-output-names = "mmc0",
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"mmc0_output",
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"mmc0_sample";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "mmc1";
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clock-output-names = "mmc1",
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"mmc1_output",
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"mmc1_sample";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "mmc2";
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clock-output-names = "mmc2",
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"mmc2_output",
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"mmc2_sample";
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};
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mmc3_clk: clk@01c20094 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-mod0-clk";
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20094 0x4>;
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clocks = <&osc24M>, <&pll6 0>;
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clock-output-names = "mmc3";
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clock-output-names = "mmc3",
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"mmc3_output",
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"mmc3_sample";
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};
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spi0_clk: clk@01c200a0 {
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@ -366,8 +374,14 @@
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ahb1_gates 8>, <&mmc0_clk>;
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clock-names = "ahb", "mmc";
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clocks = <&ahb1_gates 8>,
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<&mmc0_clk 0>,
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<&mmc0_clk 1>,
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<&mmc0_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ahb1_rst 8>;
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reset-names = "ahb";
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interrupts = <0 60 4>;
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@ -377,8 +391,14 @@
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mmc1: mmc@01c10000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ahb1_gates 9>, <&mmc1_clk>;
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clock-names = "ahb", "mmc";
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clocks = <&ahb1_gates 9>,
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<&mmc1_clk 0>,
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<&mmc1_clk 1>,
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<&mmc1_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ahb1_rst 9>;
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reset-names = "ahb";
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interrupts = <0 61 4>;
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@ -388,8 +408,14 @@
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mmc2: mmc@01c11000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ahb1_gates 10>, <&mmc2_clk>;
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clock-names = "ahb", "mmc";
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clocks = <&ahb1_gates 10>,
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<&mmc2_clk 0>,
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<&mmc2_clk 1>,
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<&mmc2_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ahb1_rst 10>;
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reset-names = "ahb";
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interrupts = <0 62 4>;
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@ -399,8 +425,14 @@
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mmc3: mmc@01c12000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c12000 0x1000>;
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clocks = <&ahb1_gates 11>, <&mmc3_clk>;
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clock-names = "ahb", "mmc";
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clocks = <&ahb1_gates 11>,
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<&mmc3_clk 0>,
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<&mmc3_clk 1>,
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<&mmc3_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ahb1_rst 11>;
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reset-names = "ahb";
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interrupts = <0 63 4>;
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@ -274,35 +274,43 @@
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <0>;
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||||
compatible = "allwinner,sun4i-a10-mod0-clk";
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||||
#clock-cells = <1>;
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||||
compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "mmc0";
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||||
clock-output-names = "mmc0",
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"mmc0_output",
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"mmc0_sample";
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||||
};
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||||
|
||||
mmc1_clk: clk@01c2008c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-mmc-clk";
|
||||
reg = <0x01c2008c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc1";
|
||||
clock-output-names = "mmc1",
|
||||
"mmc1_output",
|
||||
"mmc1_sample";
|
||||
};
|
||||
|
||||
mmc2_clk: clk@01c20090 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-mmc-clk";
|
||||
reg = <0x01c20090 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc2";
|
||||
clock-output-names = "mmc2",
|
||||
"mmc2_output",
|
||||
"mmc2_sample";
|
||||
};
|
||||
|
||||
mmc3_clk: clk@01c20094 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-mmc-clk";
|
||||
reg = <0x01c20094 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
|
||||
clock-output-names = "mmc3";
|
||||
clock-output-names = "mmc3",
|
||||
"mmc3_output",
|
||||
"mmc3_sample";
|
||||
};
|
||||
|
||||
ts_clk: clk@01c20098 {
|
||||
|
|
@ -518,8 +526,14 @@
|
|||
mmc0: mmc@01c0f000 {
|
||||
compatible = "allwinner,sun5i-a13-mmc";
|
||||
reg = <0x01c0f000 0x1000>;
|
||||
clocks = <&ahb_gates 8>, <&mmc0_clk>;
|
||||
clock-names = "ahb", "mmc";
|
||||
clocks = <&ahb_gates 8>,
|
||||
<&mmc0_clk 0>,
|
||||
<&mmc0_clk 1>,
|
||||
<&mmc0_clk 2>;
|
||||
clock-names = "ahb",
|
||||
"mmc",
|
||||
"output",
|
||||
"sample";
|
||||
interrupts = <0 32 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -527,8 +541,14 @@
|
|||
mmc1: mmc@01c10000 {
|
||||
compatible = "allwinner,sun5i-a13-mmc";
|
||||
reg = <0x01c10000 0x1000>;
|
||||
clocks = <&ahb_gates 9>, <&mmc1_clk>;
|
||||
clock-names = "ahb", "mmc";
|
||||
clocks = <&ahb_gates 9>,
|
||||
<&mmc1_clk 0>,
|
||||
<&mmc1_clk 1>,
|
||||
<&mmc1_clk 2>;
|
||||
clock-names = "ahb",
|
||||
"mmc",
|
||||
"output",
|
||||
"sample";
|
||||
interrupts = <0 33 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -536,8 +556,14 @@
|
|||
mmc2: mmc@01c11000 {
|
||||
compatible = "allwinner,sun5i-a13-mmc";
|
||||
reg = <0x01c11000 0x1000>;
|
||||
clocks = <&ahb_gates 10>, <&mmc2_clk>;
|
||||
clock-names = "ahb", "mmc";
|
||||
clocks = <&ahb_gates 10>,
|
||||
<&mmc2_clk 0>,
|
||||
<&mmc2_clk 1>,
|
||||
<&mmc2_clk 2>;
|
||||
clock-names = "ahb",
|
||||
"mmc",
|
||||
"output",
|
||||
"sample";
|
||||
interrupts = <0 34 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
@ -545,8 +571,14 @@
|
|||
mmc3: mmc@01c12000 {
|
||||
compatible = "allwinner,sun5i-a13-mmc";
|
||||
reg = <0x01c12000 0x1000>;
|
||||
clocks = <&ahb_gates 11>, <&mmc3_clk>;
|
||||
clock-names = "ahb", "mmc";
|
||||
clocks = <&ahb_gates 11>,
|
||||
<&mmc3_clk 0>,
|
||||
<&mmc3_clk 1>,
|
||||
<&mmc3_clk 2>;
|
||||
clock-names = "ahb",
|
||||
"mmc",
|
||||
"output",
|
||||
"sample";
|
||||
interrupts = <0 35 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -209,27 +209,33 @@
|
|||
};
|
||||
|
||||
mmc0_clk: clk@01c20088 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-mmc-clk";
|
||||
reg = <0x01c20088 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 0>;
|
||||
clock-output-names = "mmc0";
|
||||
clock-output-names = "mmc0",
|
||||
"mmc0_output",
|
||||
"mmc0_sample";
|
||||
};
|
||||
|
||||
mmc1_clk: clk@01c2008c {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-mmc-clk";
|
||||
reg = <0x01c2008c 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 0>;
|
||||
clock-output-names = "mmc1";
|
||||
clock-output-names = "mmc1",
|
||||
"mmc1_output",
|
||||
"mmc1_sample";
|
||||
};
|
||||
|
||||
mmc2_clk: clk@01c20090 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-a10-mod0-clk";
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-a10-mmc-clk";
|
||||
reg = <0x01c20090 0x4>;
|
||||
clocks = <&osc24M>, <&pll6 0>;
|
||||
clock-output-names = "mmc2";
|
||||
clock-output-names = "mmc2",
|
||||
"mmc2_output",
|
||||
"mmc2_sample";
|
||||
};
|
||||
|
||||
mbus_clk: clk@01c2015c {
|
||||
|
|
@ -259,8 +265,14 @@
|
|||
mmc0: mmc@01c0f000 {
|
||||
compatible = "allwinner,sun5i-a13-mmc";
|
||||
reg = <0x01c0f000 0x1000>;
|
||||
clocks = <&ahb1_gates 8>, <&mmc0_clk>;
|
||||
clock-names = "ahb", "mmc";
|
||||
clocks = <&ahb1_gates 8>,
|
||||
<&mmc0_clk 0>,
|
||||
<&mmc0_clk 1>,
|
||||
<&mmc0_clk 2>;
|
||||
clock-names = "ahb",
|
||||
"mmc",
|
||||
"output",
|
||||
"sample";
|
||||
resets = <&ahb1_rst 8>;
|
||||
reset-names = "ahb";
|
||||
interrupts = <0 60 4>;
|
||||
|
|
@ -270,8 +282,14 @@
|
|||
mmc1: mmc@01c10000 {
|
||||
compatible = "allwinner,sun5i-a13-mmc";
|
||||
reg = <0x01c10000 0x1000>;
|
||||
clocks = <&ahb1_gates 9>, <&mmc1_clk>;
|
||||
clock-names = "ahb", "mmc";
|
||||
clocks = <&ahb1_gates 9>,
|
||||
<&mmc1_clk 0>,
|
||||
<&mmc1_clk 1>,
|
||||
<&mmc1_clk 2>;
|
||||
clock-names = "ahb",
|
||||
"mmc",
|
||||
"output",
|
||||
"sample";
|
||||
resets = <&ahb1_rst 9>;
|
||||
reset-names = "ahb";
|
||||
interrupts = <0 61 4>;
|
||||
|
|
@ -281,8 +299,14 @@
|
|||
mmc2: mmc@01c11000 {
|
||||
compatible = "allwinner,sun5i-a13-mmc";
|
||||
reg = <0x01c11000 0x1000>;
|
||||
clocks = <&ahb1_gates 10>, <&mmc2_clk>;
|
||||
clock-names = "ahb", "mmc";
|
||||
clocks = <&ahb1_gates 10>,
|
||||
<&mmc2_clk 0>,
|
||||
<&mmc2_clk 1>,
|
||||
<&mmc2_clk 2>;
|
||||
clock-names = "ahb",
|
||||
"mmc",
|
||||
"output",
|
||||
"sample";
|
||||
resets = <&ahb1_rst 10>;
|
||||
reset-names = "ahb";
|
||||
interrupts = <0 62 4>;
|
||||
|
|
|
|||
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