coresight-etm4x: Controls pertaining to the reset, mode, pe and events
Adding sysfs entries to: . set the tracing entity with default values. . set various mode associated to the tracing entity. . select the processing entity the tracing entity relates to. . select various events of interest. Signed-off-by: Pratik Patel <pratikp@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Pratik Patel
Greg Kroah-Hartman
Родитель
c0ddbfea72
Коммит
d8c6696208
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@ -75,3 +75,36 @@ KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (R) Indicates the number of single-shot comparator controls that
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are available for tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/reset
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (W) Cancels all configuration on a trace unit and set it back
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to its boot configuration.
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What: /sys/bus/coresight/devices/<memory_map>.etm/mode
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls various modes supported by this ETM, for example
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P0 instruction tracing, branch broadcast, cycle counting and
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context ID tracing.
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What: /sys/bus/coresight/devices/<memory_map>.etm/pe
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls which PE to trace.
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What: /sys/bus/coresight/devices/<memory_map>.etm/event
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls the tracing of arbitrary events from bank 0 to 3.
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What: /sys/bus/coresight/devices/<memory_map>.etm/event_instren
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Date: April 2015
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KernelVersion: 4.01
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Contact: Mathieu Poirier <mathieu.poirier@linaro.org>
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Description: (RW) Controls the behavior of the events in bank 0 to 3.
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@ -268,6 +268,46 @@ static const struct coresight_ops etm4_cs_ops = {
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.source_ops = &etm4_source_ops,
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};
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static int etm4_set_mode_exclude(struct etmv4_drvdata *drvdata, bool exclude)
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{
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u8 idx = drvdata->addr_idx;
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/*
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* TRCACATRn.TYPE bit[1:0]: type of comparison
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* the trace unit performs
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*/
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if (BMVAL(drvdata->addr_acc[idx], 0, 1) == ETM_INSTR_ADDR) {
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if (idx % 2 != 0)
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return -EINVAL;
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/*
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* We are performing instruction address comparison. Set the
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* relevant bit of ViewInst Include/Exclude Control register
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* for corresponding address comparator pair.
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*/
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if (drvdata->addr_type[idx] != ETM_ADDR_TYPE_RANGE ||
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drvdata->addr_type[idx + 1] != ETM_ADDR_TYPE_RANGE)
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return -EINVAL;
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if (exclude == true) {
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/*
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* Set exclude bit and unset the include bit
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* corresponding to comparator pair
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*/
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drvdata->viiectlr |= BIT(idx / 2 + 16);
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drvdata->viiectlr &= ~BIT(idx / 2);
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} else {
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/*
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* Set include bit and unset exclude bit
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* corresponding to comparator pair
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*/
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drvdata->viiectlr |= BIT(idx / 2);
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drvdata->viiectlr &= ~BIT(idx / 2 + 16);
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}
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}
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return 0;
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}
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static ssize_t nr_pe_cmp_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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@ -376,6 +416,402 @@ static ssize_t nr_ss_cmp_show(struct device *dev,
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}
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static DEVICE_ATTR_RO(nr_ss_cmp);
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static ssize_t reset_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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int i;
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unsigned long val;
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struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
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if (kstrtoul(buf, 16, &val))
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return -EINVAL;
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spin_lock(&drvdata->spinlock);
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if (val)
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drvdata->mode = 0x0;
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/* Disable data tracing: do not trace load and store data transfers */
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drvdata->mode &= ~(ETM_MODE_LOAD | ETM_MODE_STORE);
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drvdata->cfg &= ~(BIT(1) | BIT(2));
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/* Disable data value and data address tracing */
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drvdata->mode &= ~(ETM_MODE_DATA_TRACE_ADDR |
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ETM_MODE_DATA_TRACE_VAL);
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drvdata->cfg &= ~(BIT(16) | BIT(17));
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/* Disable all events tracing */
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drvdata->eventctrl0 = 0x0;
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drvdata->eventctrl1 = 0x0;
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/* Disable timestamp event */
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drvdata->ts_ctrl = 0x0;
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/* Disable stalling */
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drvdata->stall_ctrl = 0x0;
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/* Reset trace synchronization period to 2^8 = 256 bytes*/
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if (drvdata->syncpr == false)
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drvdata->syncfreq = 0x8;
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/*
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* Enable ViewInst to trace everything with start-stop logic in
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* started state. ARM recommends start-stop logic is set before
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* each trace run.
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*/
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drvdata->vinst_ctrl |= BIT(0);
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if (drvdata->nr_addr_cmp == true) {
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drvdata->mode |= ETM_MODE_VIEWINST_STARTSTOP;
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/* SSSTATUS, bit[9] */
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drvdata->vinst_ctrl |= BIT(9);
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}
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/* No address range filtering for ViewInst */
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drvdata->viiectlr = 0x0;
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/* No start-stop filtering for ViewInst */
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drvdata->vissctlr = 0x0;
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/* Disable seq events */
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for (i = 0; i < drvdata->nrseqstate-1; i++)
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drvdata->seq_ctrl[i] = 0x0;
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drvdata->seq_rst = 0x0;
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drvdata->seq_state = 0x0;
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/* Disable external input events */
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drvdata->ext_inp = 0x0;
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drvdata->cntr_idx = 0x0;
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for (i = 0; i < drvdata->nr_cntr; i++) {
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drvdata->cntrldvr[i] = 0x0;
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drvdata->cntr_ctrl[i] = 0x0;
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drvdata->cntr_val[i] = 0x0;
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}
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drvdata->res_idx = 0x0;
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for (i = 0; i < drvdata->nr_resource; i++)
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drvdata->res_ctrl[i] = 0x0;
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for (i = 0; i < drvdata->nr_ss_cmp; i++) {
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drvdata->ss_ctrl[i] = 0x0;
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drvdata->ss_pe_cmp[i] = 0x0;
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}
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drvdata->addr_idx = 0x0;
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for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
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drvdata->addr_val[i] = 0x0;
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drvdata->addr_acc[i] = 0x0;
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drvdata->addr_type[i] = ETM_ADDR_TYPE_NONE;
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}
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drvdata->ctxid_idx = 0x0;
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for (i = 0; i < drvdata->numcidc; i++)
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drvdata->ctxid_val[i] = 0x0;
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drvdata->ctxid_mask0 = 0x0;
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drvdata->ctxid_mask1 = 0x0;
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drvdata->vmid_idx = 0x0;
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for (i = 0; i < drvdata->numvmidc; i++)
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drvdata->vmid_val[i] = 0x0;
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drvdata->vmid_mask0 = 0x0;
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drvdata->vmid_mask1 = 0x0;
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drvdata->trcid = drvdata->cpu + 1;
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spin_unlock(&drvdata->spinlock);
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return size;
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}
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static DEVICE_ATTR_WO(reset);
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static ssize_t mode_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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unsigned long val;
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struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
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val = drvdata->mode;
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return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
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}
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static ssize_t mode_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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unsigned long val, mode;
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struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
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if (kstrtoul(buf, 16, &val))
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return -EINVAL;
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spin_lock(&drvdata->spinlock);
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drvdata->mode = val & ETMv4_MODE_ALL;
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if (drvdata->mode & ETM_MODE_EXCLUDE)
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etm4_set_mode_exclude(drvdata, true);
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else
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etm4_set_mode_exclude(drvdata, false);
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if (drvdata->instrp0 == true) {
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/* start by clearing instruction P0 field */
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drvdata->cfg &= ~(BIT(1) | BIT(2));
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if (drvdata->mode & ETM_MODE_LOAD)
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/* 0b01 Trace load instructions as P0 instructions */
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drvdata->cfg |= BIT(1);
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if (drvdata->mode & ETM_MODE_STORE)
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/* 0b10 Trace store instructions as P0 instructions */
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drvdata->cfg |= BIT(2);
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if (drvdata->mode & ETM_MODE_LOAD_STORE)
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/*
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* 0b11 Trace load and store instructions
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* as P0 instructions
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*/
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drvdata->cfg |= BIT(1) | BIT(2);
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}
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/* bit[3], Branch broadcast mode */
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if ((drvdata->mode & ETM_MODE_BB) && (drvdata->trcbb == true))
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drvdata->cfg |= BIT(3);
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else
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drvdata->cfg &= ~BIT(3);
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/* bit[4], Cycle counting instruction trace bit */
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if ((drvdata->mode & ETMv4_MODE_CYCACC) &&
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(drvdata->trccci == true))
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drvdata->cfg |= BIT(4);
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else
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drvdata->cfg &= ~BIT(4);
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/* bit[6], Context ID tracing bit */
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if ((drvdata->mode & ETMv4_MODE_CTXID) && (drvdata->ctxid_size))
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drvdata->cfg |= BIT(6);
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else
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drvdata->cfg &= ~BIT(6);
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if ((drvdata->mode & ETM_MODE_VMID) && (drvdata->vmid_size))
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drvdata->cfg |= BIT(7);
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else
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drvdata->cfg &= ~BIT(7);
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/* bits[10:8], Conditional instruction tracing bit */
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mode = ETM_MODE_COND(drvdata->mode);
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if (drvdata->trccond == true) {
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drvdata->cfg &= ~(BIT(8) | BIT(9) | BIT(10));
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drvdata->cfg |= mode << 8;
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}
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/* bit[11], Global timestamp tracing bit */
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if ((drvdata->mode & ETMv4_MODE_TIMESTAMP) && (drvdata->ts_size))
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drvdata->cfg |= BIT(11);
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else
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drvdata->cfg &= ~BIT(11);
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/* bit[12], Return stack enable bit */
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if ((drvdata->mode & ETM_MODE_RETURNSTACK) &&
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(drvdata->retstack == true))
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drvdata->cfg |= BIT(12);
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else
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drvdata->cfg &= ~BIT(12);
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/* bits[14:13], Q element enable field */
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mode = ETM_MODE_QELEM(drvdata->mode);
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/* start by clearing QE bits */
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drvdata->cfg &= ~(BIT(13) | BIT(14));
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/* if supported, Q elements with instruction counts are enabled */
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if ((mode & BIT(0)) && (drvdata->q_support & BIT(0)))
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drvdata->cfg |= BIT(13);
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/*
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* if supported, Q elements with and without instruction
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* counts are enabled
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*/
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if ((mode & BIT(1)) && (drvdata->q_support & BIT(1)))
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drvdata->cfg |= BIT(14);
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/* bit[11], AMBA Trace Bus (ATB) trigger enable bit */
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if ((drvdata->mode & ETM_MODE_ATB_TRIGGER) &&
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(drvdata->atbtrig == true))
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drvdata->eventctrl1 |= BIT(11);
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else
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drvdata->eventctrl1 &= ~BIT(11);
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/* bit[12], Low-power state behavior override bit */
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if ((drvdata->mode & ETM_MODE_LPOVERRIDE) &&
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(drvdata->lpoverride == true))
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drvdata->eventctrl1 |= BIT(12);
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else
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drvdata->eventctrl1 &= ~BIT(12);
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/* bit[8], Instruction stall bit */
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if (drvdata->mode & ETM_MODE_ISTALL_EN)
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drvdata->stall_ctrl |= BIT(8);
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else
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drvdata->stall_ctrl &= ~BIT(8);
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/* bit[10], Prioritize instruction trace bit */
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if (drvdata->mode & ETM_MODE_INSTPRIO)
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drvdata->stall_ctrl |= BIT(10);
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else
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drvdata->stall_ctrl &= ~BIT(10);
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/* bit[13], Trace overflow prevention bit */
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if ((drvdata->mode & ETM_MODE_NOOVERFLOW) &&
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(drvdata->nooverflow == true))
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drvdata->stall_ctrl |= BIT(13);
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else
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drvdata->stall_ctrl &= ~BIT(13);
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/* bit[9] Start/stop logic control bit */
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if (drvdata->mode & ETM_MODE_VIEWINST_STARTSTOP)
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drvdata->vinst_ctrl |= BIT(9);
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else
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drvdata->vinst_ctrl &= ~BIT(9);
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/* bit[10], Whether a trace unit must trace a Reset exception */
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if (drvdata->mode & ETM_MODE_TRACE_RESET)
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drvdata->vinst_ctrl |= BIT(10);
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else
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drvdata->vinst_ctrl &= ~BIT(10);
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/* bit[11], Whether a trace unit must trace a system error exception */
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if ((drvdata->mode & ETM_MODE_TRACE_ERR) &&
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(drvdata->trc_error == true))
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drvdata->vinst_ctrl |= BIT(11);
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else
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drvdata->vinst_ctrl &= ~BIT(11);
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spin_unlock(&drvdata->spinlock);
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return size;
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}
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static DEVICE_ATTR_RW(mode);
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static ssize_t pe_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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unsigned long val;
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struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
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val = drvdata->pe_sel;
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return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
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}
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static ssize_t pe_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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unsigned long val;
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struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
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if (kstrtoul(buf, 16, &val))
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return -EINVAL;
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spin_lock(&drvdata->spinlock);
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if (val > drvdata->nr_pe) {
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spin_unlock(&drvdata->spinlock);
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return -EINVAL;
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}
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drvdata->pe_sel = val;
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spin_unlock(&drvdata->spinlock);
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return size;
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}
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static DEVICE_ATTR_RW(pe);
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static ssize_t event_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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unsigned long val;
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struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
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val = drvdata->eventctrl0;
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return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
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}
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static ssize_t event_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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{
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unsigned long val;
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struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
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if (kstrtoul(buf, 16, &val))
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return -EINVAL;
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spin_lock(&drvdata->spinlock);
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switch (drvdata->nr_event) {
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case 0x0:
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/* EVENT0, bits[7:0] */
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drvdata->eventctrl0 = val & 0xFF;
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break;
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case 0x1:
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/* EVENT1, bits[15:8] */
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drvdata->eventctrl0 = val & 0xFFFF;
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break;
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case 0x2:
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/* EVENT2, bits[23:16] */
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drvdata->eventctrl0 = val & 0xFFFFFF;
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break;
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case 0x3:
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/* EVENT3, bits[31:24] */
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drvdata->eventctrl0 = val;
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break;
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default:
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break;
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}
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spin_unlock(&drvdata->spinlock);
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return size;
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}
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static DEVICE_ATTR_RW(event);
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static ssize_t event_instren_show(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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unsigned long val;
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struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
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val = BMVAL(drvdata->eventctrl1, 0, 3);
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return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
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}
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static ssize_t event_instren_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t size)
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||||
{
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unsigned long val;
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struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
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||||
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if (kstrtoul(buf, 16, &val))
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return -EINVAL;
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spin_lock(&drvdata->spinlock);
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/* start by clearing all instruction event enable bits */
|
||||
drvdata->eventctrl1 &= ~(BIT(0) | BIT(1) | BIT(2) | BIT(3));
|
||||
switch (drvdata->nr_event) {
|
||||
case 0x0:
|
||||
/* generate Event element for event 1 */
|
||||
drvdata->eventctrl1 |= val & BIT(1);
|
||||
break;
|
||||
case 0x1:
|
||||
/* generate Event element for event 1 and 2 */
|
||||
drvdata->eventctrl1 |= val & (BIT(0) | BIT(1));
|
||||
break;
|
||||
case 0x2:
|
||||
/* generate Event element for event 1, 2 and 3 */
|
||||
drvdata->eventctrl1 |= val & (BIT(0) | BIT(1) | BIT(2));
|
||||
break;
|
||||
case 0x3:
|
||||
/* generate Event element for all 4 events */
|
||||
drvdata->eventctrl1 |= val & 0xF;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
spin_unlock(&drvdata->spinlock);
|
||||
return size;
|
||||
}
|
||||
static DEVICE_ATTR_RW(event_instren);
|
||||
|
||||
static ssize_t cpu_show(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
|
|
@ -398,6 +834,11 @@ static struct attribute *coresight_etmv4_attrs[] = {
|
|||
&dev_attr_nrseqstate.attr,
|
||||
&dev_attr_nr_resource.attr,
|
||||
&dev_attr_nr_ss_cmp.attr,
|
||||
&dev_attr_reset.attr,
|
||||
&dev_attr_mode.attr,
|
||||
&dev_attr_pe.attr,
|
||||
&dev_attr_event.attr,
|
||||
&dev_attr_event_instren.attr,
|
||||
&dev_attr_cpu.attr,
|
||||
NULL,
|
||||
};
|
||||
|
|
|
|||
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Ссылка в новой задаче