CRIS: add pgprot_noncached
On CRIS, the high address bit controls caching, which means that we can add a pgprot_noncached() macro that sets this bit in the address. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
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@ -33,10 +33,10 @@ typedef struct
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/* CRIS PTE bits (see R_TLB_LO in the register description)
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*
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* Bit: 31-13 12-------4 3 2 1 0
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* ________________________________________________
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* | pfn | reserved | global | valid | kernel | we |
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* |_____|__________|________|_______|________|_____|
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* Bit: 31 30-13 12-------4 3 2 1 0
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* _______________________________________________________
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* | cache |pfn | reserved | global | valid | kernel | we |
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* |_______|____|__________|________|_______|________|_____|
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*
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* (pfn = physical frame number)
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*/
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@ -53,6 +53,7 @@ typedef struct
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#define _PAGE_VALID (1<<2) /* page is valid */
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#define _PAGE_SILENT_READ (1<<2) /* synonym */
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#define _PAGE_GLOBAL (1<<3) /* global page - context is ignored */
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#define _PAGE_NO_CACHE (1<<31) /* part of the uncached memory map */
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/* Bits the HW doesn't care about but the kernel uses them in SW */
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@ -28,10 +28,10 @@ typedef struct
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/*
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* CRISv32 PTE bits:
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*
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* Bit: 31-13 12-5 4 3 2 1 0
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* +-----+------+--------+-------+--------+-------+---------+
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* | pfn | zero | global | valid | kernel | write | execute |
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* +-----+------+--------+-------+--------+-------+---------+
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* Bit: 31 30-13 12-5 4 3 2 1 0
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* +-------+-----+------+--------+-------+--------+-------+---------+
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* | cache | pfn | zero | global | valid | kernel | write | execute |
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* +-------+-----+------+--------+-------+--------+-------+---------+
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*/
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/*
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@ -45,6 +45,8 @@ typedef struct
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#define _PAGE_VALID (1 << 3) /* Page is valid. */
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#define _PAGE_SILENT_READ (1 << 3) /* Same as above. */
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#define _PAGE_GLOBAL (1 << 4) /* Global page. */
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#define _PAGE_NO_CACHE (1 << 31) /* part of the uncached memory map */
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/*
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* The hardware doesn't care about these bits, but the kernel uses them in
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@ -197,6 +197,8 @@ static inline pte_t __mk_pte(void * page, pgprot_t pgprot)
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
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#define pgprot_noncached(prot) __pgprot((pgprot_val(prot) | _PAGE_NO_CACHE))
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/* pte_val refers to a page in the 0x4xxxxxxx physical DRAM interval
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* __pte_page(pte_val) refers to the "virtual" DRAM interval
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