rtc: support for the Amlogic Meson RTC
Add support for the RTC block on the 32-bit Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs. The RTC is split in to two parts, which are both managed by this driver: - the AHB front end - and a simple serial connection to the actual registers The RTC_COUNTER register which holds the time is 32-bits wide. There are four 32-bit wide (in total: 16 bytes) "regmem" registers which are exposed using nvmem. On Amlogic's 3.10 kernel this is used to store data which needs to survive a suspend / resume cycle. Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> [resurrected Ben's patches after 2 years] Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Martin Blumenstingl
Alexandre Belloni
Родитель
1366e010ad
Коммит
d8fe6009aa
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@ -1294,6 +1294,17 @@ config RTC_DRV_IMXDI
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This driver can also be built as a module, if so, the module
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will be called "rtc-imxdi".
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config RTC_DRV_MESON
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tristate "Amlogic Meson RTC"
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depends on (ARM && ARCH_MESON) || COMPILE_TEST
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select REGMAP_MMIO
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help
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Support for the RTC block on the Amlogic Meson6, Meson8, Meson8b
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and Meson8m2 SoCs.
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This driver can also be built as a module, if so, the module
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will be called "rtc-meson".
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config RTC_DRV_OMAP
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tristate "TI OMAP Real Time Clock"
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depends on ARCH_OMAP || ARCH_DAVINCI || COMPILE_TEST
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@ -101,6 +101,7 @@ obj-$(CONFIG_RTC_DRV_MAX8997) += rtc-max8997.o
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obj-$(CONFIG_RTC_DRV_MAX8998) += rtc-max8998.o
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obj-$(CONFIG_RTC_DRV_MC13XXX) += rtc-mc13xxx.o
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obj-$(CONFIG_RTC_DRV_MCP795) += rtc-mcp795.o
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obj-$(CONFIG_RTC_DRV_MESON) += rtc-meson.o
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obj-$(CONFIG_RTC_DRV_MOXART) += rtc-moxart.o
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obj-$(CONFIG_RTC_DRV_MPC5121) += rtc-mpc5121.o
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obj-$(CONFIG_RTC_DRV_MSM6242) += rtc-msm6242.o
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@ -0,0 +1,410 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* RTC driver for the interal RTC block in the Amlogic Meson6, Meson8,
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* Meson8b and Meson8m2 SoCs.
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*
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* The RTC is split in to two parts, the AHB front end and a simple serial
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* connection to the actual registers. This driver manages both parts.
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*
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* Copyright (c) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Copyright (c) 2015 Ben Dooks <ben.dooks@codethink.co.uk> for Codethink Ltd
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* Based on origin by Carlo Caione <carlo@endlessm.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/rtc.h>
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/* registers accessed from cpu bus */
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#define RTC_ADDR0 0x00
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#define RTC_ADDR0_LINE_SCLK BIT(0)
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#define RTC_ADDR0_LINE_SEN BIT(1)
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#define RTC_ADDR0_LINE_SDI BIT(2)
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#define RTC_ADDR0_START_SER BIT(17)
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#define RTC_ADDR0_WAIT_SER BIT(22)
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#define RTC_ADDR0_DATA GENMASK(31, 24)
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#define RTC_ADDR1 0x04
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#define RTC_ADDR1_SDO BIT(0)
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#define RTC_ADDR1_S_READY BIT(1)
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#define RTC_ADDR2 0x08
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#define RTC_ADDR3 0x0c
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#define RTC_REG4 0x10
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#define RTC_REG4_STATIC_VALUE GENMASK(7, 0)
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/* rtc registers accessed via rtc-serial interface */
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#define RTC_COUNTER (0)
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#define RTC_SEC_ADJ (2)
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#define RTC_REGMEM_0 (4)
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#define RTC_REGMEM_1 (5)
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#define RTC_REGMEM_2 (6)
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#define RTC_REGMEM_3 (7)
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#define RTC_ADDR_BITS (3) /* number of address bits to send */
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#define RTC_DATA_BITS (32) /* number of data bits to tx/rx */
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#define MESON_STATIC_BIAS_CUR (0x5 << 1)
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#define MESON_STATIC_VOLTAGE (0x3 << 11)
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#define MESON_STATIC_DEFAULT (MESON_STATIC_BIAS_CUR | MESON_STATIC_VOLTAGE)
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struct meson_rtc {
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struct rtc_device *rtc; /* rtc device we created */
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struct device *dev; /* device we bound from */
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struct reset_control *reset; /* reset source */
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struct regulator *vdd; /* voltage input */
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struct regmap *peripheral; /* peripheral registers */
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struct regmap *serial; /* serial registers */
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};
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static const struct regmap_config meson_rtc_peripheral_regmap_config = {
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.name = "peripheral-registers",
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.reg_bits = 8,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = RTC_REG4,
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.fast_io = true,
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};
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/* RTC front-end serialiser controls */
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static void meson_rtc_sclk_pulse(struct meson_rtc *rtc)
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{
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udelay(5);
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regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SCLK, 0);
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udelay(5);
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regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SCLK,
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RTC_ADDR0_LINE_SCLK);
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}
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static void meson_rtc_send_bit(struct meson_rtc *rtc, unsigned int bit)
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{
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regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI,
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bit ? RTC_ADDR0_LINE_SDI : 0);
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meson_rtc_sclk_pulse(rtc);
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}
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static void meson_rtc_send_bits(struct meson_rtc *rtc, u32 data,
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unsigned int nr)
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{
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u32 bit = 1 << (nr - 1);
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while (bit) {
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meson_rtc_send_bit(rtc, data & bit);
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bit >>= 1;
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}
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}
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static void meson_rtc_set_dir(struct meson_rtc *rtc, u32 mode)
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{
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regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN, 0);
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regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI, 0);
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meson_rtc_send_bit(rtc, mode);
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regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SDI, 0);
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}
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static u32 meson_rtc_get_data(struct meson_rtc *rtc)
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{
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u32 tmp, val = 0;
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int bit;
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for (bit = 0; bit < RTC_DATA_BITS; bit++) {
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meson_rtc_sclk_pulse(rtc);
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val <<= 1;
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regmap_read(rtc->peripheral, RTC_ADDR1, &tmp);
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val |= tmp & RTC_ADDR1_SDO;
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}
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return val;
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}
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static int meson_rtc_get_bus(struct meson_rtc *rtc)
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{
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int ret, retries = 3;
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u32 val;
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/* prepare bus for transfers, set all lines low */
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val = RTC_ADDR0_LINE_SDI | RTC_ADDR0_LINE_SEN | RTC_ADDR0_LINE_SCLK;
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regmap_update_bits(rtc->peripheral, RTC_ADDR0, val, 0);
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for (retries = 0; retries < 3; retries++) {
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/* wait for the bus to be ready */
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if (!regmap_read_poll_timeout(rtc->peripheral, RTC_ADDR1, val,
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val & RTC_ADDR1_S_READY, 10,
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10000))
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return 0;
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dev_warn(rtc->dev, "failed to get bus, resetting RTC\n");
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ret = reset_control_reset(rtc->reset);
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if (ret)
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return ret;
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}
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dev_err(rtc->dev, "bus is not ready\n");
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return -ETIMEDOUT;
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}
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static int meson_rtc_serial_bus_reg_read(void *context, unsigned int reg,
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unsigned int *data)
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{
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struct meson_rtc *rtc = context;
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int ret;
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ret = meson_rtc_get_bus(rtc);
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if (ret)
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return ret;
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regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN,
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RTC_ADDR0_LINE_SEN);
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meson_rtc_send_bits(rtc, reg, RTC_ADDR_BITS);
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meson_rtc_set_dir(rtc, 0);
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*data = meson_rtc_get_data(rtc);
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return 0;
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}
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static int meson_rtc_serial_bus_reg_write(void *context, unsigned int reg,
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unsigned int data)
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{
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struct meson_rtc *rtc = context;
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int ret;
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ret = meson_rtc_get_bus(rtc);
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if (ret)
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return ret;
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regmap_update_bits(rtc->peripheral, RTC_ADDR0, RTC_ADDR0_LINE_SEN,
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RTC_ADDR0_LINE_SEN);
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meson_rtc_send_bits(rtc, data, RTC_DATA_BITS);
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meson_rtc_send_bits(rtc, reg, RTC_ADDR_BITS);
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meson_rtc_set_dir(rtc, 1);
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return 0;
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}
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static const struct regmap_bus meson_rtc_serial_bus = {
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.reg_read = meson_rtc_serial_bus_reg_read,
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.reg_write = meson_rtc_serial_bus_reg_write,
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};
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static const struct regmap_config meson_rtc_serial_regmap_config = {
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.name = "serial-registers",
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.reg_bits = 4,
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.reg_stride = 1,
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.val_bits = 32,
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.max_register = RTC_REGMEM_3,
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.fast_io = false,
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};
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static int meson_rtc_write_static(struct meson_rtc *rtc, u32 data)
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{
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u32 tmp;
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regmap_write(rtc->peripheral, RTC_REG4,
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FIELD_PREP(RTC_REG4_STATIC_VALUE, (data >> 8)));
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/* write the static value and start the auto serializer */
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tmp = FIELD_PREP(RTC_ADDR0_DATA, (data & 0xff)) | RTC_ADDR0_START_SER;
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regmap_update_bits(rtc->peripheral, RTC_ADDR0,
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RTC_ADDR0_DATA | RTC_ADDR0_START_SER, tmp);
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/* wait for the auto serializer to complete */
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return regmap_read_poll_timeout(rtc->peripheral, RTC_REG4, tmp,
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!(tmp & RTC_ADDR0_WAIT_SER), 10,
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10000);
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}
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/* RTC interface layer functions */
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static int meson_rtc_gettime(struct device *dev, struct rtc_time *tm)
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{
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struct meson_rtc *rtc = dev_get_drvdata(dev);
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u32 time;
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int ret;
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ret = regmap_read(rtc->serial, RTC_COUNTER, &time);
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if (!ret)
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rtc_time64_to_tm(time, tm);
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return ret;
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}
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static int meson_rtc_settime(struct device *dev, struct rtc_time *tm)
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{
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struct meson_rtc *rtc = dev_get_drvdata(dev);
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return regmap_write(rtc->serial, RTC_COUNTER, rtc_tm_to_time64(tm));
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}
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static const struct rtc_class_ops meson_rtc_ops = {
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.read_time = meson_rtc_gettime,
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.set_time = meson_rtc_settime,
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};
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/* NVMEM interface layer functions */
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static int meson_rtc_regmem_read(void *context, unsigned int offset,
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void *buf, size_t bytes)
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{
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struct meson_rtc *rtc = context;
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unsigned int read_offset, read_size;
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read_offset = RTC_REGMEM_0 + (offset / 4);
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read_size = bytes / 4;
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return regmap_bulk_read(rtc->serial, read_offset, buf, read_size);
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}
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static int meson_rtc_regmem_write(void *context, unsigned int offset,
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void *buf, size_t bytes)
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{
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struct meson_rtc *rtc = context;
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unsigned int write_offset, write_size;
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write_offset = RTC_REGMEM_0 + (offset / 4);
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write_size = bytes / 4;
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return regmap_bulk_write(rtc->serial, write_offset, buf, write_size);
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}
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static int meson_rtc_probe(struct platform_device *pdev)
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{
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struct nvmem_config meson_rtc_nvmem_config = {
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.name = "meson-rtc-regmem",
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.type = NVMEM_TYPE_BATTERY_BACKED,
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.word_size = 4,
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.stride = 4,
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.size = 4 * 4,
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.reg_read = meson_rtc_regmem_read,
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.reg_write = meson_rtc_regmem_write,
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};
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struct device *dev = &pdev->dev;
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struct meson_rtc *rtc;
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struct resource *res;
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void __iomem *base;
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int ret;
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u32 tm;
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rtc = devm_kzalloc(dev, sizeof(struct meson_rtc), GFP_KERNEL);
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if (!rtc)
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return -ENOMEM;
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rtc->rtc = devm_rtc_allocate_device(dev);
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if (IS_ERR(rtc->rtc))
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return PTR_ERR(rtc->rtc);
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platform_set_drvdata(pdev, rtc);
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rtc->dev = dev;
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rtc->rtc->ops = &meson_rtc_ops;
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rtc->rtc->range_max = U32_MAX;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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base = devm_ioremap_resource(dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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rtc->peripheral = devm_regmap_init_mmio(dev, base,
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&meson_rtc_peripheral_regmap_config);
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if (IS_ERR(rtc->peripheral)) {
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dev_err(dev, "failed to create peripheral regmap\n");
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return PTR_ERR(rtc->peripheral);
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}
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rtc->reset = devm_reset_control_get(dev, NULL);
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if (IS_ERR(rtc->reset)) {
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dev_err(dev, "missing reset line\n");
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return PTR_ERR(rtc->reset);
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}
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rtc->vdd = devm_regulator_get(dev, "vdd");
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if (IS_ERR(rtc->vdd)) {
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dev_err(dev, "failed to get the vdd-supply\n");
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return PTR_ERR(rtc->vdd);
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}
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ret = regulator_enable(rtc->vdd);
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if (ret) {
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dev_err(dev, "failed to enable vdd-supply\n");
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return ret;
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}
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ret = meson_rtc_write_static(rtc, MESON_STATIC_DEFAULT);
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if (ret) {
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dev_err(dev, "failed to set static values\n");
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goto out_disable_vdd;
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}
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rtc->serial = devm_regmap_init(dev, &meson_rtc_serial_bus, rtc,
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&meson_rtc_serial_regmap_config);
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if (IS_ERR(rtc->serial)) {
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dev_err(dev, "failed to create serial regmap\n");
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ret = PTR_ERR(rtc->serial);
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goto out_disable_vdd;
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}
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/*
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* check if we can read RTC counter, if not then the RTC is probably
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* not functional. If it isn't probably best to not bind.
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*/
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ret = regmap_read(rtc->serial, RTC_COUNTER, &tm);
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if (ret) {
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dev_err(dev, "cannot read RTC counter, RTC not functional\n");
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goto out_disable_vdd;
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}
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meson_rtc_nvmem_config.priv = rtc;
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ret = rtc_nvmem_register(rtc->rtc, &meson_rtc_nvmem_config);
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if (ret)
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goto out_disable_vdd;
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ret = rtc_register_device(rtc->rtc);
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if (ret)
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goto out_unregister_nvmem;
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return 0;
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out_unregister_nvmem:
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rtc_nvmem_unregister(rtc->rtc);
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out_disable_vdd:
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regulator_disable(rtc->vdd);
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return ret;
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}
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static const struct of_device_id meson_rtc_dt_match[] = {
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{ .compatible = "amlogic,meson6-rtc", },
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{ .compatible = "amlogic,meson8-rtc", },
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{ .compatible = "amlogic,meson8b-rtc", },
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{ .compatible = "amlogic,meson8m2-rtc", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, meson_rtc_dt_match);
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static struct platform_driver meson_rtc_driver = {
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.probe = meson_rtc_probe,
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.driver = {
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.name = "meson-rtc",
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.of_match_table = of_match_ptr(meson_rtc_dt_match),
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},
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};
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module_platform_driver(meson_rtc_driver);
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MODULE_DESCRIPTION("Amlogic Meson RTC Driver");
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MODULE_AUTHOR("Ben Dooks <ben.doosk@codethink.co.uk>");
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MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:meson-rtc");
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