svga: Make svga_wseq_mask() take an iomem regbase pointer.
Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Родитель
a4ade83948
Коммит
d907ec04cc
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@ -649,7 +649,7 @@ static int arkfb_set_par(struct fb_info *info)
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svga_wcrt_mask(0x11, 0x00, 0x80);
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/* Blank screen and turn off sync */
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svga_wseq_mask(0x01, 0x20, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
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svga_wcrt_mask(0x17, 0x00, 0x80);
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/* Set default values */
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@ -661,8 +661,8 @@ static int arkfb_set_par(struct fb_info *info)
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svga_wcrt_multi(par->state.vgabase, ark_start_address_regs, 0);
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/* ARK specific initialization */
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svga_wseq_mask(0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
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svga_wseq_mask(0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
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svga_wseq_mask(par->state.vgabase, 0x10, 0x1F, 0x1F); /* enable linear framebuffer and full memory access */
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svga_wseq_mask(par->state.vgabase, 0x12, 0x03, 0x03); /* 4 MB linear framebuffer size */
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vga_wseq(NULL, 0x13, info->fix.smem_start >> 16);
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vga_wseq(NULL, 0x14, info->fix.smem_start >> 24);
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@ -787,7 +787,7 @@ static int arkfb_set_par(struct fb_info *info)
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memset_io(info->screen_base, 0x00, screen_size);
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/* Device and screen back on */
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svga_wcrt_mask(0x17, 0x80, 0x80);
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svga_wseq_mask(0x01, 0x00, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
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return 0;
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}
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@ -857,22 +857,24 @@ static int arkfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
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static int arkfb_blank(int blank_mode, struct fb_info *info)
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{
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struct arkfb_info *par = info->par;
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switch (blank_mode) {
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case FB_BLANK_UNBLANK:
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pr_debug("fb%d: unblank\n", info->node);
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svga_wseq_mask(0x01, 0x00, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
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svga_wcrt_mask(0x17, 0x80, 0x80);
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break;
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case FB_BLANK_NORMAL:
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pr_debug("fb%d: blank\n", info->node);
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svga_wseq_mask(0x01, 0x20, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
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svga_wcrt_mask(0x17, 0x80, 0x80);
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break;
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case FB_BLANK_POWERDOWN:
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case FB_BLANK_HSYNC_SUSPEND:
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case FB_BLANK_VSYNC_SUSPEND:
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pr_debug("fb%d: sync down\n", info->node);
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svga_wseq_mask(0x01, 0x20, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
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svga_wcrt_mask(0x17, 0x00, 0x80);
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break;
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}
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@ -510,7 +510,7 @@ static int s3fb_set_par(struct fb_info *info)
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svga_wcrt_mask(0x11, 0x00, 0x80);
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/* Blank screen and turn off sync */
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svga_wseq_mask(0x01, 0x20, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
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svga_wcrt_mask(0x17, 0x00, 0x80);
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/* Set default values */
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@ -700,8 +700,8 @@ static int s3fb_set_par(struct fb_info *info)
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}
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if (par->chip != CHIP_988_VIRGE_VX) {
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svga_wseq_mask(0x15, multiplex ? 0x10 : 0x00, 0x10);
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svga_wseq_mask(0x18, multiplex ? 0x80 : 0x00, 0x80);
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svga_wseq_mask(par->state.vgabase, 0x15, multiplex ? 0x10 : 0x00, 0x10);
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svga_wseq_mask(par->state.vgabase, 0x18, multiplex ? 0x80 : 0x00, 0x80);
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}
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s3_set_pixclock(info, info->var.pixclock);
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@ -718,7 +718,7 @@ static int s3fb_set_par(struct fb_info *info)
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memset_io(info->screen_base, 0x00, screen_size);
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/* Device and screen back on */
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svga_wcrt_mask(0x17, 0x80, 0x80);
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svga_wseq_mask(0x01, 0x00, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
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return 0;
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}
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@ -788,31 +788,33 @@ static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
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static int s3fb_blank(int blank_mode, struct fb_info *info)
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{
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struct s3fb_info *par = info->par;
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switch (blank_mode) {
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case FB_BLANK_UNBLANK:
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pr_debug("fb%d: unblank\n", info->node);
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svga_wcrt_mask(0x56, 0x00, 0x06);
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svga_wseq_mask(0x01, 0x00, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
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break;
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case FB_BLANK_NORMAL:
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pr_debug("fb%d: blank\n", info->node);
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svga_wcrt_mask(0x56, 0x00, 0x06);
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svga_wseq_mask(0x01, 0x20, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
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break;
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case FB_BLANK_HSYNC_SUSPEND:
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pr_debug("fb%d: hsync\n", info->node);
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svga_wcrt_mask(0x56, 0x02, 0x06);
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svga_wseq_mask(0x01, 0x20, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
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break;
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case FB_BLANK_VSYNC_SUSPEND:
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pr_debug("fb%d: vsync\n", info->node);
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svga_wcrt_mask(0x56, 0x04, 0x06);
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svga_wseq_mask(0x01, 0x20, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
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break;
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case FB_BLANK_POWERDOWN:
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pr_debug("fb%d: sync down\n", info->node);
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svga_wcrt_mask(0x56, 0x06, 0x06);
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svga_wseq_mask(0x01, 0x20, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
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break;
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}
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@ -139,7 +139,7 @@ void svga_set_default_crt_regs(void)
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void svga_set_textmode_vga_regs(void)
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{
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/* svga_wseq_mask(0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */
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/* svga_wseq_mask(NULL, 0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */
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vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM);
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vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, 0x03);
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@ -253,6 +253,7 @@ static void vt8623fb_fillrect(struct fb_info *info, const struct fb_fillrect *re
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static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock)
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{
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struct vt8623fb_info *par = info->par;
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u16 m, n, r;
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u8 regval;
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int rv;
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@ -274,8 +275,8 @@ static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock)
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udelay(1000);
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/* PLL reset */
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svga_wseq_mask(0x40, 0x02, 0x02);
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svga_wseq_mask(0x40, 0x00, 0x02);
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svga_wseq_mask(par->state.vgabase, 0x40, 0x02, 0x02);
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svga_wseq_mask(par->state.vgabase, 0x40, 0x00, 0x02);
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}
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@ -415,12 +416,12 @@ static int vt8623fb_set_par(struct fb_info *info)
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info->var.activate = FB_ACTIVATE_NOW;
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/* Unlock registers */
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svga_wseq_mask(0x10, 0x01, 0x01);
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svga_wseq_mask(par->state.vgabase, 0x10, 0x01, 0x01);
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svga_wcrt_mask(0x11, 0x00, 0x80);
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svga_wcrt_mask(0x47, 0x00, 0x01);
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/* Device, screen and sync off */
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svga_wseq_mask(0x01, 0x20, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
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svga_wcrt_mask(0x36, 0x30, 0x30);
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svga_wcrt_mask(0x17, 0x00, 0x80);
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@ -444,12 +445,12 @@ static int vt8623fb_set_par(struct fb_info *info)
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else
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svga_wcrt_mask(0x09, 0x00, 0x80);
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svga_wseq_mask(0x1E, 0xF0, 0xF0); // DI/DVP bus
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svga_wseq_mask(0x2A, 0x0F, 0x0F); // DI/DVP bus
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svga_wseq_mask(0x16, 0x08, 0xBF); // FIFO read threshold
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svga_wseq_mask(par->state.vgabase, 0x1E, 0xF0, 0xF0); // DI/DVP bus
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svga_wseq_mask(par->state.vgabase, 0x2A, 0x0F, 0x0F); // DI/DVP bus
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svga_wseq_mask(par->state.vgabase, 0x16, 0x08, 0xBF); // FIFO read threshold
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vga_wseq(NULL, 0x17, 0x1F); // FIFO depth
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vga_wseq(NULL, 0x18, 0x4E);
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svga_wseq_mask(0x1A, 0x08, 0x08); // enable MMIO ?
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svga_wseq_mask(par->state.vgabase, 0x1A, 0x08, 0x08); // enable MMIO ?
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vga_wcrt(NULL, 0x32, 0x00);
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vga_wcrt(NULL, 0x34, 0x00);
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@ -466,31 +467,31 @@ static int vt8623fb_set_par(struct fb_info *info)
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case 0:
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pr_debug("fb%d: text mode\n", info->node);
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svga_set_textmode_vga_regs();
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svga_wseq_mask(0x15, 0x00, 0xFE);
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svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
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svga_wcrt_mask(0x11, 0x60, 0x70);
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break;
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case 1:
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pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
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vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
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svga_wseq_mask(0x15, 0x20, 0xFE);
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svga_wseq_mask(par->state.vgabase, 0x15, 0x20, 0xFE);
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svga_wcrt_mask(0x11, 0x00, 0x70);
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break;
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case 2:
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pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
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svga_wseq_mask(0x15, 0x00, 0xFE);
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svga_wseq_mask(par->state.vgabase, 0x15, 0x00, 0xFE);
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svga_wcrt_mask(0x11, 0x00, 0x70);
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break;
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case 3:
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pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
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svga_wseq_mask(0x15, 0x22, 0xFE);
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svga_wseq_mask(par->state.vgabase, 0x15, 0x22, 0xFE);
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break;
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case 4:
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pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
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svga_wseq_mask(0x15, 0xB6, 0xFE);
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svga_wseq_mask(par->state.vgabase, 0x15, 0xB6, 0xFE);
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break;
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case 5:
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pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
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svga_wseq_mask(0x15, 0xAE, 0xFE);
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svga_wseq_mask(par->state.vgabase, 0x15, 0xAE, 0xFE);
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break;
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default:
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printk(KERN_ERR "vt8623fb: unsupported mode - bug\n");
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@ -507,7 +508,7 @@ static int vt8623fb_set_par(struct fb_info *info)
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/* Device and screen back on */
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svga_wcrt_mask(0x17, 0x80, 0x80);
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svga_wcrt_mask(0x36, 0x00, 0x30);
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svga_wseq_mask(0x01, 0x00, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
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return 0;
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}
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@ -570,31 +571,33 @@ static int vt8623fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
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static int vt8623fb_blank(int blank_mode, struct fb_info *info)
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{
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struct vt8623fb_info *par = info->par;
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switch (blank_mode) {
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case FB_BLANK_UNBLANK:
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pr_debug("fb%d: unblank\n", info->node);
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svga_wcrt_mask(0x36, 0x00, 0x30);
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svga_wseq_mask(0x01, 0x00, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x00, 0x20);
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break;
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case FB_BLANK_NORMAL:
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pr_debug("fb%d: blank\n", info->node);
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svga_wcrt_mask(0x36, 0x00, 0x30);
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svga_wseq_mask(0x01, 0x20, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
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break;
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case FB_BLANK_HSYNC_SUSPEND:
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pr_debug("fb%d: DPMS standby (hsync off)\n", info->node);
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svga_wcrt_mask(0x36, 0x10, 0x30);
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svga_wseq_mask(0x01, 0x20, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
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break;
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case FB_BLANK_VSYNC_SUSPEND:
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pr_debug("fb%d: DPMS suspend (vsync off)\n", info->node);
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svga_wcrt_mask(0x36, 0x20, 0x30);
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svga_wseq_mask(0x01, 0x20, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
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break;
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case FB_BLANK_POWERDOWN:
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pr_debug("fb%d: DPMS off (no sync)\n", info->node);
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svga_wcrt_mask(0x36, 0x30, 0x30);
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svga_wseq_mask(0x01, 0x20, 0x20);
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svga_wseq_mask(par->state.vgabase, 0x01, 0x20, 0x20);
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break;
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}
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@ -76,9 +76,9 @@ static inline void svga_wattr(void __iomem *regbase, u8 index, u8 data)
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/* Write a value to a sequence register with a mask */
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static inline void svga_wseq_mask(u8 index, u8 data, u8 mask)
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static inline void svga_wseq_mask(void __iomem *regbase, u8 index, u8 data, u8 mask)
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{
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vga_wseq(NULL, index, (data & mask) | (vga_rseq(NULL, index) & ~mask));
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vga_wseq(regbase, index, (data & mask) | (vga_rseq(regbase, index) & ~mask));
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}
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/* Write a value to a CRT register with a mask */
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