Merge branches 'pci/dpc', 'pci/resource' and 'pci/thunderbolt' into next
* pci/dpc: PCI: Add Downstream Port Containment driver PCI: Add Downstream Port Containment portdrv service type PCI: Widen portdrv service type from 4 bits to 8 bits * pci/resource: alpha/PCI: Call iomem_is_exclusive() for IORESOURCE_MEM, but not IORESOURCE_IO PCI: Supply CPU physical address (not bus address) to iomem_is_exclusive() * pci/thunderbolt: thunderbolt: Fix double free of drom buffer
This commit is contained in:
Bjorn Helgaas
Коммит
d9322d226f
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@ -77,10 +77,10 @@ static int pci_mmap_resource(struct kobject *kobj,
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if (i >= PCI_ROM_RESOURCE)
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return -ENODEV;
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if (!__pci_mmap_fits(pdev, i, vma, sparse))
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if (res->flags & IORESOURCE_MEM && iomem_is_exclusive(res->start))
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return -EINVAL;
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if (iomem_is_exclusive(res->start))
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if (!__pci_mmap_fits(pdev, i, vma, sparse))
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return -EINVAL;
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pcibios_resource_to_bus(pdev->bus, &bar, res);
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@ -1008,6 +1008,9 @@ static int pci_mmap_resource(struct kobject *kobj, struct bin_attribute *attr,
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if (i >= PCI_ROM_RESOURCE)
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return -ENODEV;
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if (res->flags & IORESOURCE_MEM && iomem_is_exclusive(res->start))
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return -EINVAL;
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if (!pci_mmap_fits(pdev, i, vma, PCI_MMAP_SYSFS)) {
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WARN(1, "process \"%s\" tried to map 0x%08lx bytes at page 0x%08lx on %s BAR %d (start 0x%16Lx, size 0x%16Lx)\n",
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current->comm, vma->vm_end-vma->vm_start, vma->vm_pgoff,
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@ -1024,10 +1027,6 @@ static int pci_mmap_resource(struct kobject *kobj, struct bin_attribute *attr,
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pci_resource_to_user(pdev, i, res, &start, &end);
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vma->vm_pgoff += start >> PAGE_SHIFT;
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mmap_type = res->flags & IORESOURCE_MEM ? pci_mmap_mem : pci_mmap_io;
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if (res->flags & IORESOURCE_MEM && iomem_is_exclusive(start))
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return -EINVAL;
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return pci_mmap_page_range(pdev, vma, mmap_type, write_combine);
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}
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@ -81,3 +81,17 @@ endchoice
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config PCIE_PME
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def_bool y
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depends on PCIEPORTBUS && PM
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config PCIE_DPC
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tristate "PCIe Downstream Port Containment support"
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depends on PCIEPORTBUS
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default n
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help
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This enables PCI Express Downstream Port Containment (DPC)
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driver support. DPC events from Root and Downstream ports
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will be handled by the DPC driver. If your system doesn't
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have this capability or you do not want to use this feature,
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it is safe to answer N.
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To compile this driver as a module, choose M here: the module
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will be called pcie-dpc.
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@ -14,3 +14,5 @@ obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o
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obj-$(CONFIG_PCIEAER) += aer/
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obj-$(CONFIG_PCIE_PME) += pme.o
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obj-$(CONFIG_PCIE_DPC) += pcie-dpc.o
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@ -0,0 +1,163 @@
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/*
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* PCI Express Downstream Port Containment services driver
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* Copyright (C) 2016 Intel Corp.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/pcieport_if.h>
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struct dpc_dev {
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struct pcie_device *dev;
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struct work_struct work;
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int cap_pos;
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};
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static void dpc_wait_link_inactive(struct pci_dev *pdev)
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{
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unsigned long timeout = jiffies + HZ;
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u16 lnk_status;
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pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
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while (lnk_status & PCI_EXP_LNKSTA_DLLLA &&
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!time_after(jiffies, timeout)) {
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msleep(10);
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pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
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}
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if (lnk_status & PCI_EXP_LNKSTA_DLLLA)
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dev_warn(&pdev->dev, "Link state not disabled for DPC event");
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}
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static void interrupt_event_handler(struct work_struct *work)
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{
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struct dpc_dev *dpc = container_of(work, struct dpc_dev, work);
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struct pci_dev *dev, *temp, *pdev = dpc->dev->port;
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struct pci_bus *parent = pdev->subordinate;
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pci_lock_rescan_remove();
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list_for_each_entry_safe_reverse(dev, temp, &parent->devices,
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bus_list) {
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pci_dev_get(dev);
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pci_stop_and_remove_bus_device(dev);
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pci_dev_put(dev);
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}
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pci_unlock_rescan_remove();
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dpc_wait_link_inactive(pdev);
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pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS,
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PCI_EXP_DPC_STATUS_TRIGGER | PCI_EXP_DPC_STATUS_INTERRUPT);
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}
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static irqreturn_t dpc_irq(int irq, void *context)
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{
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struct dpc_dev *dpc = (struct dpc_dev *)context;
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struct pci_dev *pdev = dpc->dev->port;
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u16 status, source;
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_STATUS, &status);
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_SOURCE_ID,
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&source);
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if (!status)
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return IRQ_NONE;
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dev_info(&dpc->dev->device, "DPC containment event, status:%#06x source:%#06x\n",
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status, source);
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if (status & PCI_EXP_DPC_STATUS_TRIGGER) {
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u16 reason = (status >> 1) & 0x3;
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dev_warn(&dpc->dev->device, "DPC %s triggered, remove downstream devices\n",
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(reason == 0) ? "unmasked uncorrectable error" :
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(reason == 1) ? "ERR_NONFATAL" :
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(reason == 2) ? "ERR_FATAL" : "extended error");
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schedule_work(&dpc->work);
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}
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return IRQ_HANDLED;
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}
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#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
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static int dpc_probe(struct pcie_device *dev)
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{
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struct dpc_dev *dpc;
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struct pci_dev *pdev = dev->port;
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int status;
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u16 ctl, cap;
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dpc = kzalloc(sizeof(*dpc), GFP_KERNEL);
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if (!dpc)
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return -ENOMEM;
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dpc->cap_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
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dpc->dev = dev;
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INIT_WORK(&dpc->work, interrupt_event_handler);
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set_service_data(dev, dpc);
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status = request_irq(dev->irq, dpc_irq, IRQF_SHARED, "pcie-dpc", dpc);
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if (status) {
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dev_warn(&dev->device, "request IRQ%d failed: %d\n", dev->irq,
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status);
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goto out;
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}
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CAP, &cap);
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
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ctl |= PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN;
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pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
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dev_info(&dev->device, "DPC error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
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cap & 0xf, FLAG(cap, PCI_EXP_DPC_CAP_RP_EXT),
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FLAG(cap, PCI_EXP_DPC_CAP_POISONED_TLP),
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FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), (cap >> 8) & 0xf,
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FLAG(cap, PCI_EXP_DPC_CAP_DL_ACTIVE));
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return status;
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out:
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kfree(dpc);
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return status;
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}
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static void dpc_remove(struct pcie_device *dev)
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{
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struct dpc_dev *dpc = get_service_data(dev);
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struct pci_dev *pdev = dev->port;
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u16 ctl;
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pci_read_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, &ctl);
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ctl &= ~(PCI_EXP_DPC_CTL_EN_NONFATAL | PCI_EXP_DPC_CTL_INT_EN);
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pci_write_config_word(pdev, dpc->cap_pos + PCI_EXP_DPC_CTL, ctl);
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free_irq(dev->irq, dpc);
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kfree(dpc);
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}
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static struct pcie_port_service_driver dpcdriver = {
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.name = "dpc",
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.port_type = PCI_EXP_TYPE_ROOT_PORT | PCI_EXP_TYPE_DOWNSTREAM,
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.service = PCIE_PORT_SERVICE_DPC,
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.probe = dpc_probe,
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.remove = dpc_remove,
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};
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static int __init dpc_service_init(void)
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{
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return pcie_port_service_register(&dpcdriver);
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}
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static void __exit dpc_service_exit(void)
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{
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pcie_port_service_unregister(&dpcdriver);
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}
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MODULE_DESCRIPTION("PCI Express Downstream Port Containment driver");
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MODULE_AUTHOR("Keith Busch <keith.busch@intel.com>");
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MODULE_LICENSE("GPL");
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MODULE_VERSION("0.1");
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module_init(dpc_service_init);
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module_exit(dpc_service_exit);
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@ -11,14 +11,14 @@
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#include <linux/compiler.h>
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#define PCIE_PORT_DEVICE_MAXSERVICES 4
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#define PCIE_PORT_DEVICE_MAXSERVICES 5
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/*
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* According to the PCI Express Base Specification 2.0, the indices of
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* the MSI-X table entries used by port services must not exceed 31
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*/
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#define PCIE_PORT_MAX_MSIX_ENTRIES 32
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#define get_descriptor_id(type, service) (((type - 4) << 4) | service)
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#define get_descriptor_id(type, service) (((type - 4) << 8) | service)
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extern struct bus_type pcie_port_bus_type;
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int pcie_port_device_register(struct pci_dev *dev);
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@ -51,7 +51,7 @@ void pcie_port_acpi_setup(struct pci_dev *port, int *srv_mask)
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flags = root->osc_control_set;
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*srv_mask = PCIE_PORT_SERVICE_VC;
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*srv_mask = PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_DPC;
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if (flags & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)
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*srv_mask |= PCIE_PORT_SERVICE_HP;
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if (flags & OSC_PCI_EXPRESS_PME_CONTROL)
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@ -261,7 +261,7 @@ static int get_port_device_capability(struct pci_dev *dev)
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return 0;
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cap_mask = PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP
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| PCIE_PORT_SERVICE_VC;
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| PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_DPC;
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if (pci_aer_available())
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cap_mask |= PCIE_PORT_SERVICE_AER;
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@ -307,6 +307,8 @@ static int get_port_device_capability(struct pci_dev *dev)
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*/
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pcie_pme_interrupt_enable(dev, false);
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}
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if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC))
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services |= PCIE_PORT_SERVICE_DPC;
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return services;
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}
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@ -334,7 +336,7 @@ static int pcie_device_init(struct pci_dev *pdev, int service, int irq)
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device = &pcie->device;
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device->bus = &pcie_port_bus_type;
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device->release = release_pcie_device; /* callback to free pcie dev */
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dev_set_name(device, "%s:pcie%02x",
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dev_set_name(device, "%s:pcie%03x",
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pci_name(pdev),
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get_descriptor_id(pci_pcie_type(pdev), service));
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device->parent = &pdev->dev;
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@ -449,6 +449,7 @@ int tb_drom_read(struct tb_switch *sw)
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return tb_drom_parse_entries(sw);
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err:
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kfree(sw->drom);
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sw->drom = NULL;
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return -EIO;
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}
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@ -21,6 +21,8 @@
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#define PCIE_PORT_SERVICE_HP (1 << PCIE_PORT_SERVICE_HP_SHIFT)
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#define PCIE_PORT_SERVICE_VC_SHIFT 3 /* Virtual Channel */
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#define PCIE_PORT_SERVICE_VC (1 << PCIE_PORT_SERVICE_VC_SHIFT)
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#define PCIE_PORT_SERVICE_DPC_SHIFT 4 /* Downstream Port Containment */
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#define PCIE_PORT_SERVICE_DPC (1 << PCIE_PORT_SERVICE_DPC_SHIFT)
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struct pcie_device {
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int irq; /* Service IRQ/MSI/MSI-X Vector */
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@ -670,7 +670,8 @@
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#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
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#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
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#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
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#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PASID
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#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
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#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DPC
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#define PCI_EXT_CAP_DSN_SIZEOF 12
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#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
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@ -946,4 +947,21 @@
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#define PCI_TPH_CAP_ST_SHIFT 16 /* st table shift */
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#define PCI_TPH_BASE_SIZEOF 12 /* size with no st table */
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/* Downstream Port Containment */
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#define PCI_EXP_DPC_CAP 4 /* DPC Capability */
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#define PCI_EXP_DPC_CAP_RP_EXT 0x20 /* Root Port Extensions for DPC */
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#define PCI_EXP_DPC_CAP_POISONED_TLP 0x40 /* Poisoned TLP Egress Blocking Supported */
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#define PCI_EXP_DPC_CAP_SW_TRIGGER 0x80 /* Software Triggering Supported */
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#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
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#define PCI_EXP_DPC_CTL 6 /* DPC control */
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#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x02 /* Enable trigger on ERR_NONFATAL message */
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#define PCI_EXP_DPC_CTL_INT_EN 0x08 /* DPC Interrupt Enable */
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#define PCI_EXP_DPC_STATUS 8 /* DPC Status */
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#define PCI_EXP_DPC_STATUS_TRIGGER 0x01 /* Trigger Status */
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#define PCI_EXP_DPC_STATUS_INTERRUPT 0x08 /* Interrupt Status */
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#define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */
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#endif /* LINUX_PCI_REGS_H */
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