drm/radeon: initial VCE support v4
Only VCE 2.0 support so far.
v2: squashing multiple patches into this one
v3: add IRQ support for CIK, major cleanups,
basic code documentation
v4: remove HAINAN from chipset list
Signed-off-by: Christian König <christian.koenig@amd.com>
This commit is contained in:
Christian König
Родитель
1c61eae469
Коммит
d93f79376f
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@ -99,6 +99,12 @@ radeon-y += \
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uvd_v3_1.o \
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uvd_v4_2.o
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# add VCE block
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radeon-y += \
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radeon_vce.o \
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vce_v1_0.o \
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vce_v2_0.o \
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radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
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radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o
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radeon-$(CONFIG_ACPI) += radeon_acpi.o
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@ -7490,6 +7490,20 @@ restart_ih:
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/* reset addr and status */
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WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
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break;
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case 167: /* VCE */
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DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data);
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switch (src_data) {
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case 0:
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radeon_fence_process(rdev, TN_RING_TYPE_VCE1_INDEX);
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break;
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case 1:
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radeon_fence_process(rdev, TN_RING_TYPE_VCE2_INDEX);
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break;
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default:
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DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
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break;
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}
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break;
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case 176: /* GFX RB CP_INT */
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case 177: /* GFX IB CP_INT */
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radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
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@ -7789,6 +7803,22 @@ static int cik_startup(struct radeon_device *rdev)
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if (r)
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rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
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r = radeon_vce_resume(rdev);
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if (!r) {
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r = vce_v2_0_resume(rdev);
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if (!r)
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r = radeon_fence_driver_start_ring(rdev,
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TN_RING_TYPE_VCE1_INDEX);
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if (!r)
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r = radeon_fence_driver_start_ring(rdev,
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TN_RING_TYPE_VCE2_INDEX);
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}
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if (r) {
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dev_err(rdev->dev, "VCE init error (%d).\n", r);
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rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
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rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
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}
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/* Enable IRQ */
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if (!rdev->irq.installed) {
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r = radeon_irq_kms_init(rdev);
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@ -7864,6 +7894,23 @@ static int cik_startup(struct radeon_device *rdev)
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DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
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}
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r = -ENOENT;
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ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
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if (ring->ring_size)
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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VCE_CMD_NO_OP);
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ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
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if (ring->ring_size)
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r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
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VCE_CMD_NO_OP);
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if (!r)
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r = vce_v1_0_init(rdev);
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else if (r != -ENOENT)
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DRM_ERROR("radeon: failed initializing VCE (%d).\n", r);
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r = radeon_ib_pool_init(rdev);
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if (r) {
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dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
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@ -7934,6 +7981,7 @@ int cik_suspend(struct radeon_device *rdev)
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cik_sdma_enable(rdev, false);
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uvd_v1_0_fini(rdev);
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radeon_uvd_suspend(rdev);
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radeon_vce_suspend(rdev);
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cik_fini_pg(rdev);
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cik_fini_cg(rdev);
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cik_irq_suspend(rdev);
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@ -8066,6 +8114,17 @@ int cik_init(struct radeon_device *rdev)
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r600_ring_init(rdev, ring, 4096);
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}
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r = radeon_vce_init(rdev);
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if (!r) {
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ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 4096);
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ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
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ring->ring_obj = NULL;
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r600_ring_init(rdev, ring, 4096);
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}
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rdev->ih.ring_obj = NULL;
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r600_ih_ring_init(rdev, 64 * 1024);
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@ -8127,6 +8186,7 @@ void cik_fini(struct radeon_device *rdev)
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radeon_irq_kms_fini(rdev);
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uvd_v1_0_fini(rdev);
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radeon_uvd_fini(rdev);
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radeon_vce_fini(rdev);
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cik_pcie_gart_fini(rdev);
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r600_vram_scratch_fini(rdev);
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radeon_gem_fini(rdev);
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@ -2010,4 +2010,37 @@
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/* UVD CTX indirect */
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#define UVD_CGC_MEM_CTRL 0xC0
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/* VCE */
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#define VCE_VCPU_CACHE_OFFSET0 0x20024
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#define VCE_VCPU_CACHE_SIZE0 0x20028
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#define VCE_VCPU_CACHE_OFFSET1 0x2002c
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#define VCE_VCPU_CACHE_SIZE1 0x20030
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#define VCE_VCPU_CACHE_OFFSET2 0x20034
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#define VCE_VCPU_CACHE_SIZE2 0x20038
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#define VCE_RB_RPTR2 0x20178
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#define VCE_RB_WPTR2 0x2017c
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#define VCE_RB_RPTR 0x2018c
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#define VCE_RB_WPTR 0x20190
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#define VCE_CLOCK_GATING_A 0x202f8
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#define VCE_CLOCK_GATING_B 0x202fc
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#define VCE_UENC_CLOCK_GATING 0x207bc
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#define VCE_UENC_REG_CLOCK_GATING 0x207c0
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#define VCE_SYS_INT_EN 0x21300
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# define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3)
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#define VCE_LMI_CTRL2 0x21474
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#define VCE_LMI_CTRL 0x21498
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#define VCE_LMI_VM_CTRL 0x214a0
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#define VCE_LMI_SWAP_CNTL 0x214b4
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#define VCE_LMI_SWAP_CNTL1 0x214b8
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#define VCE_LMI_CACHE_CTRL 0x214f4
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#define VCE_CMD_NO_OP 0x00000000
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#define VCE_CMD_END 0x00000001
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#define VCE_CMD_IB 0x00000002
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#define VCE_CMD_FENCE 0x00000003
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#define VCE_CMD_TRAP 0x00000004
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#define VCE_CMD_IB_AUTO 0x00000005
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#define VCE_CMD_SEMAPHORE 0x00000006
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#endif
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@ -113,19 +113,16 @@ extern int radeon_hard_reset;
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#define RADEONFB_CONN_LIMIT 4
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#define RADEON_BIOS_NUM_SCRATCH 8
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/* max number of rings */
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#define RADEON_NUM_RINGS 6
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/* fence seq are set to this number when signaled */
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#define RADEON_FENCE_SIGNALED_SEQ 0LL
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/* internal ring indices */
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/* r1xx+ has gfx CP ring */
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#define RADEON_RING_TYPE_GFX_INDEX 0
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#define RADEON_RING_TYPE_GFX_INDEX 0
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/* cayman has 2 compute CP rings */
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#define CAYMAN_RING_TYPE_CP1_INDEX 1
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#define CAYMAN_RING_TYPE_CP2_INDEX 2
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#define CAYMAN_RING_TYPE_CP1_INDEX 1
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#define CAYMAN_RING_TYPE_CP2_INDEX 2
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/* R600+ has an async dma ring */
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#define R600_RING_TYPE_DMA_INDEX 3
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@ -133,7 +130,14 @@ extern int radeon_hard_reset;
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#define CAYMAN_RING_TYPE_DMA1_INDEX 4
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/* R600+ */
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#define R600_RING_TYPE_UVD_INDEX 5
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#define R600_RING_TYPE_UVD_INDEX 5
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/* TN+ */
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#define TN_RING_TYPE_VCE1_INDEX 6
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#define TN_RING_TYPE_VCE2_INDEX 7
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/* max number of rings */
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#define RADEON_NUM_RINGS 8
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/* number of hw syncs before falling back on blocking */
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#define RADEON_NUM_SYNCS 4
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@ -1591,6 +1595,42 @@ int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev,
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int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev,
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unsigned cg_upll_func_cntl);
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/*
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* VCE
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*/
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#define RADEON_MAX_VCE_HANDLES 16
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#define RADEON_VCE_STACK_SIZE (1024*1024)
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#define RADEON_VCE_HEAP_SIZE (4*1024*1024)
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struct radeon_vce {
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struct radeon_bo *vcpu_bo;
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void *cpu_addr;
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uint64_t gpu_addr;
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atomic_t handles[RADEON_MAX_VCE_HANDLES];
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struct drm_file *filp[RADEON_MAX_VCE_HANDLES];
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};
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int radeon_vce_init(struct radeon_device *rdev);
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void radeon_vce_fini(struct radeon_device *rdev);
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int radeon_vce_suspend(struct radeon_device *rdev);
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int radeon_vce_resume(struct radeon_device *rdev);
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int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
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uint32_t handle, struct radeon_fence **fence);
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int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
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uint32_t handle, struct radeon_fence **fence);
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void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp);
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int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi);
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int radeon_vce_cs_parse(struct radeon_cs_parser *p);
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bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
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struct radeon_ring *ring,
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struct radeon_semaphore *semaphore,
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bool emit_wait);
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void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
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void radeon_vce_fence_emit(struct radeon_device *rdev,
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struct radeon_fence *fence);
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int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
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int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
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struct r600_audio_pin {
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int channels;
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int rate;
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@ -2186,6 +2226,7 @@ struct radeon_device {
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struct radeon_gem gem;
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struct radeon_pm pm;
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struct radeon_uvd uvd;
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struct radeon_vce vce;
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uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
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struct radeon_wb wb;
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struct radeon_dummy_page dummy_page;
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@ -2205,6 +2246,7 @@ struct radeon_device {
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const struct firmware *sdma_fw; /* CIK SDMA firmware */
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const struct firmware *smc_fw; /* SMC firmware */
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const struct firmware *uvd_fw; /* UVD firmware */
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const struct firmware *vce_fw; /* VCE firmware */
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struct r600_vram_scratch vram_scratch;
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int msi_enabled; /* msi enabled */
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struct r600_ih ih; /* r6/700 interrupt ring */
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@ -1987,6 +1987,19 @@ static struct radeon_asic_ring ci_dma_ring = {
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.set_wptr = &cik_sdma_set_wptr,
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};
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static struct radeon_asic_ring ci_vce_ring = {
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.ib_execute = &radeon_vce_ib_execute,
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.emit_fence = &radeon_vce_fence_emit,
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.emit_semaphore = &radeon_vce_semaphore_emit,
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.cs_parse = &radeon_vce_cs_parse,
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.ring_test = &radeon_vce_ring_test,
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.ib_test = &radeon_vce_ib_test,
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.is_lockup = &radeon_ring_test_lockup,
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.get_rptr = &vce_v1_0_get_rptr,
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.get_wptr = &vce_v1_0_get_wptr,
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.set_wptr = &vce_v1_0_set_wptr,
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};
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static struct radeon_asic ci_asic = {
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.init = &cik_init,
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.fini = &cik_fini,
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@ -2015,6 +2028,8 @@ static struct radeon_asic ci_asic = {
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[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
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[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
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[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
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[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
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[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
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},
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.irq = {
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.set = &cik_irq_set,
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@ -2117,6 +2132,8 @@ static struct radeon_asic kv_asic = {
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[R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
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[CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
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[R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
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[TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
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[TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
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},
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.irq = {
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.set = &cik_irq_set,
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@ -863,4 +863,17 @@ bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
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/* uvd v4.2 */
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int uvd_v4_2_resume(struct radeon_device *rdev);
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/* vce v1.0 */
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uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
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struct radeon_ring *ring);
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uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring);
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void vce_v1_0_set_wptr(struct radeon_device *rdev,
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struct radeon_ring *ring);
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int vce_v1_0_init(struct radeon_device *rdev);
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int vce_v1_0_start(struct radeon_device *rdev);
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/* vce v2.0 */
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int vce_v2_0_resume(struct radeon_device *rdev);
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#endif
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@ -147,6 +147,10 @@ static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority
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case RADEON_CS_RING_UVD:
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p->ring = R600_RING_TYPE_UVD_INDEX;
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break;
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case RADEON_CS_RING_VCE:
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/* TODO: only use the low priority ring for now */
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p->ring = TN_RING_TYPE_VCE1_INDEX;
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break;
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}
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return 0;
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}
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@ -610,6 +610,7 @@ void radeon_driver_preclose_kms(struct drm_device *dev,
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if (rdev->cmask_filp == file_priv)
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rdev->cmask_filp = NULL;
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radeon_uvd_free_handles(rdev, file_priv);
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radeon_vce_free_handles(rdev, file_priv);
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}
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/*
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@ -814,6 +814,8 @@ static int cayman_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
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static int radeon_dma1_index = R600_RING_TYPE_DMA_INDEX;
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static int radeon_dma2_index = CAYMAN_RING_TYPE_DMA1_INDEX;
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static int r600_uvd_index = R600_RING_TYPE_UVD_INDEX;
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static int si_vce1_index = TN_RING_TYPE_VCE1_INDEX;
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static int si_vce2_index = TN_RING_TYPE_VCE2_INDEX;
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static struct drm_info_list radeon_debugfs_ring_info_list[] = {
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{"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_gfx_index},
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@ -822,6 +824,8 @@ static struct drm_info_list radeon_debugfs_ring_info_list[] = {
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{"radeon_ring_dma1", radeon_debugfs_ring_info, 0, &radeon_dma1_index},
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{"radeon_ring_dma2", radeon_debugfs_ring_info, 0, &radeon_dma2_index},
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{"radeon_ring_uvd", radeon_debugfs_ring_info, 0, &r600_uvd_index},
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{"radeon_ring_vce1", radeon_debugfs_ring_info, 0, &si_vce1_index},
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{"radeon_ring_vce2", radeon_debugfs_ring_info, 0, &si_vce2_index},
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};
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static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
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@ -257,20 +257,36 @@ static int radeon_test_create_and_emit_fence(struct radeon_device *rdev,
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struct radeon_ring *ring,
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struct radeon_fence **fence)
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{
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uint32_t handle = ring->idx ^ 0xdeafbeef;
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int r;
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if (ring->idx == R600_RING_TYPE_UVD_INDEX) {
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r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);
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r = radeon_uvd_get_create_msg(rdev, ring->idx, handle, NULL);
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if (r) {
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DRM_ERROR("Failed to get dummy create msg\n");
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return r;
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}
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||||
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r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, fence);
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r = radeon_uvd_get_destroy_msg(rdev, ring->idx, handle, fence);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed to get dummy destroy msg\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
} else if (ring->idx == TN_RING_TYPE_VCE1_INDEX ||
|
||||
ring->idx == TN_RING_TYPE_VCE2_INDEX) {
|
||||
r = radeon_vce_get_create_msg(rdev, ring->idx, handle, NULL);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed to get dummy create msg\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
r = radeon_vce_get_destroy_msg(rdev, ring->idx, handle, fence);
|
||||
if (r) {
|
||||
DRM_ERROR("Failed to get dummy destroy msg\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
} else {
|
||||
r = radeon_ring_lock(rdev, ring, 64);
|
||||
if (r) {
|
||||
|
|
@ -486,6 +502,16 @@ out_cleanup:
|
|||
printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
|
||||
}
|
||||
|
||||
static bool radeon_test_sync_possible(struct radeon_ring *ringA,
|
||||
struct radeon_ring *ringB)
|
||||
{
|
||||
if (ringA->idx == TN_RING_TYPE_VCE2_INDEX &&
|
||||
ringB->idx == TN_RING_TYPE_VCE1_INDEX)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void radeon_test_syncing(struct radeon_device *rdev)
|
||||
{
|
||||
int i, j, k;
|
||||
|
|
@ -500,6 +526,9 @@ void radeon_test_syncing(struct radeon_device *rdev)
|
|||
if (!ringB->ready)
|
||||
continue;
|
||||
|
||||
if (!radeon_test_sync_possible(ringA, ringB))
|
||||
continue;
|
||||
|
||||
DRM_INFO("Testing syncing between rings %d and %d...\n", i, j);
|
||||
radeon_test_ring_sync(rdev, ringA, ringB);
|
||||
|
||||
|
|
@ -511,6 +540,12 @@ void radeon_test_syncing(struct radeon_device *rdev)
|
|||
if (!ringC->ready)
|
||||
continue;
|
||||
|
||||
if (!radeon_test_sync_possible(ringA, ringC))
|
||||
continue;
|
||||
|
||||
if (!radeon_test_sync_possible(ringB, ringC))
|
||||
continue;
|
||||
|
||||
DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
|
||||
radeon_test_ring_sync2(rdev, ringA, ringB, ringC);
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,588 @@
|
|||
/*
|
||||
* Copyright 2013 Advanced Micro Devices, Inc.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sub license, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||||
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||||
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial portions
|
||||
* of the Software.
|
||||
*
|
||||
* Authors: Christian König <christian.koenig@amd.com>
|
||||
*/
|
||||
|
||||
#include <linux/firmware.h>
|
||||
#include <linux/module.h>
|
||||
#include <drm/drmP.h>
|
||||
#include <drm/drm.h>
|
||||
|
||||
#include "radeon.h"
|
||||
#include "radeon_asic.h"
|
||||
#include "sid.h"
|
||||
|
||||
/* Firmware Names */
|
||||
#define FIRMWARE_BONAIRE "radeon/BONAIRE_vce.bin"
|
||||
|
||||
MODULE_FIRMWARE(FIRMWARE_BONAIRE);
|
||||
|
||||
/**
|
||||
* radeon_vce_init - allocate memory, load vce firmware
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* First step to get VCE online, allocate memory and load the firmware
|
||||
*/
|
||||
int radeon_vce_init(struct radeon_device *rdev)
|
||||
{
|
||||
unsigned long bo_size;
|
||||
const char *fw_name;
|
||||
int i, r;
|
||||
|
||||
switch (rdev->family) {
|
||||
case CHIP_BONAIRE:
|
||||
case CHIP_KAVERI:
|
||||
case CHIP_KABINI:
|
||||
fw_name = FIRMWARE_BONAIRE;
|
||||
break;
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
r = request_firmware(&rdev->vce_fw, fw_name, rdev->dev);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "radeon_vce: Can't load firmware \"%s\"\n",
|
||||
fw_name);
|
||||
return r;
|
||||
}
|
||||
|
||||
bo_size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size) +
|
||||
RADEON_VCE_STACK_SIZE + RADEON_VCE_HEAP_SIZE;
|
||||
r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
|
||||
RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->vce.vcpu_bo);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "(%d) failed to allocate VCE bo\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
r = radeon_vce_resume(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
memset(rdev->vce.cpu_addr, 0, bo_size);
|
||||
memcpy(rdev->vce.cpu_addr, rdev->vce_fw->data, rdev->vce_fw->size);
|
||||
|
||||
r = radeon_vce_suspend(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
|
||||
atomic_set(&rdev->vce.handles[i], 0);
|
||||
rdev->vce.filp[i] = NULL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vce_fini - free memory
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* Last step on VCE teardown, free firmware memory
|
||||
*/
|
||||
void radeon_vce_fini(struct radeon_device *rdev)
|
||||
{
|
||||
radeon_vce_suspend(rdev);
|
||||
radeon_bo_unref(&rdev->vce.vcpu_bo);
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vce_suspend - unpin VCE fw memory
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* TODO: Test VCE suspend/resume
|
||||
*/
|
||||
int radeon_vce_suspend(struct radeon_device *rdev)
|
||||
{
|
||||
int r;
|
||||
|
||||
if (rdev->vce.vcpu_bo == NULL)
|
||||
return 0;
|
||||
|
||||
r = radeon_bo_reserve(rdev->vce.vcpu_bo, false);
|
||||
if (!r) {
|
||||
radeon_bo_kunmap(rdev->vce.vcpu_bo);
|
||||
radeon_bo_unpin(rdev->vce.vcpu_bo);
|
||||
radeon_bo_unreserve(rdev->vce.vcpu_bo);
|
||||
}
|
||||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vce_resume - pin VCE fw memory
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* TODO: Test VCE suspend/resume
|
||||
*/
|
||||
int radeon_vce_resume(struct radeon_device *rdev)
|
||||
{
|
||||
int r;
|
||||
|
||||
if (rdev->vce.vcpu_bo == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
r = radeon_bo_reserve(rdev->vce.vcpu_bo, false);
|
||||
if (r) {
|
||||
radeon_bo_unref(&rdev->vce.vcpu_bo);
|
||||
dev_err(rdev->dev, "(%d) failed to reserve VCE bo\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
r = radeon_bo_pin(rdev->vce.vcpu_bo, RADEON_GEM_DOMAIN_VRAM,
|
||||
&rdev->vce.gpu_addr);
|
||||
if (r) {
|
||||
radeon_bo_unreserve(rdev->vce.vcpu_bo);
|
||||
radeon_bo_unref(&rdev->vce.vcpu_bo);
|
||||
dev_err(rdev->dev, "(%d) VCE bo pin failed\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
r = radeon_bo_kmap(rdev->vce.vcpu_bo, &rdev->vce.cpu_addr);
|
||||
if (r) {
|
||||
dev_err(rdev->dev, "(%d) VCE map failed\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
radeon_bo_unreserve(rdev->vce.vcpu_bo);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vce_free_handles - free still open VCE handles
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @filp: drm file pointer
|
||||
*
|
||||
* Close all VCE handles still open by this file pointer
|
||||
*/
|
||||
void radeon_vce_free_handles(struct radeon_device *rdev, struct drm_file *filp)
|
||||
{
|
||||
int i, r;
|
||||
for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
|
||||
uint32_t handle = atomic_read(&rdev->vce.handles[i]);
|
||||
if (!handle || rdev->vce.filp[i] != filp)
|
||||
continue;
|
||||
|
||||
r = radeon_vce_get_destroy_msg(rdev, TN_RING_TYPE_VCE1_INDEX,
|
||||
handle, NULL);
|
||||
if (r)
|
||||
DRM_ERROR("Error destroying VCE handle (%d)!\n", r);
|
||||
|
||||
rdev->vce.filp[i] = NULL;
|
||||
atomic_set(&rdev->vce.handles[i], 0);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vce_get_create_msg - generate a VCE create msg
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: ring we should submit the msg to
|
||||
* @handle: VCE session handle to use
|
||||
* @fence: optional fence to return
|
||||
*
|
||||
* Open up a stream for HW test
|
||||
*/
|
||||
int radeon_vce_get_create_msg(struct radeon_device *rdev, int ring,
|
||||
uint32_t handle, struct radeon_fence **fence)
|
||||
{
|
||||
const unsigned ib_size_dw = 1024;
|
||||
struct radeon_ib ib;
|
||||
uint64_t dummy;
|
||||
int i, r;
|
||||
|
||||
r = radeon_ib_get(rdev, ring, &ib, NULL, ib_size_dw * 4);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: failed to get ib (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
dummy = ib.gpu_addr + 1024;
|
||||
|
||||
/* stitch together an VCE create msg */
|
||||
ib.length_dw = 0;
|
||||
ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
|
||||
ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
|
||||
ib.ptr[ib.length_dw++] = handle;
|
||||
|
||||
ib.ptr[ib.length_dw++] = 0x00000030; /* len */
|
||||
ib.ptr[ib.length_dw++] = 0x01000001; /* create cmd */
|
||||
ib.ptr[ib.length_dw++] = 0x00000000;
|
||||
ib.ptr[ib.length_dw++] = 0x00000042;
|
||||
ib.ptr[ib.length_dw++] = 0x0000000a;
|
||||
ib.ptr[ib.length_dw++] = 0x00000001;
|
||||
ib.ptr[ib.length_dw++] = 0x00000080;
|
||||
ib.ptr[ib.length_dw++] = 0x00000060;
|
||||
ib.ptr[ib.length_dw++] = 0x00000100;
|
||||
ib.ptr[ib.length_dw++] = 0x00000100;
|
||||
ib.ptr[ib.length_dw++] = 0x0000000c;
|
||||
ib.ptr[ib.length_dw++] = 0x00000000;
|
||||
|
||||
ib.ptr[ib.length_dw++] = 0x00000014; /* len */
|
||||
ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
|
||||
ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
|
||||
ib.ptr[ib.length_dw++] = dummy;
|
||||
ib.ptr[ib.length_dw++] = 0x00000001;
|
||||
|
||||
for (i = ib.length_dw; i < ib_size_dw; ++i)
|
||||
ib.ptr[i] = 0x0;
|
||||
|
||||
r = radeon_ib_schedule(rdev, &ib, NULL);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
|
||||
}
|
||||
|
||||
if (fence)
|
||||
*fence = radeon_fence_ref(ib.fence);
|
||||
|
||||
radeon_ib_free(rdev, &ib);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vce_get_destroy_msg - generate a VCE destroy msg
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: ring we should submit the msg to
|
||||
* @handle: VCE session handle to use
|
||||
* @fence: optional fence to return
|
||||
*
|
||||
* Close up a stream for HW test or if userspace failed to do so
|
||||
*/
|
||||
int radeon_vce_get_destroy_msg(struct radeon_device *rdev, int ring,
|
||||
uint32_t handle, struct radeon_fence **fence)
|
||||
{
|
||||
const unsigned ib_size_dw = 1024;
|
||||
struct radeon_ib ib;
|
||||
uint64_t dummy;
|
||||
int i, r;
|
||||
|
||||
r = radeon_ib_get(rdev, ring, &ib, NULL, ib_size_dw * 4);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: failed to get ib (%d).\n", r);
|
||||
return r;
|
||||
}
|
||||
|
||||
dummy = ib.gpu_addr + 1024;
|
||||
|
||||
/* stitch together an VCE destroy msg */
|
||||
ib.length_dw = 0;
|
||||
ib.ptr[ib.length_dw++] = 0x0000000c; /* len */
|
||||
ib.ptr[ib.length_dw++] = 0x00000001; /* session cmd */
|
||||
ib.ptr[ib.length_dw++] = handle;
|
||||
|
||||
ib.ptr[ib.length_dw++] = 0x00000014; /* len */
|
||||
ib.ptr[ib.length_dw++] = 0x05000005; /* feedback buffer */
|
||||
ib.ptr[ib.length_dw++] = upper_32_bits(dummy);
|
||||
ib.ptr[ib.length_dw++] = dummy;
|
||||
ib.ptr[ib.length_dw++] = 0x00000001;
|
||||
|
||||
ib.ptr[ib.length_dw++] = 0x00000008; /* len */
|
||||
ib.ptr[ib.length_dw++] = 0x02000001; /* destroy cmd */
|
||||
|
||||
for (i = ib.length_dw; i < ib_size_dw; ++i)
|
||||
ib.ptr[i] = 0x0;
|
||||
|
||||
r = radeon_ib_schedule(rdev, &ib, NULL);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
|
||||
}
|
||||
|
||||
if (fence)
|
||||
*fence = radeon_fence_ref(ib.fence);
|
||||
|
||||
radeon_ib_free(rdev, &ib);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vce_cs_reloc - command submission relocation
|
||||
*
|
||||
* @p: parser context
|
||||
* @lo: address of lower dword
|
||||
* @hi: address of higher dword
|
||||
*
|
||||
* Patch relocation inside command stream with real buffer address
|
||||
*/
|
||||
int radeon_vce_cs_reloc(struct radeon_cs_parser *p, int lo, int hi)
|
||||
{
|
||||
struct radeon_cs_chunk *relocs_chunk;
|
||||
uint64_t offset;
|
||||
unsigned idx;
|
||||
|
||||
relocs_chunk = &p->chunks[p->chunk_relocs_idx];
|
||||
offset = radeon_get_ib_value(p, lo);
|
||||
idx = radeon_get_ib_value(p, hi);
|
||||
|
||||
if (idx >= relocs_chunk->length_dw) {
|
||||
DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
|
||||
idx, relocs_chunk->length_dw);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
offset += p->relocs_ptr[(idx / 4)]->lobj.gpu_offset;
|
||||
|
||||
p->ib.ptr[lo] = offset & 0xFFFFFFFF;
|
||||
p->ib.ptr[hi] = offset >> 32;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vce_cs_parse - parse and validate the command stream
|
||||
*
|
||||
* @p: parser context
|
||||
*
|
||||
*/
|
||||
int radeon_vce_cs_parse(struct radeon_cs_parser *p)
|
||||
{
|
||||
uint32_t handle = 0;
|
||||
bool destroy = false;
|
||||
int i, r;
|
||||
|
||||
while (p->idx < p->chunks[p->chunk_ib_idx].length_dw) {
|
||||
uint32_t len = radeon_get_ib_value(p, p->idx);
|
||||
uint32_t cmd = radeon_get_ib_value(p, p->idx + 1);
|
||||
|
||||
if ((len < 8) || (len & 3)) {
|
||||
DRM_ERROR("invalid VCE command length (%d)!\n", len);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
switch (cmd) {
|
||||
case 0x00000001: // session
|
||||
handle = radeon_get_ib_value(p, p->idx + 2);
|
||||
break;
|
||||
|
||||
case 0x00000002: // task info
|
||||
case 0x01000001: // create
|
||||
case 0x04000001: // config extension
|
||||
case 0x04000002: // pic control
|
||||
case 0x04000005: // rate control
|
||||
case 0x04000007: // motion estimation
|
||||
case 0x04000008: // rdo
|
||||
break;
|
||||
|
||||
case 0x03000001: // encode
|
||||
r = radeon_vce_cs_reloc(p, p->idx + 10, p->idx + 9);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
r = radeon_vce_cs_reloc(p, p->idx + 12, p->idx + 11);
|
||||
if (r)
|
||||
return r;
|
||||
break;
|
||||
|
||||
case 0x02000001: // destroy
|
||||
destroy = true;
|
||||
break;
|
||||
|
||||
case 0x05000001: // context buffer
|
||||
case 0x05000004: // video bitstream buffer
|
||||
case 0x05000005: // feedback buffer
|
||||
r = radeon_vce_cs_reloc(p, p->idx + 3, p->idx + 2);
|
||||
if (r)
|
||||
return r;
|
||||
break;
|
||||
|
||||
default:
|
||||
DRM_ERROR("invalid VCE command (0x%x)!\n", cmd);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
p->idx += len / 4;
|
||||
}
|
||||
|
||||
if (destroy) {
|
||||
/* IB contains a destroy msg, free the handle */
|
||||
for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i)
|
||||
atomic_cmpxchg(&p->rdev->vce.handles[i], handle, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* create or encode, validate the handle */
|
||||
for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
|
||||
if (atomic_read(&p->rdev->vce.handles[i]) == handle)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* handle not found try to alloc a new one */
|
||||
for (i = 0; i < RADEON_MAX_VCE_HANDLES; ++i) {
|
||||
if (!atomic_cmpxchg(&p->rdev->vce.handles[i], 0, handle)) {
|
||||
p->rdev->vce.filp[i] = p->filp;
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
DRM_ERROR("No more free VCE handles!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vce_semaphore_emit - emit a semaphore command
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: engine to use
|
||||
* @semaphore: address of semaphore
|
||||
* @emit_wait: true=emit wait, false=emit signal
|
||||
*
|
||||
*/
|
||||
bool radeon_vce_semaphore_emit(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring,
|
||||
struct radeon_semaphore *semaphore,
|
||||
bool emit_wait)
|
||||
{
|
||||
uint64_t addr = semaphore->gpu_addr;
|
||||
|
||||
radeon_ring_write(ring, VCE_CMD_SEMAPHORE);
|
||||
radeon_ring_write(ring, (addr >> 3) & 0x000FFFFF);
|
||||
radeon_ring_write(ring, (addr >> 23) & 0x000FFFFF);
|
||||
radeon_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0));
|
||||
if (!emit_wait)
|
||||
radeon_ring_write(ring, VCE_CMD_END);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vce_ib_execute - execute indirect buffer
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ib: the IB to execute
|
||||
*
|
||||
*/
|
||||
void radeon_vce_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[ib->ring];
|
||||
radeon_ring_write(ring, VCE_CMD_IB);
|
||||
radeon_ring_write(ring, ib->gpu_addr);
|
||||
radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
|
||||
radeon_ring_write(ring, ib->length_dw);
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vce_fence_emit - add a fence command to the ring
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @fence: the fence
|
||||
*
|
||||
*/
|
||||
void radeon_vce_fence_emit(struct radeon_device *rdev,
|
||||
struct radeon_fence *fence)
|
||||
{
|
||||
struct radeon_ring *ring = &rdev->ring[fence->ring];
|
||||
uint32_t addr = rdev->fence_drv[fence->ring].gpu_addr;
|
||||
|
||||
radeon_ring_write(ring, VCE_CMD_FENCE);
|
||||
radeon_ring_write(ring, addr);
|
||||
radeon_ring_write(ring, upper_32_bits(addr));
|
||||
radeon_ring_write(ring, fence->seq);
|
||||
radeon_ring_write(ring, VCE_CMD_TRAP);
|
||||
radeon_ring_write(ring, VCE_CMD_END);
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vce_ring_test - test if VCE ring is working
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: the engine to test on
|
||||
*
|
||||
*/
|
||||
int radeon_vce_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
||||
{
|
||||
uint32_t rptr = vce_v1_0_get_rptr(rdev, ring);
|
||||
unsigned i;
|
||||
int r;
|
||||
|
||||
r = radeon_ring_lock(rdev, ring, 16);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: vce failed to lock ring %d (%d).\n",
|
||||
ring->idx, r);
|
||||
return r;
|
||||
}
|
||||
radeon_ring_write(ring, VCE_CMD_END);
|
||||
radeon_ring_unlock_commit(rdev, ring);
|
||||
|
||||
for (i = 0; i < rdev->usec_timeout; i++) {
|
||||
if (vce_v1_0_get_rptr(rdev, ring) != rptr)
|
||||
break;
|
||||
DRM_UDELAY(1);
|
||||
}
|
||||
|
||||
if (i < rdev->usec_timeout) {
|
||||
DRM_INFO("ring test on %d succeeded in %d usecs\n",
|
||||
ring->idx, i);
|
||||
} else {
|
||||
DRM_ERROR("radeon: ring %d test failed\n",
|
||||
ring->idx);
|
||||
r = -ETIMEDOUT;
|
||||
}
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
/**
|
||||
* radeon_vce_ib_test - test if VCE IBs are working
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: the engine to test on
|
||||
*
|
||||
*/
|
||||
int radeon_vce_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
||||
{
|
||||
struct radeon_fence *fence = NULL;
|
||||
int r;
|
||||
|
||||
r = radeon_vce_get_create_msg(rdev, ring->idx, 1, NULL);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: failed to get create msg (%d).\n", r);
|
||||
goto error;
|
||||
}
|
||||
|
||||
r = radeon_vce_get_destroy_msg(rdev, ring->idx, 1, &fence);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r);
|
||||
goto error;
|
||||
}
|
||||
|
||||
r = radeon_fence_wait(fence, false);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: fence wait failed (%d).\n", r);
|
||||
} else {
|
||||
DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
|
||||
}
|
||||
error:
|
||||
radeon_fence_unref(&fence);
|
||||
return r;
|
||||
}
|
||||
|
|
@ -1798,4 +1798,51 @@
|
|||
#define DMA_PACKET_CONSTANT_FILL 0xd
|
||||
#define DMA_PACKET_NOP 0xf
|
||||
|
||||
#define VCE_STATUS 0x20004
|
||||
#define VCE_VCPU_CNTL 0x20014
|
||||
#define VCE_CLK_EN (1 << 0)
|
||||
#define VCE_VCPU_CACHE_OFFSET0 0x20024
|
||||
#define VCE_VCPU_CACHE_SIZE0 0x20028
|
||||
#define VCE_VCPU_CACHE_OFFSET1 0x2002c
|
||||
#define VCE_VCPU_CACHE_SIZE1 0x20030
|
||||
#define VCE_VCPU_CACHE_OFFSET2 0x20034
|
||||
#define VCE_VCPU_CACHE_SIZE2 0x20038
|
||||
#define VCE_SOFT_RESET 0x20120
|
||||
#define VCE_ECPU_SOFT_RESET (1 << 0)
|
||||
#define VCE_FME_SOFT_RESET (1 << 2)
|
||||
#define VCE_RB_BASE_LO2 0x2016c
|
||||
#define VCE_RB_BASE_HI2 0x20170
|
||||
#define VCE_RB_SIZE2 0x20174
|
||||
#define VCE_RB_RPTR2 0x20178
|
||||
#define VCE_RB_WPTR2 0x2017c
|
||||
#define VCE_RB_BASE_LO 0x20180
|
||||
#define VCE_RB_BASE_HI 0x20184
|
||||
#define VCE_RB_SIZE 0x20188
|
||||
#define VCE_RB_RPTR 0x2018c
|
||||
#define VCE_RB_WPTR 0x20190
|
||||
#define VCE_CLOCK_GATING_A 0x202f8
|
||||
#define VCE_CLOCK_GATING_B 0x202fc
|
||||
#define VCE_UENC_CLOCK_GATING 0x205bc
|
||||
#define VCE_UENC_REG_CLOCK_GATING 0x205c0
|
||||
#define VCE_FW_REG_STATUS 0x20e10
|
||||
# define VCE_FW_REG_STATUS_BUSY (1 << 0)
|
||||
# define VCE_FW_REG_STATUS_PASS (1 << 3)
|
||||
# define VCE_FW_REG_STATUS_DONE (1 << 11)
|
||||
#define VCE_LMI_FW_START_KEYSEL 0x20e18
|
||||
#define VCE_LMI_FW_PERIODIC_CTRL 0x20e20
|
||||
#define VCE_LMI_CTRL2 0x20e74
|
||||
#define VCE_LMI_CTRL 0x20e98
|
||||
#define VCE_LMI_VM_CTRL 0x20ea0
|
||||
#define VCE_LMI_SWAP_CNTL 0x20eb4
|
||||
#define VCE_LMI_SWAP_CNTL1 0x20eb8
|
||||
#define VCE_LMI_CACHE_CTRL 0x20ef4
|
||||
|
||||
#define VCE_CMD_NO_OP 0x00000000
|
||||
#define VCE_CMD_END 0x00000001
|
||||
#define VCE_CMD_IB 0x00000002
|
||||
#define VCE_CMD_FENCE 0x00000003
|
||||
#define VCE_CMD_TRAP 0x00000004
|
||||
#define VCE_CMD_IB_AUTO 0x00000005
|
||||
#define VCE_CMD_SEMAPHORE 0x00000006
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -0,0 +1,187 @@
|
|||
/*
|
||||
* Copyright 2013 Advanced Micro Devices, Inc.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sub license, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||||
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||||
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial portions
|
||||
* of the Software.
|
||||
*
|
||||
* Authors: Christian König <christian.koenig@amd.com>
|
||||
*/
|
||||
|
||||
#include <linux/firmware.h>
|
||||
#include <drm/drmP.h>
|
||||
#include "radeon.h"
|
||||
#include "radeon_asic.h"
|
||||
#include "sid.h"
|
||||
|
||||
/**
|
||||
* vce_v1_0_get_rptr - get read pointer
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: radeon_ring pointer
|
||||
*
|
||||
* Returns the current hardware read pointer
|
||||
*/
|
||||
uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
|
||||
return RREG32(VCE_RB_RPTR);
|
||||
else
|
||||
return RREG32(VCE_RB_RPTR2);
|
||||
}
|
||||
|
||||
/**
|
||||
* vce_v1_0_get_wptr - get write pointer
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: radeon_ring pointer
|
||||
*
|
||||
* Returns the current hardware write pointer
|
||||
*/
|
||||
uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
|
||||
return RREG32(VCE_RB_WPTR);
|
||||
else
|
||||
return RREG32(VCE_RB_WPTR2);
|
||||
}
|
||||
|
||||
/**
|
||||
* vce_v1_0_set_wptr - set write pointer
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
* @ring: radeon_ring pointer
|
||||
*
|
||||
* Commits the write pointer to the hardware
|
||||
*/
|
||||
void vce_v1_0_set_wptr(struct radeon_device *rdev,
|
||||
struct radeon_ring *ring)
|
||||
{
|
||||
if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
|
||||
WREG32(VCE_RB_WPTR, ring->wptr);
|
||||
else
|
||||
WREG32(VCE_RB_WPTR2, ring->wptr);
|
||||
}
|
||||
|
||||
/**
|
||||
* vce_v1_0_start - start VCE block
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* Setup and start the VCE block
|
||||
*/
|
||||
int vce_v1_0_start(struct radeon_device *rdev)
|
||||
{
|
||||
struct radeon_ring *ring;
|
||||
int i, j, r;
|
||||
|
||||
/* set BUSY flag */
|
||||
WREG32_P(VCE_STATUS, 1, ~1);
|
||||
|
||||
ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
|
||||
WREG32(VCE_RB_RPTR, ring->rptr);
|
||||
WREG32(VCE_RB_WPTR, ring->wptr);
|
||||
WREG32(VCE_RB_BASE_LO, ring->gpu_addr);
|
||||
WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
|
||||
WREG32(VCE_RB_SIZE, ring->ring_size / 4);
|
||||
|
||||
ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
|
||||
WREG32(VCE_RB_RPTR2, ring->rptr);
|
||||
WREG32(VCE_RB_WPTR2, ring->wptr);
|
||||
WREG32(VCE_RB_BASE_LO2, ring->gpu_addr);
|
||||
WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
|
||||
WREG32(VCE_RB_SIZE2, ring->ring_size / 4);
|
||||
|
||||
WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN);
|
||||
|
||||
WREG32_P(VCE_SOFT_RESET,
|
||||
VCE_ECPU_SOFT_RESET |
|
||||
VCE_FME_SOFT_RESET, ~(
|
||||
VCE_ECPU_SOFT_RESET |
|
||||
VCE_FME_SOFT_RESET));
|
||||
|
||||
mdelay(100);
|
||||
|
||||
WREG32_P(VCE_SOFT_RESET, 0, ~(
|
||||
VCE_ECPU_SOFT_RESET |
|
||||
VCE_FME_SOFT_RESET));
|
||||
|
||||
for (i = 0; i < 10; ++i) {
|
||||
uint32_t status;
|
||||
for (j = 0; j < 100; ++j) {
|
||||
status = RREG32(VCE_STATUS);
|
||||
if (status & 2)
|
||||
break;
|
||||
mdelay(10);
|
||||
}
|
||||
r = 0;
|
||||
if (status & 2)
|
||||
break;
|
||||
|
||||
DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
|
||||
WREG32_P(VCE_SOFT_RESET, VCE_ECPU_SOFT_RESET, ~VCE_ECPU_SOFT_RESET);
|
||||
mdelay(10);
|
||||
WREG32_P(VCE_SOFT_RESET, 0, ~VCE_ECPU_SOFT_RESET);
|
||||
mdelay(10);
|
||||
r = -1;
|
||||
}
|
||||
|
||||
/* clear BUSY flag */
|
||||
WREG32_P(VCE_STATUS, 0, ~1);
|
||||
|
||||
if (r) {
|
||||
DRM_ERROR("VCE not responding, giving up!!!\n");
|
||||
return r;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int vce_v1_0_init(struct radeon_device *rdev)
|
||||
{
|
||||
struct radeon_ring *ring;
|
||||
int r;
|
||||
|
||||
r = vce_v1_0_start(rdev);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
|
||||
ring->ready = true;
|
||||
r = radeon_ring_test(rdev, TN_RING_TYPE_VCE1_INDEX, ring);
|
||||
if (r) {
|
||||
ring->ready = false;
|
||||
return r;
|
||||
}
|
||||
|
||||
ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
|
||||
ring->ready = true;
|
||||
r = radeon_ring_test(rdev, TN_RING_TYPE_VCE2_INDEX, ring);
|
||||
if (r) {
|
||||
ring->ready = false;
|
||||
return r;
|
||||
}
|
||||
|
||||
DRM_INFO("VCE initialized successfully.\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Copyright 2013 Advanced Micro Devices, Inc.
|
||||
* All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the
|
||||
* "Software"), to deal in the Software without restriction, including
|
||||
* without limitation the rights to use, copy, modify, merge, publish,
|
||||
* distribute, sub license, and/or sell copies of the Software, and to
|
||||
* permit persons to whom the Software is furnished to do so, subject to
|
||||
* the following conditions:
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
|
||||
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
|
||||
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
|
||||
* USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* The above copyright notice and this permission notice (including the
|
||||
* next paragraph) shall be included in all copies or substantial portions
|
||||
* of the Software.
|
||||
*
|
||||
* Authors: Christian König <christian.koenig@amd.com>
|
||||
*/
|
||||
|
||||
#include <linux/firmware.h>
|
||||
#include <drm/drmP.h>
|
||||
#include "radeon.h"
|
||||
#include "radeon_asic.h"
|
||||
#include "cikd.h"
|
||||
|
||||
int vce_v2_0_resume(struct radeon_device *rdev)
|
||||
{
|
||||
uint64_t addr = rdev->vce.gpu_addr;
|
||||
uint32_t size;
|
||||
|
||||
WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16));
|
||||
WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000);
|
||||
WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F);
|
||||
WREG32(VCE_CLOCK_GATING_B, 0xf7);
|
||||
|
||||
WREG32(VCE_LMI_CTRL, 0x00398000);
|
||||
WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1);
|
||||
WREG32(VCE_LMI_SWAP_CNTL, 0);
|
||||
WREG32(VCE_LMI_SWAP_CNTL1, 0);
|
||||
WREG32(VCE_LMI_VM_CTRL, 0);
|
||||
|
||||
size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);
|
||||
WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
|
||||
WREG32(VCE_VCPU_CACHE_SIZE0, size);
|
||||
|
||||
addr += size;
|
||||
size = RADEON_VCE_STACK_SIZE;
|
||||
WREG32(VCE_VCPU_CACHE_OFFSET1, addr & 0x7fffffff);
|
||||
WREG32(VCE_VCPU_CACHE_SIZE1, size);
|
||||
|
||||
addr += size;
|
||||
size = RADEON_VCE_HEAP_SIZE;
|
||||
WREG32(VCE_VCPU_CACHE_OFFSET2, addr & 0x7fffffff);
|
||||
WREG32(VCE_VCPU_CACHE_SIZE2, size);
|
||||
|
||||
WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100);
|
||||
|
||||
WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN,
|
||||
~VCE_SYS_INT_TRAP_INTERRUPT_EN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -919,6 +919,7 @@ struct drm_radeon_gem_va {
|
|||
#define RADEON_CS_RING_COMPUTE 1
|
||||
#define RADEON_CS_RING_DMA 2
|
||||
#define RADEON_CS_RING_UVD 3
|
||||
#define RADEON_CS_RING_VCE 4
|
||||
/* The third dword of RADEON_CHUNK_ID_FLAGS is a sint32 that sets the priority */
|
||||
/* 0 = normal, + = higher priority, - = lower priority */
|
||||
|
||||
|
|
|
|||
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